1 //===---------------------------------------------------------------------===//
2 // Random ideas for the X86 backend.
3 //===---------------------------------------------------------------------===//
5 Add a MUL2U and MUL2S nodes to represent a multiply that returns both the
6 Hi and Lo parts (combination of MUL and MULH[SU] into one node). Add this to
7 X86, & make the dag combiner produce it when needed. This will eliminate one
8 imul from the code generated for:
10 long long test(long long X, long long Y) { return X*Y; }
12 by using the EAX result from the mul. We should add a similar node for
17 long long test(int X, int Y) { return (long long)X*Y; }
19 ... which should only be one imul instruction.
21 //===---------------------------------------------------------------------===//
23 This should be one DIV/IDIV instruction, not a libcall:
25 unsigned test(unsigned long long X, unsigned Y) {
29 This can be done trivially with a custom legalizer. What about overflow
30 though? http://gcc.gnu.org/bugzilla/show_bug.cgi?id=14224
32 //===---------------------------------------------------------------------===//
34 Some targets (e.g. athlons) prefer freep to fstp ST(0):
35 http://gcc.gnu.org/ml/gcc-patches/2004-04/msg00659.html
37 //===---------------------------------------------------------------------===//
39 This should use fiadd on chips where it is profitable:
40 double foo(double P, int *I) { return P+*I; }
42 //===---------------------------------------------------------------------===//
44 The FP stackifier needs to be global. Also, it should handle simple permutates
45 to reduce number of shuffle instructions, e.g. turning:
58 http://gcc.gnu.org/ml/gcc-patches/2004-11/msg02410.html
61 //===---------------------------------------------------------------------===//
63 Improvements to the multiply -> shift/add algorithm:
64 http://gcc.gnu.org/ml/gcc-patches/2004-08/msg01590.html
66 //===---------------------------------------------------------------------===//
68 Improve code like this (occurs fairly frequently, e.g. in LLVM):
69 long long foo(int x) { return 1LL << x; }
71 http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01109.html
72 http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01128.html
73 http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01136.html
75 Another useful one would be ~0ULL >> X and ~0ULL << X.
77 //===---------------------------------------------------------------------===//
80 _Bool f(_Bool a) { return a!=1; }
87 //===---------------------------------------------------------------------===//
91 1. Dynamic programming based approach when compile time if not an
93 2. Code duplication (addressing mode) during isel.
94 3. Other ideas from "Register-Sensitive Selection, Duplication, and
95 Sequencing of Instructions".
96 4. Scheduling for reduced register pressure. E.g. "Minimum Register
97 Instruction Sequence Problem: Revisiting Optimal Code Generation for DAGs"
98 and other related papers.
99 http://citeseer.ist.psu.edu/govindarajan01minimum.html
101 //===---------------------------------------------------------------------===//
103 Should we promote i16 to i32 to avoid partial register update stalls?
105 //===---------------------------------------------------------------------===//
107 Leave any_extend as pseudo instruction and hint to register
108 allocator. Delay codegen until post register allocation.
110 //===---------------------------------------------------------------------===//
112 Add a target specific hook to DAG combiner to handle SINT_TO_FP and
113 FP_TO_SINT when the source operand is already in memory.
115 //===---------------------------------------------------------------------===//
117 Model X86 EFLAGS as a real register to avoid redudant cmp / test. e.g.
121 testb %al, %al # unnecessary
124 //===---------------------------------------------------------------------===//
126 Count leading zeros and count trailing zeros:
128 int clz(int X) { return __builtin_clz(X); }
129 int ctz(int X) { return __builtin_ctz(X); }
131 $ gcc t.c -S -o - -O3 -fomit-frame-pointer -masm=intel
133 bsr %eax, DWORD PTR [%esp+4]
137 bsf %eax, DWORD PTR [%esp+4]
140 however, check that these are defined for 0 and 32. Our intrinsics are, GCC's
143 //===---------------------------------------------------------------------===//
145 Use push/pop instructions in prolog/epilog sequences instead of stores off
146 ESP (certain code size win, perf win on some [which?] processors).
148 //===---------------------------------------------------------------------===//
150 Only use inc/neg/not instructions on processors where they are faster than
151 add/sub/xor. They are slower on the P4 due to only updating some processor
154 //===---------------------------------------------------------------------===//
156 Open code rint,floor,ceil,trunc:
157 http://gcc.gnu.org/ml/gcc-patches/2004-08/msg02006.html
158 http://gcc.gnu.org/ml/gcc-patches/2004-08/msg02011.html
160 //===---------------------------------------------------------------------===//
162 Combine: a = sin(x), b = cos(x) into a,b = sincos(x).
164 Expand these to calls of sin/cos and stores:
165 double sincos(double x, double *sin, double *cos);
166 float sincosf(float x, float *sin, float *cos);
167 long double sincosl(long double x, long double *sin, long double *cos);
169 Doing so could allow SROA of the destination pointers. See also:
170 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=17687
172 //===---------------------------------------------------------------------===//
174 The instruction selector sometimes misses folding a load into a compare. The
175 pattern is written as (cmp reg, (load p)). Because the compare isn't
176 commutative, it is not matched with the load on both sides. The dag combiner
177 should be made smart enough to cannonicalize the load into the RHS of a compare
178 when it can invert the result of the compare for free.
180 //===---------------------------------------------------------------------===//
182 LSR should be turned on for the X86 backend and tuned to take advantage of its
185 //===---------------------------------------------------------------------===//
187 When compiled with unsafemath enabled, "main" should enable SSE DAZ mode and
188 other fast SSE modes.
190 //===---------------------------------------------------------------------===//
192 Think about doing i64 math in SSE regs.
194 //===---------------------------------------------------------------------===//
196 The DAG Isel doesn't fold the loads into the adds in this testcase. The
197 pattern selector does. This is because the chain value of the load gets
198 selected first, and the loads aren't checking to see if they are only used by
203 int %test(int* %x, int* %y, int* %z) {
236 This is bad for register pressure, though the dag isel is producing a
239 //===---------------------------------------------------------------------===//
241 This testcase should have no SSE instructions in it, and only one load from
244 double %test3(bool %B) {
245 %C = select bool %B, double 123.412, double 523.01123123
249 Currently, the select is being lowered, which prevents the dag combiner from
250 turning 'select (load CPI1), (load CPI2)' -> 'load (select CPI1, CPI2)'
252 The pattern isel got this one right.
254 //===---------------------------------------------------------------------===//
256 We need to lower switch statements to tablejumps when appropriate instead of
257 always into binary branch trees.
259 //===---------------------------------------------------------------------===//
261 SSE doesn't have [mem] op= reg instructions. If we have an SSE instruction
266 and the register allocator decides to spill X, it is cheaper to emit this as:
277 ..and this uses one fewer register (so this should be done at load folding
278 time, not at spiller time). *Note* however that this can only be done
279 if Y is dead. Here's a testcase:
281 %.str_3 = external global [15 x sbyte] ; <[15 x sbyte]*> [#uses=0]
282 implementation ; Functions:
283 declare void %printf(int, ...)
287 no_exit.i7: ; preds = %no_exit.i7, %build_tree.exit
288 %tmp.0.1.0.i9 = phi double [ 0.000000e+00, %build_tree.exit ], [ %tmp.34.i18, %no_exit.i7 ] ; <double> [#uses=1]
289 %tmp.0.0.0.i10 = phi double [ 0.000000e+00, %build_tree.exit ], [ %tmp.28.i16, %no_exit.i7 ] ; <double> [#uses=1]
290 %tmp.28.i16 = add double %tmp.0.0.0.i10, 0.000000e+00
291 %tmp.34.i18 = add double %tmp.0.1.0.i9, 0.000000e+00
292 br bool false, label %Compute_Tree.exit23, label %no_exit.i7
293 Compute_Tree.exit23: ; preds = %no_exit.i7
294 tail call void (int, ...)* %printf( int 0 )
295 store double %tmp.34.i18, double* null
304 *** movsd %XMM2, QWORD PTR [%ESP + 8]
305 *** addsd %XMM2, %XMM1
306 *** movsd QWORD PTR [%ESP + 8], %XMM2
307 jmp .BBmain_1 # no_exit.i7
309 This is a bugpoint reduced testcase, which is why the testcase doesn't make
310 much sense (e.g. its an infinite loop). :)
312 //===---------------------------------------------------------------------===//
314 None of the FPStack instructions are handled in
315 X86RegisterInfo::foldMemoryOperand, which prevents the spiller from
316 folding spill code into the instructions.
318 //===---------------------------------------------------------------------===//
320 In many cases, LLVM generates code like this:
329 on some processors (which ones?), it is more efficient to do this:
338 Doing this correctly is tricky though, as the xor clobbers the flags.
340 //===---------------------------------------------------------------------===//
342 We should generate 'test' instead of 'cmp' in various cases, e.g.:
345 %Y = shl int %X, ubyte 1
355 This may just be a matter of using 'test' to write bigger patterns for X86cmp.
357 //===---------------------------------------------------------------------===//
359 Evaluate whether using movapd for SSE reg-reg moves is faster than using
360 movsd/movss for them. It may eliminate false partial register dependences by
361 writing the whole result register.
363 //===---------------------------------------------------------------------===//
365 SSE should implement 'select_cc' using 'emulated conditional moves' that use
366 pcmp/pand/pandn/por to do a selection instead of a conditional branch:
368 double %X(double %Y, double %Z, double %A, double %B) {
369 %C = setlt double %A, %B
370 %z = add double %Z, 0.0 ;; select operand is not a load
371 %D = select bool %C, double %Y, double %z
380 addsd 24(%esp), %xmm0
381 movsd 32(%esp), %xmm1
382 movsd 16(%esp), %xmm2
383 ucomisd 40(%esp), %xmm1
393 //===---------------------------------------------------------------------===//
395 The x86 backend currently supports dynamic-no-pic. Need to add asm
396 printer support for static and PIC.
398 //===---------------------------------------------------------------------===//
400 We should generate bts/btr/etc instructions on targets where they are cheap or
401 when codesize is important. e.g., for:
403 void setbit(int *target, int bit) {
404 *target |= (1 << bit);
406 void clearbit(int *target, int bit) {
407 *target &= ~(1 << bit);
410 //===---------------------------------------------------------------------===//
412 Easy: Global addresses are not always allowed as immediates. For this:
414 int dst = 0; int *ptr = 0;
415 void foo() { ptr = &dst; }
424 When: "movl $_dst, _ptr" is sufficient.
426 //===---------------------------------------------------------------------===//
428 Use fisttp to do FP to integer conversion whenever it is available.
430 //===---------------------------------------------------------------------===//
432 Instead of the following for memset char*, 1, 10:
434 movl $16843009, 4(%edx)
435 movl $16843009, (%edx)
438 It might be better to generate
445 when we can spare a register. It reduces code size.