1 //===---------------------------------------------------------------------===//
2 // Random ideas for the X86 backend.
3 //===---------------------------------------------------------------------===//
5 Add a MUL2U and MUL2S nodes to represent a multiply that returns both the
6 Hi and Lo parts (combination of MUL and MULH[SU] into one node). Add this to
7 X86, & make the dag combiner produce it when needed. This will eliminate one
8 imul from the code generated for:
10 long long test(long long X, long long Y) { return X*Y; }
12 by using the EAX result from the mul. We should add a similar node for
17 long long test(int X, int Y) { return (long long)X*Y; }
19 ... which should only be one imul instruction.
21 //===---------------------------------------------------------------------===//
23 This should be one DIV/IDIV instruction, not a libcall:
25 unsigned test(unsigned long long X, unsigned Y) {
29 This can be done trivially with a custom legalizer. What about overflow
30 though? http://gcc.gnu.org/bugzilla/show_bug.cgi?id=14224
32 //===---------------------------------------------------------------------===//
34 Some targets (e.g. athlons) prefer freep to fstp ST(0):
35 http://gcc.gnu.org/ml/gcc-patches/2004-04/msg00659.html
37 //===---------------------------------------------------------------------===//
39 This should use fiadd on chips where it is profitable:
40 double foo(double P, int *I) { return P+*I; }
42 We have fiadd patterns now but the followings have the same cost and
43 complexity. We need a way to specify the later is more profitable.
45 def FpADD32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW,
46 [(set RFP:$dst, (fadd RFP:$src1,
47 (extloadf64f32 addr:$src2)))]>;
48 // ST(0) = ST(0) + [mem32]
50 def FpIADD32m : FpI<(ops RFP:$dst, RFP:$src1, i32mem:$src2), OneArgFPRW,
51 [(set RFP:$dst, (fadd RFP:$src1,
52 (X86fild addr:$src2, i32)))]>;
53 // ST(0) = ST(0) + [mem32int]
55 //===---------------------------------------------------------------------===//
57 The FP stackifier needs to be global. Also, it should handle simple permutates
58 to reduce number of shuffle instructions, e.g. turning:
71 http://gcc.gnu.org/ml/gcc-patches/2004-11/msg02410.html
74 //===---------------------------------------------------------------------===//
76 Improvements to the multiply -> shift/add algorithm:
77 http://gcc.gnu.org/ml/gcc-patches/2004-08/msg01590.html
79 //===---------------------------------------------------------------------===//
81 Improve code like this (occurs fairly frequently, e.g. in LLVM):
82 long long foo(int x) { return 1LL << x; }
84 http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01109.html
85 http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01128.html
86 http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01136.html
88 Another useful one would be ~0ULL >> X and ~0ULL << X.
90 //===---------------------------------------------------------------------===//
93 _Bool f(_Bool a) { return a!=1; }
100 //===---------------------------------------------------------------------===//
104 1. Dynamic programming based approach when compile time if not an
106 2. Code duplication (addressing mode) during isel.
107 3. Other ideas from "Register-Sensitive Selection, Duplication, and
108 Sequencing of Instructions".
109 4. Scheduling for reduced register pressure. E.g. "Minimum Register
110 Instruction Sequence Problem: Revisiting Optimal Code Generation for DAGs"
111 and other related papers.
112 http://citeseer.ist.psu.edu/govindarajan01minimum.html
114 //===---------------------------------------------------------------------===//
116 Should we promote i16 to i32 to avoid partial register update stalls?
118 //===---------------------------------------------------------------------===//
120 Leave any_extend as pseudo instruction and hint to register
121 allocator. Delay codegen until post register allocation.
123 //===---------------------------------------------------------------------===//
125 Add a target specific hook to DAG combiner to handle SINT_TO_FP and
126 FP_TO_SINT when the source operand is already in memory.
128 //===---------------------------------------------------------------------===//
130 Model X86 EFLAGS as a real register to avoid redudant cmp / test. e.g.
134 testb %al, %al # unnecessary
137 //===---------------------------------------------------------------------===//
139 Count leading zeros and count trailing zeros:
141 int clz(int X) { return __builtin_clz(X); }
142 int ctz(int X) { return __builtin_ctz(X); }
144 $ gcc t.c -S -o - -O3 -fomit-frame-pointer -masm=intel
146 bsr %eax, DWORD PTR [%esp+4]
150 bsf %eax, DWORD PTR [%esp+4]
153 however, check that these are defined for 0 and 32. Our intrinsics are, GCC's
156 //===---------------------------------------------------------------------===//
158 Use push/pop instructions in prolog/epilog sequences instead of stores off
159 ESP (certain code size win, perf win on some [which?] processors).
160 Also, it appears icc use push for parameter passing. Need to investigate.
162 //===---------------------------------------------------------------------===//
164 Only use inc/neg/not instructions on processors where they are faster than
165 add/sub/xor. They are slower on the P4 due to only updating some processor
168 //===---------------------------------------------------------------------===//
170 Open code rint,floor,ceil,trunc:
171 http://gcc.gnu.org/ml/gcc-patches/2004-08/msg02006.html
172 http://gcc.gnu.org/ml/gcc-patches/2004-08/msg02011.html
174 //===---------------------------------------------------------------------===//
176 Combine: a = sin(x), b = cos(x) into a,b = sincos(x).
178 Expand these to calls of sin/cos and stores:
179 double sincos(double x, double *sin, double *cos);
180 float sincosf(float x, float *sin, float *cos);
181 long double sincosl(long double x, long double *sin, long double *cos);
183 Doing so could allow SROA of the destination pointers. See also:
184 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=17687
186 //===---------------------------------------------------------------------===//
188 The instruction selector sometimes misses folding a load into a compare. The
189 pattern is written as (cmp reg, (load p)). Because the compare isn't
190 commutative, it is not matched with the load on both sides. The dag combiner
191 should be made smart enough to cannonicalize the load into the RHS of a compare
192 when it can invert the result of the compare for free.
194 //===---------------------------------------------------------------------===//
196 LSR should be turned on for the X86 backend and tuned to take advantage of its
199 //===---------------------------------------------------------------------===//
201 When compiled with unsafemath enabled, "main" should enable SSE DAZ mode and
202 other fast SSE modes.
204 //===---------------------------------------------------------------------===//
206 Think about doing i64 math in SSE regs.
208 //===---------------------------------------------------------------------===//
210 The DAG Isel doesn't fold the loads into the adds in this testcase. The
211 pattern selector does. This is because the chain value of the load gets
212 selected first, and the loads aren't checking to see if they are only used by
217 int %test(int* %x, int* %y, int* %z) {
250 This is bad for register pressure, though the dag isel is producing a
253 //===---------------------------------------------------------------------===//
255 This testcase should have no SSE instructions in it, and only one load from
258 double %test3(bool %B) {
259 %C = select bool %B, double 123.412, double 523.01123123
263 Currently, the select is being lowered, which prevents the dag combiner from
264 turning 'select (load CPI1), (load CPI2)' -> 'load (select CPI1, CPI2)'
266 The pattern isel got this one right.
268 //===---------------------------------------------------------------------===//
270 We need to lower switch statements to tablejumps when appropriate instead of
271 always into binary branch trees.
273 //===---------------------------------------------------------------------===//
275 SSE doesn't have [mem] op= reg instructions. If we have an SSE instruction
280 and the register allocator decides to spill X, it is cheaper to emit this as:
291 ..and this uses one fewer register (so this should be done at load folding
292 time, not at spiller time). *Note* however that this can only be done
293 if Y is dead. Here's a testcase:
295 %.str_3 = external global [15 x sbyte] ; <[15 x sbyte]*> [#uses=0]
296 implementation ; Functions:
297 declare void %printf(int, ...)
301 no_exit.i7: ; preds = %no_exit.i7, %build_tree.exit
302 %tmp.0.1.0.i9 = phi double [ 0.000000e+00, %build_tree.exit ], [ %tmp.34.i18, %no_exit.i7 ] ; <double> [#uses=1]
303 %tmp.0.0.0.i10 = phi double [ 0.000000e+00, %build_tree.exit ], [ %tmp.28.i16, %no_exit.i7 ] ; <double> [#uses=1]
304 %tmp.28.i16 = add double %tmp.0.0.0.i10, 0.000000e+00
305 %tmp.34.i18 = add double %tmp.0.1.0.i9, 0.000000e+00
306 br bool false, label %Compute_Tree.exit23, label %no_exit.i7
307 Compute_Tree.exit23: ; preds = %no_exit.i7
308 tail call void (int, ...)* %printf( int 0 )
309 store double %tmp.34.i18, double* null
318 *** movsd %XMM2, QWORD PTR [%ESP + 8]
319 *** addsd %XMM2, %XMM1
320 *** movsd QWORD PTR [%ESP + 8], %XMM2
321 jmp .BBmain_1 # no_exit.i7
323 This is a bugpoint reduced testcase, which is why the testcase doesn't make
324 much sense (e.g. its an infinite loop). :)
326 //===---------------------------------------------------------------------===//
328 None of the FPStack instructions are handled in
329 X86RegisterInfo::foldMemoryOperand, which prevents the spiller from
330 folding spill code into the instructions.
332 //===---------------------------------------------------------------------===//
334 In many cases, LLVM generates code like this:
343 on some processors (which ones?), it is more efficient to do this:
352 Doing this correctly is tricky though, as the xor clobbers the flags.
354 //===---------------------------------------------------------------------===//
356 We should generate 'test' instead of 'cmp' in various cases, e.g.:
359 %Y = shl int %X, ubyte 1
369 This may just be a matter of using 'test' to write bigger patterns for X86cmp.
371 //===---------------------------------------------------------------------===//
373 SSE should implement 'select_cc' using 'emulated conditional moves' that use
374 pcmp/pand/pandn/por to do a selection instead of a conditional branch:
376 double %X(double %Y, double %Z, double %A, double %B) {
377 %C = setlt double %A, %B
378 %z = add double %Z, 0.0 ;; select operand is not a load
379 %D = select bool %C, double %Y, double %z
388 addsd 24(%esp), %xmm0
389 movsd 32(%esp), %xmm1
390 movsd 16(%esp), %xmm2
391 ucomisd 40(%esp), %xmm1
401 //===---------------------------------------------------------------------===//
403 We should generate bts/btr/etc instructions on targets where they are cheap or
404 when codesize is important. e.g., for:
406 void setbit(int *target, int bit) {
407 *target |= (1 << bit);
409 void clearbit(int *target, int bit) {
410 *target &= ~(1 << bit);
413 //===---------------------------------------------------------------------===//
415 Instead of the following for memset char*, 1, 10:
417 movl $16843009, 4(%edx)
418 movl $16843009, (%edx)
421 It might be better to generate
428 when we can spare a register. It reduces code size.
430 //===---------------------------------------------------------------------===//
432 It's not clear whether we should use pxor or xorps / xorpd to clear XMM
433 registers. The choice may depend on subtarget information. We should do some
434 more experiments on different x86 machines.
436 //===---------------------------------------------------------------------===//
438 Evaluate what the best way to codegen sdiv X, (2^C) is. For X/8, we currently
455 GCC knows several different ways to codegen it, one of which is this:
465 which is probably slower, but it's interesting at least :)
467 //===---------------------------------------------------------------------===//
469 Currently the x86 codegen isn't very good at mixing SSE and FPStack
472 unsigned int foo(double x) { return x; }
476 movsd 24(%esp), %xmm0
484 This will be solved when we go to a dynamic programming based isel.
486 //===---------------------------------------------------------------------===//
488 Should generate min/max for stuff like:
490 void minf(float a, float b, float *X) {
494 Make use of floating point min / max instructions. Perhaps introduce ISD::FMIN
495 and ISD::FMAX node types?
497 //===---------------------------------------------------------------------===//
499 The first BB of this code:
503 %V = call bool %foo()
504 br bool %V, label %T, label %F
521 It would be better to emit "cmp %al, 1" than a xor and test.
523 //===---------------------------------------------------------------------===//
525 Enable X86InstrInfo::convertToThreeAddress().
527 //===---------------------------------------------------------------------===//
529 Investigate whether it is better to codegen the following
531 %tmp.1 = mul int %x, 9
535 leal (%eax,%eax,8), %eax
537 as opposed to what llc is currently generating:
539 imull $9, 4(%esp), %eax
541 Currently the load folding imull has a higher complexity than the LEA32 pattern.
543 //===---------------------------------------------------------------------===//
545 Lower memcpy / memset to a series of SSE 128 bit move instructions when it's
548 //===---------------------------------------------------------------------===//
550 Teach the coalescer to commute 2-addr instructions, allowing us to eliminate
551 the reg-reg copy in this example:
553 float foo(int *x, float *y, unsigned c) {
556 for (i = 0; i < c; i++) {
557 float xx = (float)x[i];
566 cvtsi2ss %XMM0, DWORD PTR [%EDX + 4*%ESI]
567 mulss %XMM0, DWORD PTR [%EAX + 4*%ESI]
571 **** movaps %XMM1, %XMM0
572 jb LBB_foo_3 # no_exit
574 //===---------------------------------------------------------------------===//
577 if (copysign(1.0, x) == copysign(1.0, y))
582 //===---------------------------------------------------------------------===//
584 Optimize this into something reasonable:
585 x * copysign(1.0, y) * copysign(1.0, z)
587 //===---------------------------------------------------------------------===//
589 Optimize copysign(x, *y) to use an integer load from y.
591 //===---------------------------------------------------------------------===//
593 %X = weak global int 0
596 %N = cast int %N to uint
597 %tmp.24 = setgt int %N, 0
598 br bool %tmp.24, label %no_exit, label %return
601 %indvar = phi uint [ 0, %entry ], [ %indvar.next, %no_exit ]
602 %i.0.0 = cast uint %indvar to int
603 volatile store int %i.0.0, int* %X
604 %indvar.next = add uint %indvar, 1
605 %exitcond = seteq uint %indvar.next, %N
606 br bool %exitcond, label %return, label %no_exit
620 jl LBB_foo_4 # return
621 LBB_foo_1: # no_exit.preheader
624 movl L_X$non_lazy_ptr, %edx
628 jne LBB_foo_2 # no_exit
629 LBB_foo_3: # return.loopexit
633 We should hoist "movl L_X$non_lazy_ptr, %edx" out of the loop after
634 remateralization is implemented. This can be accomplished with 1) a target
635 dependent LICM pass or 2) makeing SelectDAG represent the whole function.
637 //===---------------------------------------------------------------------===//
639 The following tests perform worse with LSR:
641 lambda, siod, optimizer-eval, ackermann, hash2, nestedloop, strcat, and Treesor.
643 //===---------------------------------------------------------------------===//
645 Teach the coalescer to coalesce vregs of different register classes. e.g. FR32 /
648 //===---------------------------------------------------------------------===//
656 Obviously it would have been better for the first mov (or any op) to store
657 directly %esp[0] if there are no other uses.
659 //===---------------------------------------------------------------------===//
661 Add more vector shuffle special cases using unpckhps and unpcklps.