1 //===---------------------------------------------------------------------===//
2 // Random ideas for the X86 backend.
3 //===---------------------------------------------------------------------===//
6 - Support for SSE4: http://www.intel.com/software/penryn
7 http://softwarecommunity.intel.com/isn/Downloads/Intel%20SSE4%20Programming%20Reference.pdf
11 //===---------------------------------------------------------------------===//
13 CodeGen/X86/lea-3.ll:test3 should be a single LEA, not a shift/move. The X86
14 backend knows how to three-addressify this shift, but it appears the register
15 allocator isn't even asking it to do so in this case. We should investigate
16 why this isn't happening, it could have significant impact on other important
17 cases for X86 as well.
19 //===---------------------------------------------------------------------===//
21 This should be one DIV/IDIV instruction, not a libcall:
23 unsigned test(unsigned long long X, unsigned Y) {
27 This can be done trivially with a custom legalizer. What about overflow
28 though? http://gcc.gnu.org/bugzilla/show_bug.cgi?id=14224
30 //===---------------------------------------------------------------------===//
32 Improvements to the multiply -> shift/add algorithm:
33 http://gcc.gnu.org/ml/gcc-patches/2004-08/msg01590.html
35 //===---------------------------------------------------------------------===//
37 Improve code like this (occurs fairly frequently, e.g. in LLVM):
38 long long foo(int x) { return 1LL << x; }
40 http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01109.html
41 http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01128.html
42 http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01136.html
44 Another useful one would be ~0ULL >> X and ~0ULL << X.
46 One better solution for 1LL << x is:
55 But that requires good 8-bit subreg support.
57 64-bit shifts (in general) expand to really bad code. Instead of using
58 cmovs, we should expand to a conditional branch like GCC produces.
60 //===---------------------------------------------------------------------===//
63 _Bool f(_Bool a) { return a!=1; }
70 //===---------------------------------------------------------------------===//
74 1. Dynamic programming based approach when compile time if not an
76 2. Code duplication (addressing mode) during isel.
77 3. Other ideas from "Register-Sensitive Selection, Duplication, and
78 Sequencing of Instructions".
79 4. Scheduling for reduced register pressure. E.g. "Minimum Register
80 Instruction Sequence Problem: Revisiting Optimal Code Generation for DAGs"
81 and other related papers.
82 http://citeseer.ist.psu.edu/govindarajan01minimum.html
84 //===---------------------------------------------------------------------===//
86 Should we promote i16 to i32 to avoid partial register update stalls?
88 //===---------------------------------------------------------------------===//
90 Leave any_extend as pseudo instruction and hint to register
91 allocator. Delay codegen until post register allocation.
92 Note. any_extend is now turned into an INSERT_SUBREG. We still need to teach
93 the coalescer how to deal with it though.
95 //===---------------------------------------------------------------------===//
97 Count leading zeros and count trailing zeros:
99 int clz(int X) { return __builtin_clz(X); }
100 int ctz(int X) { return __builtin_ctz(X); }
102 $ gcc t.c -S -o - -O3 -fomit-frame-pointer -masm=intel
104 bsr %eax, DWORD PTR [%esp+4]
108 bsf %eax, DWORD PTR [%esp+4]
111 however, check that these are defined for 0 and 32. Our intrinsics are, GCC's
114 Another example (use predsimplify to eliminate a select):
116 int foo (unsigned long j) {
118 return __builtin_ffs (j) - 1;
123 //===---------------------------------------------------------------------===//
125 It appears icc use push for parameter passing. Need to investigate.
127 //===---------------------------------------------------------------------===//
129 Only use inc/neg/not instructions on processors where they are faster than
130 add/sub/xor. They are slower on the P4 due to only updating some processor
133 //===---------------------------------------------------------------------===//
135 The instruction selector sometimes misses folding a load into a compare. The
136 pattern is written as (cmp reg, (load p)). Because the compare isn't
137 commutative, it is not matched with the load on both sides. The dag combiner
138 should be made smart enough to cannonicalize the load into the RHS of a compare
139 when it can invert the result of the compare for free.
141 //===---------------------------------------------------------------------===//
143 How about intrinsics? An example is:
144 *res = _mm_mulhi_epu16(*A, _mm_mul_epu32(*B, *C));
147 pmuludq (%eax), %xmm0
152 The transformation probably requires a X86 specific pass or a DAG combiner
153 target specific hook.
155 //===---------------------------------------------------------------------===//
157 In many cases, LLVM generates code like this:
166 on some processors (which ones?), it is more efficient to do this:
175 Doing this correctly is tricky though, as the xor clobbers the flags.
177 //===---------------------------------------------------------------------===//
179 We should generate bts/btr/etc instructions on targets where they are cheap or
180 when codesize is important. e.g., for:
182 void setbit(int *target, int bit) {
183 *target |= (1 << bit);
185 void clearbit(int *target, int bit) {
186 *target &= ~(1 << bit);
189 //===---------------------------------------------------------------------===//
191 Instead of the following for memset char*, 1, 10:
193 movl $16843009, 4(%edx)
194 movl $16843009, (%edx)
197 It might be better to generate
204 when we can spare a register. It reduces code size.
206 //===---------------------------------------------------------------------===//
208 Evaluate what the best way to codegen sdiv X, (2^C) is. For X/8, we currently
225 GCC knows several different ways to codegen it, one of which is this:
235 which is probably slower, but it's interesting at least :)
237 //===---------------------------------------------------------------------===//
239 The first BB of this code:
243 %V = call bool %foo()
244 br bool %V, label %T, label %F
261 It would be better to emit "cmp %al, 1" than a xor and test.
263 //===---------------------------------------------------------------------===//
265 We are currently lowering large (1MB+) memmove/memcpy to rep/stosl and rep/movsl
266 We should leave these as libcalls for everything over a much lower threshold,
267 since libc is hand tuned for medium and large mem ops (avoiding RFO for large
268 stores, TLB preheating, etc)
270 //===---------------------------------------------------------------------===//
272 Optimize this into something reasonable:
273 x * copysign(1.0, y) * copysign(1.0, z)
275 //===---------------------------------------------------------------------===//
277 Optimize copysign(x, *y) to use an integer load from y.
279 //===---------------------------------------------------------------------===//
281 %X = weak global int 0
284 %N = cast int %N to uint
285 %tmp.24 = setgt int %N, 0
286 br bool %tmp.24, label %no_exit, label %return
289 %indvar = phi uint [ 0, %entry ], [ %indvar.next, %no_exit ]
290 %i.0.0 = cast uint %indvar to int
291 volatile store int %i.0.0, int* %X
292 %indvar.next = add uint %indvar, 1
293 %exitcond = seteq uint %indvar.next, %N
294 br bool %exitcond, label %return, label %no_exit
308 jl LBB_foo_4 # return
309 LBB_foo_1: # no_exit.preheader
312 movl L_X$non_lazy_ptr, %edx
316 jne LBB_foo_2 # no_exit
317 LBB_foo_3: # return.loopexit
321 We should hoist "movl L_X$non_lazy_ptr, %edx" out of the loop after
322 remateralization is implemented. This can be accomplished with 1) a target
323 dependent LICM pass or 2) makeing SelectDAG represent the whole function.
325 //===---------------------------------------------------------------------===//
327 The following tests perform worse with LSR:
329 lambda, siod, optimizer-eval, ackermann, hash2, nestedloop, strcat, and Treesor.
331 //===---------------------------------------------------------------------===//
333 We are generating far worse code than gcc:
339 for (i = 0; i < N; i++) { X = i; Y = i*4; }
342 LBB1_1: #bb.preheader
346 movl L_X$non_lazy_ptr, %esi
350 movl L_Y$non_lazy_ptr, %edi
360 movl L_X$non_lazy_ptr-"L00000000001$pb"(%ebx), %esi
361 movl L_Y$non_lazy_ptr-"L00000000001$pb"(%ebx), %ecx
364 leal 0(,%edx,4), %eax
372 1. Lack of post regalloc LICM.
373 2. LSR unable to reused IV for a different type (i16 vs. i32) even though
374 the cast would be free.
376 //===---------------------------------------------------------------------===//
378 Teach the coalescer to coalesce vregs of different register classes. e.g. FR32 /
381 //===---------------------------------------------------------------------===//
389 Obviously it would have been better for the first mov (or any op) to store
390 directly %esp[0] if there are no other uses.
392 //===---------------------------------------------------------------------===//
394 Adding to the list of cmp / test poor codegen issues:
396 int test(__m128 *A, __m128 *B) {
397 if (_mm_comige_ss(*A, *B))
417 Note the setae, movzbl, cmpl, cmove can be replaced with a single cmovae. There
418 are a number of issues. 1) We are introducing a setcc between the result of the
419 intrisic call and select. 2) The intrinsic is expected to produce a i32 value
420 so a any extend (which becomes a zero extend) is added.
422 We probably need some kind of target DAG combine hook to fix this.
424 //===---------------------------------------------------------------------===//
426 We generate significantly worse code for this than GCC:
427 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=21150
428 http://gcc.gnu.org/bugzilla/attachment.cgi?id=8701
430 There is also one case we do worse on PPC.
432 //===---------------------------------------------------------------------===//
434 If shorter, we should use things like:
439 The former can also be used when the two-addressy nature of the 'and' would
440 require a copy to be inserted (in X86InstrInfo::convertToThreeAddress).
442 //===---------------------------------------------------------------------===//
446 typedef struct pair { float A, B; } pair;
447 void pairtest(pair P, float *FP) {
451 We currently generate this code with llvmgcc4:
463 we should be able to generate:
471 The issue is that llvmgcc4 is forcing the struct to memory, then passing it as
472 integer chunks. It does this so that structs like {short,short} are passed in
473 a single 32-bit integer stack slot. We should handle the safe cases above much
474 nicer, while still handling the hard cases.
476 While true in general, in this specific case we could do better by promoting
477 load int + bitcast to float -> load fload. This basically needs alignment info,
478 the code is already implemented (but disabled) in dag combine).
480 //===---------------------------------------------------------------------===//
482 Another instruction selector deficiency:
485 %tmp = load int (int)** %foo
486 %tmp = tail call int %tmp( int 3 )
492 movl L_foo$non_lazy_ptr, %eax
498 The current isel scheme will not allow the load to be folded in the call since
499 the load's chain result is read by the callseq_start.
501 //===---------------------------------------------------------------------===//
511 imull $3, 4(%esp), %eax
513 Perhaps this is what we really should generate is? Is imull three or four
514 cycles? Note: ICC generates this:
516 leal (%eax,%eax,2), %eax
518 The current instruction priority is based on pattern complexity. The former is
519 more "complex" because it folds a load so the latter will not be emitted.
521 Perhaps we should use AddedComplexity to give LEA32r a higher priority? We
522 should always try to match LEA first since the LEA matching code does some
523 estimate to determine whether the match is profitable.
525 However, if we care more about code size, then imull is better. It's two bytes
526 shorter than movl + leal.
528 //===---------------------------------------------------------------------===//
530 Implement CTTZ, CTLZ with bsf and bsr. GCC produces:
532 int ctz_(unsigned X) { return __builtin_ctz(X); }
533 int clz_(unsigned X) { return __builtin_clz(X); }
534 int ffs_(unsigned X) { return __builtin_ffs(X); }
550 //===---------------------------------------------------------------------===//
552 It appears gcc place string data with linkonce linkage in
553 .section __TEXT,__const_coal,coalesced instead of
554 .section __DATA,__const_coal,coalesced.
555 Take a look at darwin.h, there are other Darwin assembler directives that we
558 //===---------------------------------------------------------------------===//
560 int %foo(int* %a, int %t) {
564 cond_true: ; preds = %cond_true, %entry
565 %x.0.0 = phi int [ 0, %entry ], [ %tmp9, %cond_true ]
566 %t_addr.0.0 = phi int [ %t, %entry ], [ %tmp7, %cond_true ]
567 %tmp2 = getelementptr int* %a, int %x.0.0
568 %tmp3 = load int* %tmp2 ; <int> [#uses=1]
569 %tmp5 = add int %t_addr.0.0, %x.0.0 ; <int> [#uses=1]
570 %tmp7 = add int %tmp5, %tmp3 ; <int> [#uses=2]
571 %tmp9 = add int %x.0.0, 1 ; <int> [#uses=2]
572 %tmp = setgt int %tmp9, 39 ; <bool> [#uses=1]
573 br bool %tmp, label %bb12, label %cond_true
575 bb12: ; preds = %cond_true
579 is pessimized by -loop-reduce and -indvars
581 //===---------------------------------------------------------------------===//
583 u32 to float conversion improvement:
585 float uint32_2_float( unsigned u ) {
586 float fl = (int) (u & 0xffff);
587 float fh = (int) (u >> 16);
592 00000000 subl $0x04,%esp
593 00000003 movl 0x08(%esp,1),%eax
594 00000007 movl %eax,%ecx
595 00000009 shrl $0x10,%ecx
596 0000000c cvtsi2ss %ecx,%xmm0
597 00000010 andl $0x0000ffff,%eax
598 00000015 cvtsi2ss %eax,%xmm1
599 00000019 mulss 0x00000078,%xmm0
600 00000021 addss %xmm1,%xmm0
601 00000025 movss %xmm0,(%esp,1)
602 0000002a flds (%esp,1)
603 0000002d addl $0x04,%esp
606 //===---------------------------------------------------------------------===//
608 When using fastcc abi, align stack slot of argument of type double on 8 byte
609 boundary to improve performance.
611 //===---------------------------------------------------------------------===//
615 int f(int a, int b) {
616 if (a == 4 || a == 6)
628 //===---------------------------------------------------------------------===//
630 GCC's ix86_expand_int_movcc function (in i386.c) has a ton of interesting
631 simplifications for integer "x cmp y ? a : b". For example, instead of:
634 void f(int X, int Y) {
660 //===---------------------------------------------------------------------===//
662 Currently we don't have elimination of redundant stack manipulations. Consider
667 call fastcc void %test1( )
668 call fastcc void %test2( sbyte* cast (void ()* %test1 to sbyte*) )
672 declare fastcc void %test1()
674 declare fastcc void %test2(sbyte*)
677 This currently compiles to:
687 The add\sub pair is really unneeded here.
689 //===---------------------------------------------------------------------===//
691 We currently compile sign_extend_inreg into two shifts:
694 return (long)(signed char)X;
711 //===---------------------------------------------------------------------===//
713 Consider the expansion of:
715 uint %test3(uint %X) {
716 %tmp1 = rem uint %X, 255
720 Currently it compiles to:
723 movl $2155905153, %ecx
729 This could be "reassociated" into:
731 movl $2155905153, %eax
735 to avoid the copy. In fact, the existing two-address stuff would do this
736 except that mul isn't a commutative 2-addr instruction. I guess this has
737 to be done at isel time based on the #uses to mul?
739 //===---------------------------------------------------------------------===//
741 Make sure the instruction which starts a loop does not cross a cacheline
742 boundary. This requires knowning the exact length of each machine instruction.
743 That is somewhat complicated, but doable. Example 256.bzip2:
745 In the new trace, the hot loop has an instruction which crosses a cacheline
746 boundary. In addition to potential cache misses, this can't help decoding as I
747 imagine there has to be some kind of complicated decoder reset and realignment
748 to grab the bytes from the next cacheline.
750 532 532 0x3cfc movb (1809(%esp, %esi), %bl <<<--- spans 2 64 byte lines
751 942 942 0x3d03 movl %dh, (1809(%esp, %esi)
752 937 937 0x3d0a incl %esi
753 3 3 0x3d0b cmpb %bl, %dl
754 27 27 0x3d0d jnz 0x000062db <main+11707>
756 //===---------------------------------------------------------------------===//
758 In c99 mode, the preprocessor doesn't like assembly comments like #TRUNCATE.
760 //===---------------------------------------------------------------------===//
762 This could be a single 16-bit load.
765 if ((p[0] == 1) & (p[1] == 2)) return 1;
769 //===---------------------------------------------------------------------===//
771 We should inline lrintf and probably other libc functions.
773 //===---------------------------------------------------------------------===//
775 Start using the flags more. For example, compile:
777 int add_zf(int *x, int y, int a, int b) {
801 int add_zf(int *x, int y, int a, int b) {
825 //===---------------------------------------------------------------------===//
829 int foo(double X) { return isnan(X); }
840 the pxor is not needed, we could compare the value against itself.
842 //===---------------------------------------------------------------------===//
844 These two functions have identical effects:
846 unsigned int f(unsigned int i, unsigned int n) {++i; if (i == n) ++i; return i;}
847 unsigned int f2(unsigned int i, unsigned int n) {++i; i += i == n; return i;}
849 We currently compile them to:
857 jne LBB1_2 #UnifiedReturnBlock
861 LBB1_2: #UnifiedReturnBlock
871 leal 1(%ecx,%eax), %eax
874 both of which are inferior to GCC's:
892 //===---------------------------------------------------------------------===//
900 is currently compiled to:
911 It would be better to produce:
920 This can be applied to any no-return function call that takes no arguments etc.
921 Alternatively, the stack save/restore logic could be shrink-wrapped, producing
932 Both are useful in different situations. Finally, it could be shrink-wrapped
933 and tail called, like this:
940 pop %eax # realign stack.
943 Though this probably isn't worth it.
945 //===---------------------------------------------------------------------===//
947 We need to teach the codegen to convert two-address INC instructions to LEA
948 when the flags are dead (likewise dec). For example, on X86-64, compile:
950 int foo(int A, int B) {
969 ;; X's live range extends beyond the shift, so the register allocator
970 ;; cannot coalesce it with Y. Because of this, a copy needs to be
971 ;; emitted before the shift to save the register value before it is
972 ;; clobbered. However, this copy is not needed if the register
973 ;; allocator turns the shift into an LEA. This also occurs for ADD.
975 ; Check that the shift gets turned into an LEA.
976 ; RUN: llvm-upgrade < %s | llvm-as | llc -march=x86 -x86-asm-syntax=intel | \
977 ; RUN: not grep {mov E.X, E.X}
979 %G = external global int
981 int %test1(int %X, int %Y) {
983 volatile store int %Y, int* %G
984 volatile store int %Z, int* %G
989 %Z = add int %X, 1 ;; inc
990 volatile store int %Z, int* %G
994 //===---------------------------------------------------------------------===//
996 Sometimes it is better to codegen subtractions from a constant (e.g. 7-x) with
997 a neg instead of a sub instruction. Consider:
999 int test(char X) { return 7-X; }
1001 we currently produce:
1004 movsbl 4(%esp), %ecx
1008 We would use one fewer register if codegen'd as:
1010 movsbl 4(%esp), %eax
1015 Note that this isn't beneficial if the load can be folded into the sub. In
1016 this case, we want a sub:
1018 int test(int X) { return 7-X; }
1024 //===---------------------------------------------------------------------===//
1029 We get an implicit def on the undef side. If the phi is spilled, we then get:
1033 It should be possible to teach the x86 backend to "fold" the store into the
1034 implicitdef, which just deletes the implicit def.
1036 These instructions should go away:
1038 movaps %xmm1, 192(%esp)
1039 movaps %xmm1, 224(%esp)
1040 movaps %xmm1, 176(%esp)
1042 //===---------------------------------------------------------------------===//
1044 This is a "commutable two-address" register coallescing deficiency:
1046 define <4 x float> @test1(<4 x float> %V) {
1048 %tmp8 = shufflevector <4 x float> %V, <4 x float> undef,
1049 <4 x i32> < i32 3, i32 2, i32 1, i32 0 >
1050 %add = add <4 x float> %tmp8, %V
1051 ret <4 x float> %add
1057 pshufd $27, %xmm0, %xmm1
1065 pshufd $27, %xmm0, %xmm1
1069 //===---------------------------------------------------------------------===//
1071 Leaf functions that require one 4-byte spill slot have a prolog like this:
1077 and an epilog like this:
1082 It would be smaller, and potentially faster, to push eax on entry and to
1083 pop into a dummy register instead of using addl/subl of esp. Just don't pop
1084 into any return registers :)
1086 //===---------------------------------------------------------------------===//
1088 The X86 backend should fold (branch (or (setcc, setcc))) into multiple
1089 branches. We generate really poor code for:
1091 double testf(double a) {
1092 return a == 0.0 ? 0.0 : (a > 0.0 ? 1.0 : -1.0);
1095 For example, the entry BB is:
1100 movsd 24(%esp), %xmm1
1101 ucomisd %xmm0, %xmm1
1105 jne LBB1_5 # UnifiedReturnBlock
1109 it would be better to replace the last four instructions with:
1115 We also codegen the inner ?: into a diamond:
1117 cvtss2sd LCPI1_0(%rip), %xmm2
1118 cvtss2sd LCPI1_1(%rip), %xmm3
1119 ucomisd %xmm1, %xmm0
1120 ja LBB1_3 # cond_true
1127 We should sink the load into xmm3 into the LBB1_2 block. This should
1128 be pretty easy, and will nuke all the copies.
1130 //===---------------------------------------------------------------------===//
1133 #include <algorithm>
1134 inline std::pair<unsigned, bool> full_add(unsigned a, unsigned b)
1135 { return std::make_pair(a + b, a + b < a); }
1136 bool no_overflow(unsigned a, unsigned b)
1137 { return !full_add(a, b).second; }
1157 //===---------------------------------------------------------------------===//
1159 Re-materialize MOV32r0 etc. with xor instead of changing them to moves if the
1160 condition register is dead. xor reg reg is shorter than mov reg, #0.
1162 //===---------------------------------------------------------------------===//
1164 We aren't matching RMW instructions aggressively
1165 enough. Here's a reduced testcase (more in PR1160):
1167 define void @test(i32* %huge_ptr, i32* %target_ptr) {
1168 %A = load i32* %huge_ptr ; <i32> [#uses=1]
1169 %B = load i32* %target_ptr ; <i32> [#uses=1]
1170 %C = or i32 %A, %B ; <i32> [#uses=1]
1171 store i32 %C, i32* %target_ptr
1175 $ llvm-as < t.ll | llc -march=x86-64
1183 That should be something like:
1190 //===---------------------------------------------------------------------===//
1194 bb114.preheader: ; preds = %cond_next94
1195 %tmp231232 = sext i16 %tmp62 to i32 ; <i32> [#uses=1]
1196 %tmp233 = sub i32 32, %tmp231232 ; <i32> [#uses=1]
1197 %tmp245246 = sext i16 %tmp65 to i32 ; <i32> [#uses=1]
1198 %tmp252253 = sext i16 %tmp68 to i32 ; <i32> [#uses=1]
1199 %tmp254 = sub i32 32, %tmp252253 ; <i32> [#uses=1]
1200 %tmp553554 = bitcast i16* %tmp37 to i8* ; <i8*> [#uses=2]
1201 %tmp583584 = sext i16 %tmp98 to i32 ; <i32> [#uses=1]
1202 %tmp585 = sub i32 32, %tmp583584 ; <i32> [#uses=1]
1203 %tmp614615 = sext i16 %tmp101 to i32 ; <i32> [#uses=1]
1204 %tmp621622 = sext i16 %tmp104 to i32 ; <i32> [#uses=1]
1205 %tmp623 = sub i32 32, %tmp621622 ; <i32> [#uses=1]
1210 LBB3_5: # bb114.preheader
1211 movswl -68(%ebp), %eax
1213 movl %ecx, -80(%ebp)
1214 subl %eax, -80(%ebp)
1215 movswl -52(%ebp), %eax
1216 movl %ecx, -84(%ebp)
1217 subl %eax, -84(%ebp)
1218 movswl -70(%ebp), %eax
1219 movl %ecx, -88(%ebp)
1220 subl %eax, -88(%ebp)
1221 movswl -50(%ebp), %eax
1223 movl %ecx, -76(%ebp)
1224 movswl -42(%ebp), %eax
1225 movl %eax, -92(%ebp)
1226 movswl -66(%ebp), %eax
1227 movl %eax, -96(%ebp)
1230 This appears to be bad because the RA is not folding the store to the stack
1231 slot into the movl. The above instructions could be:
1236 This seems like a cross between remat and spill folding.
1238 This has redundant subtractions of %eax from a stack slot. However, %ecx doesn't
1239 change, so we could simply subtract %eax from %ecx first and then use %ecx (or
1242 //===---------------------------------------------------------------------===//
1246 cond_next603: ; preds = %bb493, %cond_true336, %cond_next599
1247 %v.21050.1 = phi i32 [ %v.21050.0, %cond_next599 ], [ %tmp344, %cond_true336 ], [ %v.2, %bb493 ] ; <i32> [#uses=1]
1248 %maxz.21051.1 = phi i32 [ %maxz.21051.0, %cond_next599 ], [ 0, %cond_true336 ], [ %maxz.2, %bb493 ] ; <i32> [#uses=2]
1249 %cnt.01055.1 = phi i32 [ %cnt.01055.0, %cond_next599 ], [ 0, %cond_true336 ], [ %cnt.0, %bb493 ] ; <i32> [#uses=2]
1250 %byteptr.9 = phi i8* [ %byteptr.12, %cond_next599 ], [ %byteptr.0, %cond_true336 ], [ %byteptr.10, %bb493 ] ; <i8*> [#uses=9]
1251 %bitptr.6 = phi i32 [ %tmp5571104.1, %cond_next599 ], [ %tmp4921049, %cond_true336 ], [ %bitptr.7, %bb493 ] ; <i32> [#uses=4]
1252 %source.5 = phi i32 [ %tmp602, %cond_next599 ], [ %source.0, %cond_true336 ], [ %source.6, %bb493 ] ; <i32> [#uses=7]
1253 %tmp606 = getelementptr %struct.const_tables* @tables, i32 0, i32 0, i32 %cnt.01055.1 ; <i8*> [#uses=1]
1254 %tmp607 = load i8* %tmp606, align 1 ; <i8> [#uses=1]
1258 LBB4_70: # cond_next603
1259 movl -20(%ebp), %esi
1260 movl L_tables$non_lazy_ptr-"L4$pb"(%esi), %esi
1262 However, ICC caches this information before the loop and produces this:
1264 movl 88(%esp), %eax #481.12
1266 //===---------------------------------------------------------------------===//
1270 %tmp659 = icmp slt i16 %tmp654, 0 ; <i1> [#uses=1]
1271 br i1 %tmp659, label %cond_true662, label %cond_next715
1277 jns LBB4_109 # cond_next715
1279 Shark tells us that using %cx in the testw instruction is sub-optimal. It
1280 suggests using the 32-bit register (which is what ICC uses).
1282 //===---------------------------------------------------------------------===//
1284 rdar://5506677 - We compile this:
1286 define i32 @foo(double %x) {
1287 %x14 = bitcast double %x to i64 ; <i64> [#uses=1]
1288 %tmp713 = trunc i64 %x14 to i32 ; <i32> [#uses=1]
1289 %tmp8 = and i32 %tmp713, 2147483647 ; <i32> [#uses=1]
1299 movl $2147483647, %eax
1305 It would be much better to eliminate the fldl/fstpl by folding the bitcast
1306 into the load SDNode. That would give us:
1309 movl $2147483647, %eax
1313 //===---------------------------------------------------------------------===//
1317 void compare (long long foo) {
1318 if (foo < 4294967297LL)
1335 je LBB1_2 # cond_true
1337 (also really horrible code on ppc). This is due to the expand code for 64-bit
1338 compares. GCC produces multiple branches, which is much nicer:
1354 //===---------------------------------------------------------------------===//
1356 Tail call optimization improvements: Tail call optimization currently
1357 pushes all arguments on the top of the stack (their normal place for
1358 non-tail call optimized calls) before moving them to actual stack
1359 slot. This is done to prevent overwriting of parameters (see example
1360 below) that might be used, since the arguments of the callee
1361 overwrites caller's arguments.
1365 int callee(int32, int64);
1366 int caller(int32 arg1, int32 arg2) {
1367 int64 local = arg2 * 2;
1368 return callee(arg2, (int64)local);
1371 [arg1] [!arg2 no longer valid since we moved local onto it]
1375 Moving arg1 onto the stack slot of callee function would overwrite
1378 Possible optimizations:
1380 - Only push those arguments to the top of the stack that are actual
1381 parameters of the caller function and have no local value in the
1384 In the above example local does not need to be pushed onto the top
1385 of the stack as it is definitely not a caller's function
1388 - Analyse the actual parameters of the callee to see which would
1389 overwrite a caller parameter which is used by the callee and only
1390 push them onto the top of the stack.
1392 int callee (int32 arg1, int32 arg2);
1393 int caller (int32 arg1, int32 arg2) {
1394 return callee(arg1,arg2);
1397 Here we don't need to write any variables to the top of the stack
1398 since they don't overwrite each other.
1400 int callee (int32 arg1, int32 arg2);
1401 int caller (int32 arg1, int32 arg2) {
1402 return callee(arg2,arg1);
1405 Here we need to push the arguments because they overwrite each
1409 Code for lowering directly onto callers arguments:
1410 + SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
1411 + SmallVector<SDOperand, 8> MemOpChains;
1413 + SDOperand FramePtr;
1417 + // Walk the register/memloc assignments, inserting copies/loads.
1418 + for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1419 + CCValAssign &VA = ArgLocs[i];
1420 + SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
1424 + if (VA.isRegLoc()) {
1425 + RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1427 + assert(VA.isMemLoc());
1428 + // create frame index
1429 + int32_t Offset = VA.getLocMemOffset()+FPDiff;
1430 + uint32_t OpSize = (MVT::getSizeInBits(VA.getLocVT())+7)/8;
1431 + FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
1432 + FIN = DAG.getFrameIndex(FI, MVT::i32);
1433 + // store relative to framepointer
1434 + MemOpChains.push_back(DAG.getStore(Chain, Arg, FIN, NULL, 0));
1437 //===---------------------------------------------------------------------===//