1 //===---------------------------------------------------------------------===//
2 // Random ideas for the X86 backend.
3 //===---------------------------------------------------------------------===//
6 - Support for SSE4: http://www.intel.com/software/penryn
7 http://softwarecommunity.intel.com/isn/Downloads/Intel%20SSE4%20Programming%20Reference.pdf
11 //===---------------------------------------------------------------------===//
13 Add a MUL2U and MUL2S nodes to represent a multiply that returns both the
14 Hi and Lo parts (combination of MUL and MULH[SU] into one node). Add this to
15 X86, & make the dag combiner produce it when needed. This will eliminate one
16 imul from the code generated for:
18 long long test(long long X, long long Y) { return X*Y; }
20 by using the EAX result from the mul. We should add a similar node for
25 long long test(int X, int Y) { return (long long)X*Y; }
27 ... which should only be one imul instruction.
29 This can be done with a custom expander, but it would be nice to move this to
32 //===---------------------------------------------------------------------===//
34 CodeGen/X86/lea-3.ll:test3 should be a single LEA, not a shift/move. The X86
35 backend knows how to three-addressify this shift, but it appears the register
36 allocator isn't even asking it to do so in this case. We should investigate
37 why this isn't happening, it could have significant impact on other important
38 cases for X86 as well.
40 //===---------------------------------------------------------------------===//
42 This should be one DIV/IDIV instruction, not a libcall:
44 unsigned test(unsigned long long X, unsigned Y) {
48 This can be done trivially with a custom legalizer. What about overflow
49 though? http://gcc.gnu.org/bugzilla/show_bug.cgi?id=14224
51 //===---------------------------------------------------------------------===//
53 Improvements to the multiply -> shift/add algorithm:
54 http://gcc.gnu.org/ml/gcc-patches/2004-08/msg01590.html
56 //===---------------------------------------------------------------------===//
58 Improve code like this (occurs fairly frequently, e.g. in LLVM):
59 long long foo(int x) { return 1LL << x; }
61 http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01109.html
62 http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01128.html
63 http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01136.html
65 Another useful one would be ~0ULL >> X and ~0ULL << X.
67 One better solution for 1LL << x is:
76 But that requires good 8-bit subreg support.
78 64-bit shifts (in general) expand to really bad code. Instead of using
79 cmovs, we should expand to a conditional branch like GCC produces.
81 //===---------------------------------------------------------------------===//
84 _Bool f(_Bool a) { return a!=1; }
91 //===---------------------------------------------------------------------===//
95 1. Dynamic programming based approach when compile time if not an
97 2. Code duplication (addressing mode) during isel.
98 3. Other ideas from "Register-Sensitive Selection, Duplication, and
99 Sequencing of Instructions".
100 4. Scheduling for reduced register pressure. E.g. "Minimum Register
101 Instruction Sequence Problem: Revisiting Optimal Code Generation for DAGs"
102 and other related papers.
103 http://citeseer.ist.psu.edu/govindarajan01minimum.html
105 //===---------------------------------------------------------------------===//
107 Should we promote i16 to i32 to avoid partial register update stalls?
109 //===---------------------------------------------------------------------===//
111 Leave any_extend as pseudo instruction and hint to register
112 allocator. Delay codegen until post register allocation.
114 //===---------------------------------------------------------------------===//
116 Count leading zeros and count trailing zeros:
118 int clz(int X) { return __builtin_clz(X); }
119 int ctz(int X) { return __builtin_ctz(X); }
121 $ gcc t.c -S -o - -O3 -fomit-frame-pointer -masm=intel
123 bsr %eax, DWORD PTR [%esp+4]
127 bsf %eax, DWORD PTR [%esp+4]
130 however, check that these are defined for 0 and 32. Our intrinsics are, GCC's
133 Another example (use predsimplify to eliminate a select):
135 int foo (unsigned long j) {
137 return __builtin_ffs (j) - 1;
142 //===---------------------------------------------------------------------===//
144 Use push/pop instructions in prolog/epilog sequences instead of stores off
145 ESP (certain code size win, perf win on some [which?] processors).
146 Also, it appears icc use push for parameter passing. Need to investigate.
148 //===---------------------------------------------------------------------===//
150 Only use inc/neg/not instructions on processors where they are faster than
151 add/sub/xor. They are slower on the P4 due to only updating some processor
154 //===---------------------------------------------------------------------===//
156 The instruction selector sometimes misses folding a load into a compare. The
157 pattern is written as (cmp reg, (load p)). Because the compare isn't
158 commutative, it is not matched with the load on both sides. The dag combiner
159 should be made smart enough to cannonicalize the load into the RHS of a compare
160 when it can invert the result of the compare for free.
162 //===---------------------------------------------------------------------===//
164 How about intrinsics? An example is:
165 *res = _mm_mulhi_epu16(*A, _mm_mul_epu32(*B, *C));
168 pmuludq (%eax), %xmm0
173 The transformation probably requires a X86 specific pass or a DAG combiner
174 target specific hook.
176 //===---------------------------------------------------------------------===//
178 In many cases, LLVM generates code like this:
187 on some processors (which ones?), it is more efficient to do this:
196 Doing this correctly is tricky though, as the xor clobbers the flags.
198 //===---------------------------------------------------------------------===//
200 We should generate bts/btr/etc instructions on targets where they are cheap or
201 when codesize is important. e.g., for:
203 void setbit(int *target, int bit) {
204 *target |= (1 << bit);
206 void clearbit(int *target, int bit) {
207 *target &= ~(1 << bit);
210 //===---------------------------------------------------------------------===//
212 Instead of the following for memset char*, 1, 10:
214 movl $16843009, 4(%edx)
215 movl $16843009, (%edx)
218 It might be better to generate
225 when we can spare a register. It reduces code size.
227 //===---------------------------------------------------------------------===//
229 Evaluate what the best way to codegen sdiv X, (2^C) is. For X/8, we currently
246 GCC knows several different ways to codegen it, one of which is this:
256 which is probably slower, but it's interesting at least :)
258 //===---------------------------------------------------------------------===//
260 The first BB of this code:
264 %V = call bool %foo()
265 br bool %V, label %T, label %F
282 It would be better to emit "cmp %al, 1" than a xor and test.
284 //===---------------------------------------------------------------------===//
286 Enable X86InstrInfo::convertToThreeAddress().
288 //===---------------------------------------------------------------------===//
290 We are currently lowering large (1MB+) memmove/memcpy to rep/stosl and rep/movsl
291 We should leave these as libcalls for everything over a much lower threshold,
292 since libc is hand tuned for medium and large mem ops (avoiding RFO for large
293 stores, TLB preheating, etc)
295 //===---------------------------------------------------------------------===//
297 Optimize this into something reasonable:
298 x * copysign(1.0, y) * copysign(1.0, z)
300 //===---------------------------------------------------------------------===//
302 Optimize copysign(x, *y) to use an integer load from y.
304 //===---------------------------------------------------------------------===//
306 %X = weak global int 0
309 %N = cast int %N to uint
310 %tmp.24 = setgt int %N, 0
311 br bool %tmp.24, label %no_exit, label %return
314 %indvar = phi uint [ 0, %entry ], [ %indvar.next, %no_exit ]
315 %i.0.0 = cast uint %indvar to int
316 volatile store int %i.0.0, int* %X
317 %indvar.next = add uint %indvar, 1
318 %exitcond = seteq uint %indvar.next, %N
319 br bool %exitcond, label %return, label %no_exit
333 jl LBB_foo_4 # return
334 LBB_foo_1: # no_exit.preheader
337 movl L_X$non_lazy_ptr, %edx
341 jne LBB_foo_2 # no_exit
342 LBB_foo_3: # return.loopexit
346 We should hoist "movl L_X$non_lazy_ptr, %edx" out of the loop after
347 remateralization is implemented. This can be accomplished with 1) a target
348 dependent LICM pass or 2) makeing SelectDAG represent the whole function.
350 //===---------------------------------------------------------------------===//
352 The following tests perform worse with LSR:
354 lambda, siod, optimizer-eval, ackermann, hash2, nestedloop, strcat, and Treesor.
356 //===---------------------------------------------------------------------===//
358 We are generating far worse code than gcc:
364 for (i = 0; i < N; i++) { X = i; Y = i*4; }
367 LBB1_1: #bb.preheader
371 movl L_X$non_lazy_ptr, %esi
375 movl L_Y$non_lazy_ptr, %edi
385 movl L_X$non_lazy_ptr-"L00000000001$pb"(%ebx), %esi
386 movl L_Y$non_lazy_ptr-"L00000000001$pb"(%ebx), %ecx
389 leal 0(,%edx,4), %eax
397 1. Lack of post regalloc LICM.
398 2. Poor sub-regclass support. That leads to inability to promote the 16-bit
399 arithmetic op to 32-bit and making use of leal.
400 3. LSR unable to reused IV for a different type (i16 vs. i32) even though
401 the cast would be free.
403 //===---------------------------------------------------------------------===//
405 Teach the coalescer to coalesce vregs of different register classes. e.g. FR32 /
408 //===---------------------------------------------------------------------===//
416 Obviously it would have been better for the first mov (or any op) to store
417 directly %esp[0] if there are no other uses.
419 //===---------------------------------------------------------------------===//
421 Adding to the list of cmp / test poor codegen issues:
423 int test(__m128 *A, __m128 *B) {
424 if (_mm_comige_ss(*A, *B))
444 Note the setae, movzbl, cmpl, cmove can be replaced with a single cmovae. There
445 are a number of issues. 1) We are introducing a setcc between the result of the
446 intrisic call and select. 2) The intrinsic is expected to produce a i32 value
447 so a any extend (which becomes a zero extend) is added.
449 We probably need some kind of target DAG combine hook to fix this.
451 //===---------------------------------------------------------------------===//
453 We generate significantly worse code for this than GCC:
454 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=21150
455 http://gcc.gnu.org/bugzilla/attachment.cgi?id=8701
457 There is also one case we do worse on PPC.
459 //===---------------------------------------------------------------------===//
461 If shorter, we should use things like:
466 The former can also be used when the two-addressy nature of the 'and' would
467 require a copy to be inserted (in X86InstrInfo::convertToThreeAddress).
469 //===---------------------------------------------------------------------===//
473 char foo(int x) { return x; }
481 SIGN_EXTEND_INREG can be implemented as (sext (trunc)) to take advantage of
484 //===---------------------------------------------------------------------===//
488 typedef struct pair { float A, B; } pair;
489 void pairtest(pair P, float *FP) {
493 We currently generate this code with llvmgcc4:
505 we should be able to generate:
513 The issue is that llvmgcc4 is forcing the struct to memory, then passing it as
514 integer chunks. It does this so that structs like {short,short} are passed in
515 a single 32-bit integer stack slot. We should handle the safe cases above much
516 nicer, while still handling the hard cases.
518 While true in general, in this specific case we could do better by promoting
519 load int + bitcast to float -> load fload. This basically needs alignment info,
520 the code is already implemented (but disabled) in dag combine).
522 //===---------------------------------------------------------------------===//
524 Another instruction selector deficiency:
527 %tmp = load int (int)** %foo
528 %tmp = tail call int %tmp( int 3 )
534 movl L_foo$non_lazy_ptr, %eax
540 The current isel scheme will not allow the load to be folded in the call since
541 the load's chain result is read by the callseq_start.
543 //===---------------------------------------------------------------------===//
545 Don't forget to find a way to squash noop truncates in the JIT environment.
547 //===---------------------------------------------------------------------===//
549 Implement anyext in the same manner as truncate that would allow them to be
552 //===---------------------------------------------------------------------===//
554 How about implementing truncate / anyext as a property of machine instruction
555 operand? i.e. Print as 32-bit super-class register / 16-bit sub-class register.
556 Do this for the cases where a truncate / anyext is guaranteed to be eliminated.
557 For IA32 that is truncate from 32 to 16 and anyext from 16 to 32.
559 //===---------------------------------------------------------------------===//
569 imull $3, 4(%esp), %eax
571 Perhaps this is what we really should generate is? Is imull three or four
572 cycles? Note: ICC generates this:
574 leal (%eax,%eax,2), %eax
576 The current instruction priority is based on pattern complexity. The former is
577 more "complex" because it folds a load so the latter will not be emitted.
579 Perhaps we should use AddedComplexity to give LEA32r a higher priority? We
580 should always try to match LEA first since the LEA matching code does some
581 estimate to determine whether the match is profitable.
583 However, if we care more about code size, then imull is better. It's two bytes
584 shorter than movl + leal.
586 //===---------------------------------------------------------------------===//
588 Implement CTTZ, CTLZ with bsf and bsr.
590 //===---------------------------------------------------------------------===//
592 It appears gcc place string data with linkonce linkage in
593 .section __TEXT,__const_coal,coalesced instead of
594 .section __DATA,__const_coal,coalesced.
595 Take a look at darwin.h, there are other Darwin assembler directives that we
598 //===---------------------------------------------------------------------===//
600 int %foo(int* %a, int %t) {
604 cond_true: ; preds = %cond_true, %entry
605 %x.0.0 = phi int [ 0, %entry ], [ %tmp9, %cond_true ]
606 %t_addr.0.0 = phi int [ %t, %entry ], [ %tmp7, %cond_true ]
607 %tmp2 = getelementptr int* %a, int %x.0.0
608 %tmp3 = load int* %tmp2 ; <int> [#uses=1]
609 %tmp5 = add int %t_addr.0.0, %x.0.0 ; <int> [#uses=1]
610 %tmp7 = add int %tmp5, %tmp3 ; <int> [#uses=2]
611 %tmp9 = add int %x.0.0, 1 ; <int> [#uses=2]
612 %tmp = setgt int %tmp9, 39 ; <bool> [#uses=1]
613 br bool %tmp, label %bb12, label %cond_true
615 bb12: ; preds = %cond_true
619 is pessimized by -loop-reduce and -indvars
621 //===---------------------------------------------------------------------===//
623 u32 to float conversion improvement:
625 float uint32_2_float( unsigned u ) {
626 float fl = (int) (u & 0xffff);
627 float fh = (int) (u >> 16);
632 00000000 subl $0x04,%esp
633 00000003 movl 0x08(%esp,1),%eax
634 00000007 movl %eax,%ecx
635 00000009 shrl $0x10,%ecx
636 0000000c cvtsi2ss %ecx,%xmm0
637 00000010 andl $0x0000ffff,%eax
638 00000015 cvtsi2ss %eax,%xmm1
639 00000019 mulss 0x00000078,%xmm0
640 00000021 addss %xmm1,%xmm0
641 00000025 movss %xmm0,(%esp,1)
642 0000002a flds (%esp,1)
643 0000002d addl $0x04,%esp
646 //===---------------------------------------------------------------------===//
648 When using fastcc abi, align stack slot of argument of type double on 8 byte
649 boundary to improve performance.
651 //===---------------------------------------------------------------------===//
655 int f(int a, int b) {
656 if (a == 4 || a == 6)
668 //===---------------------------------------------------------------------===//
670 GCC's ix86_expand_int_movcc function (in i386.c) has a ton of interesting
671 simplifications for integer "x cmp y ? a : b". For example, instead of:
674 void f(int X, int Y) {
700 //===---------------------------------------------------------------------===//
702 Currently we don't have elimination of redundant stack manipulations. Consider
707 call fastcc void %test1( )
708 call fastcc void %test2( sbyte* cast (void ()* %test1 to sbyte*) )
712 declare fastcc void %test1()
714 declare fastcc void %test2(sbyte*)
717 This currently compiles to:
727 The add\sub pair is really unneeded here.
729 //===---------------------------------------------------------------------===//
731 We currently compile sign_extend_inreg into two shifts:
734 return (long)(signed char)X;
751 //===---------------------------------------------------------------------===//
753 Consider the expansion of:
755 uint %test3(uint %X) {
756 %tmp1 = rem uint %X, 255
760 Currently it compiles to:
763 movl $2155905153, %ecx
769 This could be "reassociated" into:
771 movl $2155905153, %eax
775 to avoid the copy. In fact, the existing two-address stuff would do this
776 except that mul isn't a commutative 2-addr instruction. I guess this has
777 to be done at isel time based on the #uses to mul?
779 //===---------------------------------------------------------------------===//
781 Make sure the instruction which starts a loop does not cross a cacheline
782 boundary. This requires knowning the exact length of each machine instruction.
783 That is somewhat complicated, but doable. Example 256.bzip2:
785 In the new trace, the hot loop has an instruction which crosses a cacheline
786 boundary. In addition to potential cache misses, this can't help decoding as I
787 imagine there has to be some kind of complicated decoder reset and realignment
788 to grab the bytes from the next cacheline.
790 532 532 0x3cfc movb (1809(%esp, %esi), %bl <<<--- spans 2 64 byte lines
791 942 942 0x3d03 movl %dh, (1809(%esp, %esi)
792 937 937 0x3d0a incl %esi
793 3 3 0x3d0b cmpb %bl, %dl
794 27 27 0x3d0d jnz 0x000062db <main+11707>
796 //===---------------------------------------------------------------------===//
798 In c99 mode, the preprocessor doesn't like assembly comments like #TRUNCATE.
800 //===---------------------------------------------------------------------===//
802 This could be a single 16-bit load.
805 if ((p[0] == 1) & (p[1] == 2)) return 1;
809 //===---------------------------------------------------------------------===//
811 We should inline lrintf and probably other libc functions.
813 //===---------------------------------------------------------------------===//
815 Start using the flags more. For example, compile:
817 int add_zf(int *x, int y, int a, int b) {
841 int add_zf(int *x, int y, int a, int b) {
865 //===---------------------------------------------------------------------===//
869 int foo(double X) { return isnan(X); }
880 the pxor is not needed, we could compare the value against itself.
882 //===---------------------------------------------------------------------===//
884 These two functions have identical effects:
886 unsigned int f(unsigned int i, unsigned int n) {++i; if (i == n) ++i; return i;}
887 unsigned int f2(unsigned int i, unsigned int n) {++i; i += i == n; return i;}
889 We currently compile them to:
897 jne LBB1_2 #UnifiedReturnBlock
901 LBB1_2: #UnifiedReturnBlock
911 leal 1(%ecx,%eax), %eax
914 both of which are inferior to GCC's:
932 //===---------------------------------------------------------------------===//
940 is currently compiled to:
951 It would be better to produce:
960 This can be applied to any no-return function call that takes no arguments etc.
961 Alternatively, the stack save/restore logic could be shrink-wrapped, producing
972 Both are useful in different situations. Finally, it could be shrink-wrapped
973 and tail called, like this:
980 pop %eax # realign stack.
983 Though this probably isn't worth it.
985 //===---------------------------------------------------------------------===//
987 We need to teach the codegen to convert two-address INC instructions to LEA
988 when the flags are dead. For example, on X86-64, compile:
990 int foo(int A, int B) {
1007 //===---------------------------------------------------------------------===//
1009 We use push/pop of stack space around calls in situations where we don't have to.
1010 Call to f below produces:
1011 subl $16, %esp <<<<<
1014 addl $16, %esp <<<<<
1015 The stack push/pop can be moved into the prolog/epilog. It does this because it's
1016 building the frame pointer, but this should not be sufficient, only the use of alloca
1017 should cause it to do this.
1018 (There are other issues shown by this code, but this is one.)
1020 typedef struct _range_t {
1026 unsigned char lut[];
1038 const range_t*const*range;
1041 typedef struct _decode_t decode_t;
1043 extern int f(const decode_t* decode);
1045 int decode_byte (const decode_t* decode) {
1046 if (decode->swap != 0)
1052 //===---------------------------------------------------------------------===//
1055 #include <xmmintrin.h>
1056 unsigned test(float f) {
1057 return _mm_cvtsi128_si32( (__m128i) _mm_set_ss( f ));
1062 movss 4(%esp), %xmm0
1066 it should compile to a move from the stack slot directly into eax. DAGCombine
1067 has this xform, but it is currently disabled until the alignment fields of
1068 the load/store nodes are trustworthy.