1 //===---------------------------------------------------------------------===//
2 // Random ideas for the X86 backend.
3 //===---------------------------------------------------------------------===//
6 //===---------------------------------------------------------------------===//
8 CodeGen/X86/lea-3.ll:test3 should be a single LEA, not a shift/move. The X86
9 backend knows how to three-addressify this shift, but it appears the register
10 allocator isn't even asking it to do so in this case. We should investigate
11 why this isn't happening, it could have significant impact on other important
12 cases for X86 as well.
14 //===---------------------------------------------------------------------===//
16 This should be one DIV/IDIV instruction, not a libcall:
18 unsigned test(unsigned long long X, unsigned Y) {
22 This can be done trivially with a custom legalizer. What about overflow
23 though? http://gcc.gnu.org/bugzilla/show_bug.cgi?id=14224
25 //===---------------------------------------------------------------------===//
27 Improvements to the multiply -> shift/add algorithm:
28 http://gcc.gnu.org/ml/gcc-patches/2004-08/msg01590.html
30 //===---------------------------------------------------------------------===//
32 Improve code like this (occurs fairly frequently, e.g. in LLVM):
33 long long foo(int x) { return 1LL << x; }
35 http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01109.html
36 http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01128.html
37 http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01136.html
39 Another useful one would be ~0ULL >> X and ~0ULL << X.
41 One better solution for 1LL << x is:
50 But that requires good 8-bit subreg support.
52 Also, this might be better. It's an extra shift, but it's one instruction
53 shorter, and doesn't stress 8-bit subreg support.
54 (From http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01148.html,
55 but without the unnecessary and.)
63 64-bit shifts (in general) expand to really bad code. Instead of using
64 cmovs, we should expand to a conditional branch like GCC produces.
66 //===---------------------------------------------------------------------===//
69 _Bool f(_Bool a) { return a!=1; }
76 (Although note that this isn't a legal way to express the code that llvm-gcc
77 currently generates for that function.)
79 //===---------------------------------------------------------------------===//
83 1. Dynamic programming based approach when compile time if not an
85 2. Code duplication (addressing mode) during isel.
86 3. Other ideas from "Register-Sensitive Selection, Duplication, and
87 Sequencing of Instructions".
88 4. Scheduling for reduced register pressure. E.g. "Minimum Register
89 Instruction Sequence Problem: Revisiting Optimal Code Generation for DAGs"
90 and other related papers.
91 http://citeseer.ist.psu.edu/govindarajan01minimum.html
93 //===---------------------------------------------------------------------===//
95 Should we promote i16 to i32 to avoid partial register update stalls?
97 //===---------------------------------------------------------------------===//
99 Leave any_extend as pseudo instruction and hint to register
100 allocator. Delay codegen until post register allocation.
101 Note. any_extend is now turned into an INSERT_SUBREG. We still need to teach
102 the coalescer how to deal with it though.
104 //===---------------------------------------------------------------------===//
106 It appears icc use push for parameter passing. Need to investigate.
108 //===---------------------------------------------------------------------===//
110 Only use inc/neg/not instructions on processors where they are faster than
111 add/sub/xor. They are slower on the P4 due to only updating some processor
114 //===---------------------------------------------------------------------===//
116 The instruction selector sometimes misses folding a load into a compare. The
117 pattern is written as (cmp reg, (load p)). Because the compare isn't
118 commutative, it is not matched with the load on both sides. The dag combiner
119 should be made smart enough to cannonicalize the load into the RHS of a compare
120 when it can invert the result of the compare for free.
122 //===---------------------------------------------------------------------===//
124 How about intrinsics? An example is:
125 *res = _mm_mulhi_epu16(*A, _mm_mul_epu32(*B, *C));
128 pmuludq (%eax), %xmm0
133 The transformation probably requires a X86 specific pass or a DAG combiner
134 target specific hook.
136 //===---------------------------------------------------------------------===//
138 In many cases, LLVM generates code like this:
147 on some processors (which ones?), it is more efficient to do this:
156 Doing this correctly is tricky though, as the xor clobbers the flags.
158 //===---------------------------------------------------------------------===//
160 We should generate bts/btr/etc instructions on targets where they are cheap or
161 when codesize is important. e.g., for:
163 void setbit(int *target, int bit) {
164 *target |= (1 << bit);
166 void clearbit(int *target, int bit) {
167 *target &= ~(1 << bit);
170 //===---------------------------------------------------------------------===//
172 Instead of the following for memset char*, 1, 10:
174 movl $16843009, 4(%edx)
175 movl $16843009, (%edx)
178 It might be better to generate
185 when we can spare a register. It reduces code size.
187 //===---------------------------------------------------------------------===//
189 Evaluate what the best way to codegen sdiv X, (2^C) is. For X/8, we currently
192 define i32 @test1(i32 %X) {
206 GCC knows several different ways to codegen it, one of which is this:
216 which is probably slower, but it's interesting at least :)
218 //===---------------------------------------------------------------------===//
220 We are currently lowering large (1MB+) memmove/memcpy to rep/stosl and rep/movsl
221 We should leave these as libcalls for everything over a much lower threshold,
222 since libc is hand tuned for medium and large mem ops (avoiding RFO for large
223 stores, TLB preheating, etc)
225 //===---------------------------------------------------------------------===//
227 Optimize this into something reasonable:
228 x * copysign(1.0, y) * copysign(1.0, z)
230 //===---------------------------------------------------------------------===//
232 Optimize copysign(x, *y) to use an integer load from y.
234 //===---------------------------------------------------------------------===//
236 %X = weak global int 0
239 %N = cast int %N to uint
240 %tmp.24 = setgt int %N, 0
241 br bool %tmp.24, label %no_exit, label %return
244 %indvar = phi uint [ 0, %entry ], [ %indvar.next, %no_exit ]
245 %i.0.0 = cast uint %indvar to int
246 volatile store int %i.0.0, int* %X
247 %indvar.next = add uint %indvar, 1
248 %exitcond = seteq uint %indvar.next, %N
249 br bool %exitcond, label %return, label %no_exit
263 jl LBB_foo_4 # return
264 LBB_foo_1: # no_exit.preheader
267 movl L_X$non_lazy_ptr, %edx
271 jne LBB_foo_2 # no_exit
272 LBB_foo_3: # return.loopexit
276 We should hoist "movl L_X$non_lazy_ptr, %edx" out of the loop after
277 remateralization is implemented. This can be accomplished with 1) a target
278 dependent LICM pass or 2) makeing SelectDAG represent the whole function.
280 //===---------------------------------------------------------------------===//
282 The following tests perform worse with LSR:
284 lambda, siod, optimizer-eval, ackermann, hash2, nestedloop, strcat, and Treesor.
286 //===---------------------------------------------------------------------===//
288 We are generating far worse code than gcc:
294 for (i = 0; i < N; i++) { X = i; Y = i*4; }
297 LBB1_1: # entry.bb_crit_edge
301 movl L_X$non_lazy_ptr, %esi
303 movl L_Y$non_lazy_ptr, %esi
313 movl L_X$non_lazy_ptr-"L00000000001$pb"(%ebx), %esi
314 movl L_Y$non_lazy_ptr-"L00000000001$pb"(%ebx), %ecx
317 leal 0(,%edx,4), %eax
323 This is due to the lack of post regalloc LICM.
325 //===---------------------------------------------------------------------===//
327 Teach the coalescer to coalesce vregs of different register classes. e.g. FR32 /
330 //===---------------------------------------------------------------------===//
332 Adding to the list of cmp / test poor codegen issues:
334 int test(__m128 *A, __m128 *B) {
335 if (_mm_comige_ss(*A, *B))
355 Note the setae, movzbl, cmpl, cmove can be replaced with a single cmovae. There
356 are a number of issues. 1) We are introducing a setcc between the result of the
357 intrisic call and select. 2) The intrinsic is expected to produce a i32 value
358 so a any extend (which becomes a zero extend) is added.
360 We probably need some kind of target DAG combine hook to fix this.
362 //===---------------------------------------------------------------------===//
364 We generate significantly worse code for this than GCC:
365 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=21150
366 http://gcc.gnu.org/bugzilla/attachment.cgi?id=8701
368 There is also one case we do worse on PPC.
370 //===---------------------------------------------------------------------===//
380 imull $3, 4(%esp), %eax
382 Perhaps this is what we really should generate is? Is imull three or four
383 cycles? Note: ICC generates this:
385 leal (%eax,%eax,2), %eax
387 The current instruction priority is based on pattern complexity. The former is
388 more "complex" because it folds a load so the latter will not be emitted.
390 Perhaps we should use AddedComplexity to give LEA32r a higher priority? We
391 should always try to match LEA first since the LEA matching code does some
392 estimate to determine whether the match is profitable.
394 However, if we care more about code size, then imull is better. It's two bytes
395 shorter than movl + leal.
397 On a Pentium M, both variants have the same characteristics with regard
398 to throughput; however, the multiplication has a latency of four cycles, as
399 opposed to two cycles for the movl+lea variant.
401 //===---------------------------------------------------------------------===//
403 __builtin_ffs codegen is messy.
405 int ffs_(unsigned X) { return __builtin_ffs(X); }
428 Another example of __builtin_ffs (use predsimplify to eliminate a select):
430 int foo (unsigned long j) {
432 return __builtin_ffs (j) - 1;
437 //===---------------------------------------------------------------------===//
439 It appears gcc place string data with linkonce linkage in
440 .section __TEXT,__const_coal,coalesced instead of
441 .section __DATA,__const_coal,coalesced.
442 Take a look at darwin.h, there are other Darwin assembler directives that we
445 //===---------------------------------------------------------------------===//
447 define i32 @foo(i32* %a, i32 %t) {
451 cond_true: ; preds = %cond_true, %entry
452 %x.0.0 = phi i32 [ 0, %entry ], [ %tmp9, %cond_true ] ; <i32> [#uses=3]
453 %t_addr.0.0 = phi i32 [ %t, %entry ], [ %tmp7, %cond_true ] ; <i32> [#uses=1]
454 %tmp2 = getelementptr i32* %a, i32 %x.0.0 ; <i32*> [#uses=1]
455 %tmp3 = load i32* %tmp2 ; <i32> [#uses=1]
456 %tmp5 = add i32 %t_addr.0.0, %x.0.0 ; <i32> [#uses=1]
457 %tmp7 = add i32 %tmp5, %tmp3 ; <i32> [#uses=2]
458 %tmp9 = add i32 %x.0.0, 1 ; <i32> [#uses=2]
459 %tmp = icmp sgt i32 %tmp9, 39 ; <i1> [#uses=1]
460 br i1 %tmp, label %bb12, label %cond_true
462 bb12: ; preds = %cond_true
465 is pessimized by -loop-reduce and -indvars
467 //===---------------------------------------------------------------------===//
469 u32 to float conversion improvement:
471 float uint32_2_float( unsigned u ) {
472 float fl = (int) (u & 0xffff);
473 float fh = (int) (u >> 16);
478 00000000 subl $0x04,%esp
479 00000003 movl 0x08(%esp,1),%eax
480 00000007 movl %eax,%ecx
481 00000009 shrl $0x10,%ecx
482 0000000c cvtsi2ss %ecx,%xmm0
483 00000010 andl $0x0000ffff,%eax
484 00000015 cvtsi2ss %eax,%xmm1
485 00000019 mulss 0x00000078,%xmm0
486 00000021 addss %xmm1,%xmm0
487 00000025 movss %xmm0,(%esp,1)
488 0000002a flds (%esp,1)
489 0000002d addl $0x04,%esp
492 //===---------------------------------------------------------------------===//
494 When using fastcc abi, align stack slot of argument of type double on 8 byte
495 boundary to improve performance.
497 //===---------------------------------------------------------------------===//
501 int f(int a, int b) {
502 if (a == 4 || a == 6)
514 //===---------------------------------------------------------------------===//
516 GCC's ix86_expand_int_movcc function (in i386.c) has a ton of interesting
517 simplifications for integer "x cmp y ? a : b". For example, instead of:
520 void f(int X, int Y) {
547 int usesbb(unsigned int a, unsigned int b) {
548 return (a < b ? -1 : 0);
562 movl $4294967295, %ecx
566 //===---------------------------------------------------------------------===//
568 Currently we don't have elimination of redundant stack manipulations. Consider
573 call fastcc void %test1( )
574 call fastcc void %test2( sbyte* cast (void ()* %test1 to sbyte*) )
578 declare fastcc void %test1()
580 declare fastcc void %test2(sbyte*)
583 This currently compiles to:
593 The add\sub pair is really unneeded here.
595 //===---------------------------------------------------------------------===//
597 Consider the expansion of:
599 define i32 @test3(i32 %X) {
600 %tmp1 = urem i32 %X, 255
604 Currently it compiles to:
607 movl $2155905153, %ecx
613 This could be "reassociated" into:
615 movl $2155905153, %eax
619 to avoid the copy. In fact, the existing two-address stuff would do this
620 except that mul isn't a commutative 2-addr instruction. I guess this has
621 to be done at isel time based on the #uses to mul?
623 //===---------------------------------------------------------------------===//
625 Make sure the instruction which starts a loop does not cross a cacheline
626 boundary. This requires knowning the exact length of each machine instruction.
627 That is somewhat complicated, but doable. Example 256.bzip2:
629 In the new trace, the hot loop has an instruction which crosses a cacheline
630 boundary. In addition to potential cache misses, this can't help decoding as I
631 imagine there has to be some kind of complicated decoder reset and realignment
632 to grab the bytes from the next cacheline.
634 532 532 0x3cfc movb (1809(%esp, %esi), %bl <<<--- spans 2 64 byte lines
635 942 942 0x3d03 movl %dh, (1809(%esp, %esi)
636 937 937 0x3d0a incl %esi
637 3 3 0x3d0b cmpb %bl, %dl
638 27 27 0x3d0d jnz 0x000062db <main+11707>
640 //===---------------------------------------------------------------------===//
642 In c99 mode, the preprocessor doesn't like assembly comments like #TRUNCATE.
644 //===---------------------------------------------------------------------===//
646 This could be a single 16-bit load.
649 if ((p[0] == 1) & (p[1] == 2)) return 1;
653 //===---------------------------------------------------------------------===//
655 We should inline lrintf and probably other libc functions.
657 //===---------------------------------------------------------------------===//
659 Start using the flags more. For example, compile:
661 int add_zf(int *x, int y, int a, int b) {
685 int add_zf(int *x, int y, int a, int b) {
709 //===---------------------------------------------------------------------===//
711 These two functions have identical effects:
713 unsigned int f(unsigned int i, unsigned int n) {++i; if (i == n) ++i; return i;}
714 unsigned int f2(unsigned int i, unsigned int n) {++i; i += i == n; return i;}
716 We currently compile them to:
724 jne LBB1_2 #UnifiedReturnBlock
728 LBB1_2: #UnifiedReturnBlock
738 leal 1(%ecx,%eax), %eax
741 both of which are inferior to GCC's:
759 //===---------------------------------------------------------------------===//
767 is currently compiled to:
778 It would be better to produce:
787 This can be applied to any no-return function call that takes no arguments etc.
788 Alternatively, the stack save/restore logic could be shrink-wrapped, producing
799 Both are useful in different situations. Finally, it could be shrink-wrapped
800 and tail called, like this:
807 pop %eax # realign stack.
810 Though this probably isn't worth it.
812 //===---------------------------------------------------------------------===//
814 We need to teach the codegen to convert two-address INC instructions to LEA
815 when the flags are dead (likewise dec). For example, on X86-64, compile:
817 int foo(int A, int B) {
836 ;; X's live range extends beyond the shift, so the register allocator
837 ;; cannot coalesce it with Y. Because of this, a copy needs to be
838 ;; emitted before the shift to save the register value before it is
839 ;; clobbered. However, this copy is not needed if the register
840 ;; allocator turns the shift into an LEA. This also occurs for ADD.
842 ; Check that the shift gets turned into an LEA.
843 ; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | \
844 ; RUN: not grep {mov E.X, E.X}
846 @G = external global i32 ; <i32*> [#uses=3]
848 define i32 @test1(i32 %X, i32 %Y) {
849 %Z = add i32 %X, %Y ; <i32> [#uses=1]
850 volatile store i32 %Y, i32* @G
851 volatile store i32 %Z, i32* @G
855 define i32 @test2(i32 %X) {
856 %Z = add i32 %X, 1 ; <i32> [#uses=1]
857 volatile store i32 %Z, i32* @G
861 //===---------------------------------------------------------------------===//
863 Sometimes it is better to codegen subtractions from a constant (e.g. 7-x) with
864 a neg instead of a sub instruction. Consider:
866 int test(char X) { return 7-X; }
868 we currently produce:
875 We would use one fewer register if codegen'd as:
882 Note that this isn't beneficial if the load can be folded into the sub. In
883 this case, we want a sub:
885 int test(int X) { return 7-X; }
891 //===---------------------------------------------------------------------===//
893 Leaf functions that require one 4-byte spill slot have a prolog like this:
899 and an epilog like this:
904 It would be smaller, and potentially faster, to push eax on entry and to
905 pop into a dummy register instead of using addl/subl of esp. Just don't pop
906 into any return registers :)
908 //===---------------------------------------------------------------------===//
910 The X86 backend should fold (branch (or (setcc, setcc))) into multiple
911 branches. We generate really poor code for:
913 double testf(double a) {
914 return a == 0.0 ? 0.0 : (a > 0.0 ? 1.0 : -1.0);
917 For example, the entry BB is:
922 movsd 24(%esp), %xmm1
927 jne LBB1_5 # UnifiedReturnBlock
931 it would be better to replace the last four instructions with:
937 We also codegen the inner ?: into a diamond:
939 cvtss2sd LCPI1_0(%rip), %xmm2
940 cvtss2sd LCPI1_1(%rip), %xmm3
942 ja LBB1_3 # cond_true
949 We should sink the load into xmm3 into the LBB1_2 block. This should
950 be pretty easy, and will nuke all the copies.
952 //===---------------------------------------------------------------------===//
956 inline std::pair<unsigned, bool> full_add(unsigned a, unsigned b)
957 { return std::make_pair(a + b, a + b < a); }
958 bool no_overflow(unsigned a, unsigned b)
959 { return !full_add(a, b).second; }
969 FIXME: That code looks wrong; bool return is normally defined as zext.
981 //===---------------------------------------------------------------------===//
983 Re-materialize MOV32r0 etc. with xor instead of changing them to moves if the
984 condition register is dead. xor reg reg is shorter than mov reg, #0.
986 //===---------------------------------------------------------------------===//
988 We aren't matching RMW instructions aggressively
989 enough. Here's a reduced testcase (more in PR1160):
991 define void @test(i32* %huge_ptr, i32* %target_ptr) {
992 %A = load i32* %huge_ptr ; <i32> [#uses=1]
993 %B = load i32* %target_ptr ; <i32> [#uses=1]
994 %C = or i32 %A, %B ; <i32> [#uses=1]
995 store i32 %C, i32* %target_ptr
999 $ llvm-as < t.ll | llc -march=x86-64
1007 That should be something like:
1014 //===---------------------------------------------------------------------===//
1018 bb114.preheader: ; preds = %cond_next94
1019 %tmp231232 = sext i16 %tmp62 to i32 ; <i32> [#uses=1]
1020 %tmp233 = sub i32 32, %tmp231232 ; <i32> [#uses=1]
1021 %tmp245246 = sext i16 %tmp65 to i32 ; <i32> [#uses=1]
1022 %tmp252253 = sext i16 %tmp68 to i32 ; <i32> [#uses=1]
1023 %tmp254 = sub i32 32, %tmp252253 ; <i32> [#uses=1]
1024 %tmp553554 = bitcast i16* %tmp37 to i8* ; <i8*> [#uses=2]
1025 %tmp583584 = sext i16 %tmp98 to i32 ; <i32> [#uses=1]
1026 %tmp585 = sub i32 32, %tmp583584 ; <i32> [#uses=1]
1027 %tmp614615 = sext i16 %tmp101 to i32 ; <i32> [#uses=1]
1028 %tmp621622 = sext i16 %tmp104 to i32 ; <i32> [#uses=1]
1029 %tmp623 = sub i32 32, %tmp621622 ; <i32> [#uses=1]
1034 LBB3_5: # bb114.preheader
1035 movswl -68(%ebp), %eax
1037 movl %ecx, -80(%ebp)
1038 subl %eax, -80(%ebp)
1039 movswl -52(%ebp), %eax
1040 movl %ecx, -84(%ebp)
1041 subl %eax, -84(%ebp)
1042 movswl -70(%ebp), %eax
1043 movl %ecx, -88(%ebp)
1044 subl %eax, -88(%ebp)
1045 movswl -50(%ebp), %eax
1047 movl %ecx, -76(%ebp)
1048 movswl -42(%ebp), %eax
1049 movl %eax, -92(%ebp)
1050 movswl -66(%ebp), %eax
1051 movl %eax, -96(%ebp)
1054 This appears to be bad because the RA is not folding the store to the stack
1055 slot into the movl. The above instructions could be:
1060 This seems like a cross between remat and spill folding.
1062 This has redundant subtractions of %eax from a stack slot. However, %ecx doesn't
1063 change, so we could simply subtract %eax from %ecx first and then use %ecx (or
1066 //===---------------------------------------------------------------------===//
1070 %tmp659 = icmp slt i16 %tmp654, 0 ; <i1> [#uses=1]
1071 br i1 %tmp659, label %cond_true662, label %cond_next715
1077 jns LBB4_109 # cond_next715
1079 Shark tells us that using %cx in the testw instruction is sub-optimal. It
1080 suggests using the 32-bit register (which is what ICC uses).
1082 //===---------------------------------------------------------------------===//
1086 void compare (long long foo) {
1087 if (foo < 4294967297LL)
1103 jne .LBB1_2 # UnifiedReturnBlock
1106 .LBB1_2: # UnifiedReturnBlock
1110 (also really horrible code on ppc). This is due to the expand code for 64-bit
1111 compares. GCC produces multiple branches, which is much nicer:
1132 //===---------------------------------------------------------------------===//
1134 Tail call optimization improvements: Tail call optimization currently
1135 pushes all arguments on the top of the stack (their normal place for
1136 non-tail call optimized calls) that source from the callers arguments
1137 or that source from a virtual register (also possibly sourcing from
1139 This is done to prevent overwriting of parameters (see example
1140 below) that might be used later.
1144 int callee(int32, int64);
1145 int caller(int32 arg1, int32 arg2) {
1146 int64 local = arg2 * 2;
1147 return callee(arg2, (int64)local);
1150 [arg1] [!arg2 no longer valid since we moved local onto it]
1154 Moving arg1 onto the stack slot of callee function would overwrite
1157 Possible optimizations:
1160 - Analyse the actual parameters of the callee to see which would
1161 overwrite a caller parameter which is used by the callee and only
1162 push them onto the top of the stack.
1164 int callee (int32 arg1, int32 arg2);
1165 int caller (int32 arg1, int32 arg2) {
1166 return callee(arg1,arg2);
1169 Here we don't need to write any variables to the top of the stack
1170 since they don't overwrite each other.
1172 int callee (int32 arg1, int32 arg2);
1173 int caller (int32 arg1, int32 arg2) {
1174 return callee(arg2,arg1);
1177 Here we need to push the arguments because they overwrite each
1180 //===---------------------------------------------------------------------===//
1185 unsigned long int z = 0;
1196 gcc compiles this to:
1222 jge LBB1_4 # cond_true
1225 addl $4294950912, %ecx
1235 1. LSR should rewrite the first cmp with induction variable %ecx.
1236 2. DAG combiner should fold
1242 //===---------------------------------------------------------------------===//
1244 define i64 @test(double %X) {
1245 %Y = fptosi double %X to i64
1253 movsd 24(%esp), %xmm0
1254 movsd %xmm0, 8(%esp)
1263 This should just fldl directly from the input stack slot.
1265 //===---------------------------------------------------------------------===//
1268 int foo (int x) { return (x & 65535) | 255; }
1270 Should compile into:
1273 movzwl 4(%esp), %eax
1284 //===---------------------------------------------------------------------===//
1286 We're codegen'ing multiply of long longs inefficiently:
1288 unsigned long long LLM(unsigned long long arg1, unsigned long long arg2) {
1292 We compile to (fomit-frame-pointer):
1300 imull 12(%esp), %esi
1302 imull 20(%esp), %ecx
1308 This looks like a scheduling deficiency and lack of remat of the load from
1309 the argument area. ICC apparently produces:
1312 imull 12(%esp), %ecx
1321 Note that it remat'd loads from 4(esp) and 12(esp). See this GCC PR:
1322 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=17236
1324 //===---------------------------------------------------------------------===//
1326 We can fold a store into "zeroing a reg". Instead of:
1329 movl %eax, 124(%esp)
1335 if the flags of the xor are dead.
1337 Likewise, we isel "x<<1" into "add reg,reg". If reg is spilled, this should
1338 be folded into: shl [mem], 1
1340 //===---------------------------------------------------------------------===//
1342 This testcase misses a read/modify/write opportunity (from PR1425):
1344 void vertical_decompose97iH1(int *b0, int *b1, int *b2, int width){
1346 for(i=0; i<width; i++)
1347 b1[i] += (1*(b0[i] + b2[i])+0)>>0;
1350 We compile it down to:
1353 movl (%esi,%edi,4), %ebx
1354 addl (%ecx,%edi,4), %ebx
1355 addl (%edx,%edi,4), %ebx
1356 movl %ebx, (%ecx,%edi,4)
1361 the inner loop should add to the memory location (%ecx,%edi,4), saving
1362 a mov. Something like:
1364 movl (%esi,%edi,4), %ebx
1365 addl (%edx,%edi,4), %ebx
1366 addl %ebx, (%ecx,%edi,4)
1368 Here is another interesting example:
1370 void vertical_compose97iH1(int *b0, int *b1, int *b2, int width){
1372 for(i=0; i<width; i++)
1373 b1[i] -= (1*(b0[i] + b2[i])+0)>>0;
1376 We miss the r/m/w opportunity here by using 2 subs instead of an add+sub[mem]:
1379 movl (%ecx,%edi,4), %ebx
1380 subl (%esi,%edi,4), %ebx
1381 subl (%edx,%edi,4), %ebx
1382 movl %ebx, (%ecx,%edi,4)
1387 Additionally, LSR should rewrite the exit condition of these loops to use
1388 a stride-4 IV, would would allow all the scales in the loop to go away.
1389 This would result in smaller code and more efficient microops.
1391 //===---------------------------------------------------------------------===//
1393 In SSE mode, we turn abs and neg into a load from the constant pool plus a xor
1394 or and instruction, for example:
1396 xorpd LCPI1_0, %xmm2
1398 However, if xmm2 gets spilled, we end up with really ugly code like this:
1401 xorpd LCPI1_0, %xmm0
1404 Since we 'know' that this is a 'neg', we can actually "fold" the spill into
1405 the neg/abs instruction, turning it into an *integer* operation, like this:
1407 xorl 2147483648, [mem+4] ## 2147483648 = (1 << 31)
1409 you could also use xorb, but xorl is less likely to lead to a partial register
1410 stall. Here is a contrived testcase:
1413 void test(double *P) {
1423 //===---------------------------------------------------------------------===//
1425 handling llvm.memory.barrier on pre SSE2 cpus
1428 lock ; mov %esp, %esp
1430 //===---------------------------------------------------------------------===//
1432 The generated code on x86 for checking for signed overflow on a multiply the
1433 obvious way is much longer than it needs to be.
1435 int x(int a, int b) {
1436 long long prod = (long long)a*b;
1437 return prod > 0x7FFFFFFF || prod < (-0x7FFFFFFF-1);
1440 See PR2053 for more details.
1442 //===---------------------------------------------------------------------===//
1444 We should investigate using cdq/ctld (effect: edx = sar eax, 31)
1445 more aggressively; it should cost the same as a move+shift on any modern
1446 processor, but it's a lot shorter. Downside is that it puts more
1447 pressure on register allocation because it has fixed operands.
1450 int abs(int x) {return x < 0 ? -x : x;}
1452 gcc compiles this to the following when using march/mtune=pentium2/3/4/m/etc.:
1460 //===---------------------------------------------------------------------===//
1463 int test(unsigned long a, unsigned long b) { return -(a < b); }
1465 We currently compile this to:
1467 define i32 @test(i32 %a, i32 %b) nounwind {
1468 %tmp3 = icmp ult i32 %a, %b ; <i1> [#uses=1]
1469 %tmp34 = zext i1 %tmp3 to i32 ; <i32> [#uses=1]
1470 %tmp5 = sub i32 0, %tmp34 ; <i32> [#uses=1]
1484 Several deficiencies here. First, we should instcombine zext+neg into sext:
1486 define i32 @test2(i32 %a, i32 %b) nounwind {
1487 %tmp3 = icmp ult i32 %a, %b ; <i1> [#uses=1]
1488 %tmp34 = sext i1 %tmp3 to i32 ; <i32> [#uses=1]
1492 However, before we can do that, we have to fix the bad codegen that we get for
1504 This code should be at least as good as the code above. Once this is fixed, we
1505 can optimize this specific case even more to:
1512 //===---------------------------------------------------------------------===//
1514 Take the following code (from
1515 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=16541):
1517 extern unsigned char first_one[65536];
1518 int FirstOnet(unsigned long long arg1)
1521 return (first_one[arg1 >> 48]);
1526 The following code is currently generated:
1531 jb .LBB1_2 # UnifiedReturnBlock
1534 movzbl first_one(%eax), %eax
1536 .LBB1_2: # UnifiedReturnBlock
1540 There are a few possible improvements here:
1541 1. We should be able to eliminate the dead load into %ecx
1542 2. We could change the "movl 8(%esp), %eax" into
1543 "movzwl 10(%esp), %eax"; this lets us change the cmpl
1544 into a testl, which is shorter, and eliminate the shift.
1546 We could also in theory eliminate the branch by using a conditional
1547 for the address of the load, but that seems unlikely to be worthwhile
1550 //===---------------------------------------------------------------------===//
1552 We compile this function:
1554 define i32 @foo(i32 %a, i32 %b, i32 %c, i8 zeroext %d) nounwind {
1556 %tmp2 = icmp eq i8 %d, 0 ; <i1> [#uses=1]
1557 br i1 %tmp2, label %bb7, label %bb
1559 bb: ; preds = %entry
1560 %tmp6 = add i32 %b, %a ; <i32> [#uses=1]
1563 bb7: ; preds = %entry
1564 %tmp10 = sub i32 %a, %c ; <i32> [#uses=1]
1584 The coalescer could coalesce "edx" with "eax" to avoid the movl in LBB1_2
1585 if it commuted the addl in LBB1_1.
1587 //===---------------------------------------------------------------------===//
1594 cvtss2sd LCPI1_0, %xmm1
1596 movsd 176(%esp), %xmm2
1601 mulsd LCPI1_23, %xmm4
1602 addsd LCPI1_24, %xmm4
1604 addsd LCPI1_25, %xmm4
1606 addsd LCPI1_26, %xmm4
1608 addsd LCPI1_27, %xmm4
1610 addsd LCPI1_28, %xmm4
1614 movsd 152(%esp), %xmm1
1616 movsd %xmm1, 152(%esp)
1620 LBB1_16: # bb358.loopexit
1621 movsd 152(%esp), %xmm0
1623 addsd LCPI1_22, %xmm0
1624 movsd %xmm0, 152(%esp)
1626 Rather than spilling the result of the last addsd in the loop, we should have
1627 insert a copy to split the interval (one for the duration of the loop, one
1628 extending to the fall through). The register pressure in the loop isn't high
1629 enough to warrant the spill.
1631 Also check why xmm7 is not used at all in the function.
1633 //===---------------------------------------------------------------------===//
1635 Legalize loses track of the fact that bools are always zero extended when in
1636 memory. This causes us to compile abort_gzip (from 164.gzip) from:
1638 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
1639 target triple = "i386-apple-darwin8"
1640 @in_exit.4870.b = internal global i1 false ; <i1*> [#uses=2]
1641 define fastcc void @abort_gzip() noreturn nounwind {
1643 %tmp.b.i = load i1* @in_exit.4870.b ; <i1> [#uses=1]
1644 br i1 %tmp.b.i, label %bb.i, label %bb4.i
1645 bb.i: ; preds = %entry
1646 tail call void @exit( i32 1 ) noreturn nounwind
1648 bb4.i: ; preds = %entry
1649 store i1 true, i1* @in_exit.4870.b
1650 tail call void @exit( i32 1 ) noreturn nounwind
1653 declare void @exit(i32) noreturn nounwind
1659 movb _in_exit.4870.b, %al
1666 //===---------------------------------------------------------------------===//
1670 int test(int x, int y) {
1682 it would be better to codegen as: x+~y (notl+addl)
1684 //===---------------------------------------------------------------------===//
1688 int foo(const char *str,...)
1690 __builtin_va_list a; int x;
1691 __builtin_va_start(a,str); x = __builtin_va_arg(a,int); __builtin_va_end(a);
1695 gets compiled into this on x86-64:
1697 movaps %xmm7, 160(%rsp)
1698 movaps %xmm6, 144(%rsp)
1699 movaps %xmm5, 128(%rsp)
1700 movaps %xmm4, 112(%rsp)
1701 movaps %xmm3, 96(%rsp)
1702 movaps %xmm2, 80(%rsp)
1703 movaps %xmm1, 64(%rsp)
1704 movaps %xmm0, 48(%rsp)
1711 movq %rax, 192(%rsp)
1712 leaq 208(%rsp), %rax
1713 movq %rax, 184(%rsp)
1716 movl 176(%rsp), %eax
1720 movq 184(%rsp), %rcx
1722 movq %rax, 184(%rsp)
1730 addq 192(%rsp), %rcx
1731 movl %eax, 176(%rsp)
1737 leaq 104(%rsp), %rax
1738 movq %rsi, -80(%rsp)
1740 movq %rax, -112(%rsp)
1741 leaq -88(%rsp), %rax
1742 movq %rax, -104(%rsp)
1746 movq -112(%rsp), %rdx
1754 addq -104(%rsp), %rdx
1756 movl %eax, -120(%rsp)
1761 and it gets compiled into this on x86:
1781 //===---------------------------------------------------------------------===//
1783 Teach tblgen not to check bitconvert source type in some cases. This allows us
1784 to consolidate the following patterns in X86InstrMMX.td:
1786 def : Pat<(v2i32 (bitconvert (i64 (vector_extract (v2i64 VR128:$src),
1788 (v2i32 (MMX_MOVDQ2Qrr VR128:$src))>;
1789 def : Pat<(v4i16 (bitconvert (i64 (vector_extract (v2i64 VR128:$src),
1791 (v4i16 (MMX_MOVDQ2Qrr VR128:$src))>;
1792 def : Pat<(v8i8 (bitconvert (i64 (vector_extract (v2i64 VR128:$src),
1794 (v8i8 (MMX_MOVDQ2Qrr VR128:$src))>;
1796 There are other cases in various td files.
1798 //===---------------------------------------------------------------------===//
1800 Take something like the following on x86-32:
1801 unsigned a(unsigned long long x, unsigned y) {return x % y;}
1803 We currently generate a libcall, but we really shouldn't: the expansion is
1804 shorter and likely faster than the libcall. The expected code is something
1816 A similar code sequence works for division.
1818 //===---------------------------------------------------------------------===//
1820 These should compile to the same code, but the later codegen's to useless
1821 instructions on X86. This may be a trivial dag combine (GCC PR7061):
1823 struct s1 { unsigned char a, b; };
1824 unsigned long f1(struct s1 x) {
1827 struct s2 { unsigned a: 8, b: 8; };
1828 unsigned long f2(struct s2 x) {
1832 //===---------------------------------------------------------------------===//