1 //===---------------------------------------------------------------------===//
2 // Random ideas for the X86 backend.
3 //===---------------------------------------------------------------------===//
5 Add a MUL2U and MUL2S nodes to represent a multiply that returns both the
6 Hi and Lo parts (combination of MUL and MULH[SU] into one node). Add this to
7 X86, & make the dag combiner produce it when needed. This will eliminate one
8 imul from the code generated for:
10 long long test(long long X, long long Y) { return X*Y; }
12 by using the EAX result from the mul. We should add a similar node for
17 long long test(int X, int Y) { return (long long)X*Y; }
19 ... which should only be one imul instruction.
21 This can be done with a custom expander, but it would be nice to move this to
24 //===---------------------------------------------------------------------===//
26 This should be one DIV/IDIV instruction, not a libcall:
28 unsigned test(unsigned long long X, unsigned Y) {
32 This can be done trivially with a custom legalizer. What about overflow
33 though? http://gcc.gnu.org/bugzilla/show_bug.cgi?id=14224
35 //===---------------------------------------------------------------------===//
37 Improvements to the multiply -> shift/add algorithm:
38 http://gcc.gnu.org/ml/gcc-patches/2004-08/msg01590.html
40 //===---------------------------------------------------------------------===//
42 Improve code like this (occurs fairly frequently, e.g. in LLVM):
43 long long foo(int x) { return 1LL << x; }
45 http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01109.html
46 http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01128.html
47 http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01136.html
49 Another useful one would be ~0ULL >> X and ~0ULL << X.
51 One better solution for 1LL << x is:
60 But that requires good 8-bit subreg support.
62 64-bit shifts (in general) expand to really bad code. Instead of using
63 cmovs, we should expand to a conditional branch like GCC produces.
65 //===---------------------------------------------------------------------===//
68 _Bool f(_Bool a) { return a!=1; }
75 //===---------------------------------------------------------------------===//
79 1. Dynamic programming based approach when compile time if not an
81 2. Code duplication (addressing mode) during isel.
82 3. Other ideas from "Register-Sensitive Selection, Duplication, and
83 Sequencing of Instructions".
84 4. Scheduling for reduced register pressure. E.g. "Minimum Register
85 Instruction Sequence Problem: Revisiting Optimal Code Generation for DAGs"
86 and other related papers.
87 http://citeseer.ist.psu.edu/govindarajan01minimum.html
89 //===---------------------------------------------------------------------===//
91 Should we promote i16 to i32 to avoid partial register update stalls?
93 //===---------------------------------------------------------------------===//
95 Leave any_extend as pseudo instruction and hint to register
96 allocator. Delay codegen until post register allocation.
98 //===---------------------------------------------------------------------===//
100 Count leading zeros and count trailing zeros:
102 int clz(int X) { return __builtin_clz(X); }
103 int ctz(int X) { return __builtin_ctz(X); }
105 $ gcc t.c -S -o - -O3 -fomit-frame-pointer -masm=intel
107 bsr %eax, DWORD PTR [%esp+4]
111 bsf %eax, DWORD PTR [%esp+4]
114 however, check that these are defined for 0 and 32. Our intrinsics are, GCC's
117 //===---------------------------------------------------------------------===//
119 Use push/pop instructions in prolog/epilog sequences instead of stores off
120 ESP (certain code size win, perf win on some [which?] processors).
121 Also, it appears icc use push for parameter passing. Need to investigate.
123 //===---------------------------------------------------------------------===//
125 Only use inc/neg/not instructions on processors where they are faster than
126 add/sub/xor. They are slower on the P4 due to only updating some processor
129 //===---------------------------------------------------------------------===//
131 The instruction selector sometimes misses folding a load into a compare. The
132 pattern is written as (cmp reg, (load p)). Because the compare isn't
133 commutative, it is not matched with the load on both sides. The dag combiner
134 should be made smart enough to cannonicalize the load into the RHS of a compare
135 when it can invert the result of the compare for free.
137 //===---------------------------------------------------------------------===//
139 How about intrinsics? An example is:
140 *res = _mm_mulhi_epu16(*A, _mm_mul_epu32(*B, *C));
143 pmuludq (%eax), %xmm0
148 The transformation probably requires a X86 specific pass or a DAG combiner
149 target specific hook.
151 //===---------------------------------------------------------------------===//
153 In many cases, LLVM generates code like this:
162 on some processors (which ones?), it is more efficient to do this:
171 Doing this correctly is tricky though, as the xor clobbers the flags.
173 //===---------------------------------------------------------------------===//
175 We should generate bts/btr/etc instructions on targets where they are cheap or
176 when codesize is important. e.g., for:
178 void setbit(int *target, int bit) {
179 *target |= (1 << bit);
181 void clearbit(int *target, int bit) {
182 *target &= ~(1 << bit);
185 //===---------------------------------------------------------------------===//
187 Instead of the following for memset char*, 1, 10:
189 movl $16843009, 4(%edx)
190 movl $16843009, (%edx)
193 It might be better to generate
200 when we can spare a register. It reduces code size.
202 //===---------------------------------------------------------------------===//
204 Evaluate what the best way to codegen sdiv X, (2^C) is. For X/8, we currently
221 GCC knows several different ways to codegen it, one of which is this:
231 which is probably slower, but it's interesting at least :)
233 //===---------------------------------------------------------------------===//
235 Should generate min/max for stuff like:
237 void minf(float a, float b, float *X) {
241 Make use of floating point min / max instructions. Perhaps introduce ISD::FMIN
242 and ISD::FMAX node types?
244 //===---------------------------------------------------------------------===//
246 The first BB of this code:
250 %V = call bool %foo()
251 br bool %V, label %T, label %F
268 It would be better to emit "cmp %al, 1" than a xor and test.
270 //===---------------------------------------------------------------------===//
272 Enable X86InstrInfo::convertToThreeAddress().
274 //===---------------------------------------------------------------------===//
276 We are currently lowering large (1MB+) memmove/memcpy to rep/stosl and rep/movsl
277 We should leave these as libcalls for everything over a much lower threshold,
278 since libc is hand tuned for medium and large mem ops (avoiding RFO for large
279 stores, TLB preheating, etc)
281 //===---------------------------------------------------------------------===//
283 Optimize this into something reasonable:
284 x * copysign(1.0, y) * copysign(1.0, z)
286 //===---------------------------------------------------------------------===//
288 Optimize copysign(x, *y) to use an integer load from y.
290 //===---------------------------------------------------------------------===//
292 %X = weak global int 0
295 %N = cast int %N to uint
296 %tmp.24 = setgt int %N, 0
297 br bool %tmp.24, label %no_exit, label %return
300 %indvar = phi uint [ 0, %entry ], [ %indvar.next, %no_exit ]
301 %i.0.0 = cast uint %indvar to int
302 volatile store int %i.0.0, int* %X
303 %indvar.next = add uint %indvar, 1
304 %exitcond = seteq uint %indvar.next, %N
305 br bool %exitcond, label %return, label %no_exit
319 jl LBB_foo_4 # return
320 LBB_foo_1: # no_exit.preheader
323 movl L_X$non_lazy_ptr, %edx
327 jne LBB_foo_2 # no_exit
328 LBB_foo_3: # return.loopexit
332 We should hoist "movl L_X$non_lazy_ptr, %edx" out of the loop after
333 remateralization is implemented. This can be accomplished with 1) a target
334 dependent LICM pass or 2) makeing SelectDAG represent the whole function.
336 //===---------------------------------------------------------------------===//
338 The following tests perform worse with LSR:
340 lambda, siod, optimizer-eval, ackermann, hash2, nestedloop, strcat, and Treesor.
342 //===---------------------------------------------------------------------===//
344 Teach the coalescer to coalesce vregs of different register classes. e.g. FR32 /
347 //===---------------------------------------------------------------------===//
355 Obviously it would have been better for the first mov (or any op) to store
356 directly %esp[0] if there are no other uses.
358 //===---------------------------------------------------------------------===//
360 Adding to the list of cmp / test poor codegen issues:
362 int test(__m128 *A, __m128 *B) {
363 if (_mm_comige_ss(*A, *B))
383 Note the setae, movzbl, cmpl, cmove can be replaced with a single cmovae. There
384 are a number of issues. 1) We are introducing a setcc between the result of the
385 intrisic call and select. 2) The intrinsic is expected to produce a i32 value
386 so a any extend (which becomes a zero extend) is added.
388 We probably need some kind of target DAG combine hook to fix this.
390 //===---------------------------------------------------------------------===//
392 We generate significantly worse code for this than GCC:
393 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=21150
394 http://gcc.gnu.org/bugzilla/attachment.cgi?id=8701
396 There is also one case we do worse on PPC.
398 //===---------------------------------------------------------------------===//
400 If shorter, we should use things like:
405 The former can also be used when the two-addressy nature of the 'and' would
406 require a copy to be inserted (in X86InstrInfo::convertToThreeAddress).
408 //===---------------------------------------------------------------------===//
412 char foo(int x) { return x; }
420 SIGN_EXTEND_INREG can be implemented as (sext (trunc)) to take advantage of
423 //===---------------------------------------------------------------------===//
427 typedef struct pair { float A, B; } pair;
428 void pairtest(pair P, float *FP) {
432 We currently generate this code with llvmgcc4:
447 we should be able to generate:
455 The issue is that llvmgcc4 is forcing the struct to memory, then passing it as
456 integer chunks. It does this so that structs like {short,short} are passed in
457 a single 32-bit integer stack slot. We should handle the safe cases above much
458 nicer, while still handling the hard cases.
460 //===---------------------------------------------------------------------===//
462 Another instruction selector deficiency:
465 %tmp = load int (int)** %foo
466 %tmp = tail call int %tmp( int 3 )
472 movl L_foo$non_lazy_ptr, %eax
478 The current isel scheme will not allow the load to be folded in the call since
479 the load's chain result is read by the callseq_start.
481 //===---------------------------------------------------------------------===//
483 Don't forget to find a way to squash noop truncates in the JIT environment.
485 //===---------------------------------------------------------------------===//
487 Implement anyext in the same manner as truncate that would allow them to be
490 //===---------------------------------------------------------------------===//
492 How about implementing truncate / anyext as a property of machine instruction
493 operand? i.e. Print as 32-bit super-class register / 16-bit sub-class register.
494 Do this for the cases where a truncate / anyext is guaranteed to be eliminated.
495 For IA32 that is truncate from 32 to 16 and anyext from 16 to 32.
497 //===---------------------------------------------------------------------===//
507 imull $3, 4(%esp), %eax
509 Perhaps this is what we really should generate is? Is imull three or four
510 cycles? Note: ICC generates this:
512 leal (%eax,%eax,2), %eax
514 The current instruction priority is based on pattern complexity. The former is
515 more "complex" because it folds a load so the latter will not be emitted.
517 Perhaps we should use AddedComplexity to give LEA32r a higher priority? We
518 should always try to match LEA first since the LEA matching code does some
519 estimate to determine whether the match is profitable.
521 However, if we care more about code size, then imull is better. It's two bytes
522 shorter than movl + leal.
524 //===---------------------------------------------------------------------===//
526 Implement CTTZ, CTLZ with bsf and bsr.
528 //===---------------------------------------------------------------------===//
530 It appears gcc place string data with linkonce linkage in
531 .section __TEXT,__const_coal,coalesced instead of
532 .section __DATA,__const_coal,coalesced.
533 Take a look at darwin.h, there are other Darwin assembler directives that we
536 //===---------------------------------------------------------------------===//
538 We should handle __attribute__ ((__visibility__ ("hidden"))).
540 //===---------------------------------------------------------------------===//
542 int %foo(int* %a, int %t) {
546 cond_true: ; preds = %cond_true, %entry
547 %x.0.0 = phi int [ 0, %entry ], [ %tmp9, %cond_true ]
548 %t_addr.0.0 = phi int [ %t, %entry ], [ %tmp7, %cond_true ]
549 %tmp2 = getelementptr int* %a, int %x.0.0
550 %tmp3 = load int* %tmp2 ; <int> [#uses=1]
551 %tmp5 = add int %t_addr.0.0, %x.0.0 ; <int> [#uses=1]
552 %tmp7 = add int %tmp5, %tmp3 ; <int> [#uses=2]
553 %tmp9 = add int %x.0.0, 1 ; <int> [#uses=2]
554 %tmp = setgt int %tmp9, 39 ; <bool> [#uses=1]
555 br bool %tmp, label %bb12, label %cond_true
557 bb12: ; preds = %cond_true
561 is pessimized by -loop-reduce and -indvars
563 //===---------------------------------------------------------------------===//
565 Use cpuid to auto-detect CPU features such as SSE, SSE2, and SSE3.
567 //===---------------------------------------------------------------------===//
569 u32 to float conversion improvement:
571 float uint32_2_float( unsigned u ) {
572 float fl = (int) (u & 0xffff);
573 float fh = (int) (u >> 16);
578 00000000 subl $0x04,%esp
579 00000003 movl 0x08(%esp,1),%eax
580 00000007 movl %eax,%ecx
581 00000009 shrl $0x10,%ecx
582 0000000c cvtsi2ss %ecx,%xmm0
583 00000010 andl $0x0000ffff,%eax
584 00000015 cvtsi2ss %eax,%xmm1
585 00000019 mulss 0x00000078,%xmm0
586 00000021 addss %xmm1,%xmm0
587 00000025 movss %xmm0,(%esp,1)
588 0000002a flds (%esp,1)
589 0000002d addl $0x04,%esp
592 //===---------------------------------------------------------------------===//
594 When using fastcc abi, align stack slot of argument of type double on 8 byte
595 boundary to improve performance.
597 //===---------------------------------------------------------------------===//
601 int f(int a, int b) {
602 if (a == 4 || a == 6)
614 If we aren't going to do this, we should lower the switch better. We compile
626 jmp LBB1_2 #UnifiedReturnBlock
629 jne LBB1_2 #UnifiedReturnBlock
633 LBB1_2: #UnifiedReturnBlock
636 In the code above, the 'if' is turned into a 'switch' at the mid-level. It
637 looks like the 'lower to branches' mode could be improved a little here. In
638 particular, the fall-through to LBB1_3 doesn't need a branch. It would also be
639 nice to eliminate the redundant "cmp 6", maybe by lowering to a linear sequence
640 of compares if there are below a certain number of cases (instead of a binary
643 //===---------------------------------------------------------------------===//
646 int %test(ulong *%tmp) {
647 %tmp = load ulong* %tmp ; <ulong> [#uses=1]
648 %tmp.mask = shr ulong %tmp, ubyte 50 ; <ulong> [#uses=1]
649 %tmp.mask = cast ulong %tmp.mask to ubyte
650 %tmp2 = and ubyte %tmp.mask, 3 ; <ubyte> [#uses=1]
651 %tmp2 = cast ubyte %tmp2 to int ; <int> [#uses=1]
670 # TRUNCATE movb %al, %al
675 This saves a movzbl, and saves a truncate if it doesn't get coallesced right.
676 This is a simple DAGCombine to propagate the zext through the and.
678 //===---------------------------------------------------------------------===//
680 GCC's ix86_expand_int_movcc function (in i386.c) has a ton of interesting
681 simplifications for integer "x cmp y ? a : b". For example, instead of:
684 void f(int X, int Y) {
710 //===---------------------------------------------------------------------===//
712 Currently we don't have elimination of redundant stack manipulations. Consider
717 call fastcc void %test1( )
718 call fastcc void %test2( sbyte* cast (void ()* %test1 to sbyte*) )
722 declare fastcc void %test1()
724 declare fastcc void %test2(sbyte*)
727 This currently compiles to:
737 The add\sub pair is really unneeded here.
739 //===---------------------------------------------------------------------===//
741 We generate really bad code in some cases due to lowering SETCC/SELECT at
742 legalize time, which prevents the post-legalize dag combine pass from
743 understanding the code. As a silly example, this prevents us from folding
746 bool %test(ulong %x) {
747 %tmp = setlt ulong %x, 4294967296