1 //===---------------------------------------------------------------------===//
2 // Random ideas for the X86 backend.
3 //===---------------------------------------------------------------------===//
6 //===---------------------------------------------------------------------===//
8 CodeGen/X86/lea-3.ll:test3 should be a single LEA, not a shift/move. The X86
9 backend knows how to three-addressify this shift, but it appears the register
10 allocator isn't even asking it to do so in this case. We should investigate
11 why this isn't happening, it could have significant impact on other important
12 cases for X86 as well.
14 //===---------------------------------------------------------------------===//
16 This should be one DIV/IDIV instruction, not a libcall:
18 unsigned test(unsigned long long X, unsigned Y) {
22 This can be done trivially with a custom legalizer. What about overflow
23 though? http://gcc.gnu.org/bugzilla/show_bug.cgi?id=14224
25 //===---------------------------------------------------------------------===//
27 Improvements to the multiply -> shift/add algorithm:
28 http://gcc.gnu.org/ml/gcc-patches/2004-08/msg01590.html
30 //===---------------------------------------------------------------------===//
32 Improve code like this (occurs fairly frequently, e.g. in LLVM):
33 long long foo(int x) { return 1LL << x; }
35 http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01109.html
36 http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01128.html
37 http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01136.html
39 Another useful one would be ~0ULL >> X and ~0ULL << X.
41 One better solution for 1LL << x is:
50 But that requires good 8-bit subreg support.
52 Also, this might be better. It's an extra shift, but it's one instruction
53 shorter, and doesn't stress 8-bit subreg support.
54 (From http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01148.html,
55 but without the unnecessary and.)
63 64-bit shifts (in general) expand to really bad code. Instead of using
64 cmovs, we should expand to a conditional branch like GCC produces.
66 //===---------------------------------------------------------------------===//
69 _Bool f(_Bool a) { return a!=1; }
76 (Although note that this isn't a legal way to express the code that llvm-gcc
77 currently generates for that function.)
79 //===---------------------------------------------------------------------===//
83 1. Dynamic programming based approach when compile time if not an
85 2. Code duplication (addressing mode) during isel.
86 3. Other ideas from "Register-Sensitive Selection, Duplication, and
87 Sequencing of Instructions".
88 4. Scheduling for reduced register pressure. E.g. "Minimum Register
89 Instruction Sequence Problem: Revisiting Optimal Code Generation for DAGs"
90 and other related papers.
91 http://citeseer.ist.psu.edu/govindarajan01minimum.html
93 //===---------------------------------------------------------------------===//
95 Should we promote i16 to i32 to avoid partial register update stalls?
97 //===---------------------------------------------------------------------===//
99 Leave any_extend as pseudo instruction and hint to register
100 allocator. Delay codegen until post register allocation.
101 Note. any_extend is now turned into an INSERT_SUBREG. We still need to teach
102 the coalescer how to deal with it though.
104 //===---------------------------------------------------------------------===//
106 It appears icc use push for parameter passing. Need to investigate.
108 //===---------------------------------------------------------------------===//
110 Only use inc/neg/not instructions on processors where they are faster than
111 add/sub/xor. They are slower on the P4 due to only updating some processor
114 //===---------------------------------------------------------------------===//
116 The instruction selector sometimes misses folding a load into a compare. The
117 pattern is written as (cmp reg, (load p)). Because the compare isn't
118 commutative, it is not matched with the load on both sides. The dag combiner
119 should be made smart enough to cannonicalize the load into the RHS of a compare
120 when it can invert the result of the compare for free.
122 //===---------------------------------------------------------------------===//
124 How about intrinsics? An example is:
125 *res = _mm_mulhi_epu16(*A, _mm_mul_epu32(*B, *C));
128 pmuludq (%eax), %xmm0
133 The transformation probably requires a X86 specific pass or a DAG combiner
134 target specific hook.
136 //===---------------------------------------------------------------------===//
138 In many cases, LLVM generates code like this:
147 on some processors (which ones?), it is more efficient to do this:
156 Doing this correctly is tricky though, as the xor clobbers the flags.
158 //===---------------------------------------------------------------------===//
160 We should generate bts/btr/etc instructions on targets where they are cheap or
161 when codesize is important. e.g., for:
163 void setbit(int *target, int bit) {
164 *target |= (1 << bit);
166 void clearbit(int *target, int bit) {
167 *target &= ~(1 << bit);
170 //===---------------------------------------------------------------------===//
172 Instead of the following for memset char*, 1, 10:
174 movl $16843009, 4(%edx)
175 movl $16843009, (%edx)
178 It might be better to generate
185 when we can spare a register. It reduces code size.
187 //===---------------------------------------------------------------------===//
189 Evaluate what the best way to codegen sdiv X, (2^C) is. For X/8, we currently
192 define i32 @test1(i32 %X) {
206 GCC knows several different ways to codegen it, one of which is this:
216 which is probably slower, but it's interesting at least :)
218 //===---------------------------------------------------------------------===//
220 We are currently lowering large (1MB+) memmove/memcpy to rep/stosl and rep/movsl
221 We should leave these as libcalls for everything over a much lower threshold,
222 since libc is hand tuned for medium and large mem ops (avoiding RFO for large
223 stores, TLB preheating, etc)
225 //===---------------------------------------------------------------------===//
227 Optimize this into something reasonable:
228 x * copysign(1.0, y) * copysign(1.0, z)
230 //===---------------------------------------------------------------------===//
232 Optimize copysign(x, *y) to use an integer load from y.
234 //===---------------------------------------------------------------------===//
236 %X = weak global int 0
239 %N = cast int %N to uint
240 %tmp.24 = setgt int %N, 0
241 br bool %tmp.24, label %no_exit, label %return
244 %indvar = phi uint [ 0, %entry ], [ %indvar.next, %no_exit ]
245 %i.0.0 = cast uint %indvar to int
246 volatile store int %i.0.0, int* %X
247 %indvar.next = add uint %indvar, 1
248 %exitcond = seteq uint %indvar.next, %N
249 br bool %exitcond, label %return, label %no_exit
263 jl LBB_foo_4 # return
264 LBB_foo_1: # no_exit.preheader
267 movl L_X$non_lazy_ptr, %edx
271 jne LBB_foo_2 # no_exit
272 LBB_foo_3: # return.loopexit
276 We should hoist "movl L_X$non_lazy_ptr, %edx" out of the loop after
277 remateralization is implemented. This can be accomplished with 1) a target
278 dependent LICM pass or 2) makeing SelectDAG represent the whole function.
280 //===---------------------------------------------------------------------===//
282 The following tests perform worse with LSR:
284 lambda, siod, optimizer-eval, ackermann, hash2, nestedloop, strcat, and Treesor.
286 //===---------------------------------------------------------------------===//
288 We are generating far worse code than gcc:
294 for (i = 0; i < N; i++) { X = i; Y = i*4; }
297 LBB1_1: # entry.bb_crit_edge
301 movl L_X$non_lazy_ptr, %esi
303 movl L_Y$non_lazy_ptr, %esi
313 movl L_X$non_lazy_ptr-"L00000000001$pb"(%ebx), %esi
314 movl L_Y$non_lazy_ptr-"L00000000001$pb"(%ebx), %ecx
317 leal 0(,%edx,4), %eax
323 This is due to the lack of post regalloc LICM.
325 //===---------------------------------------------------------------------===//
327 Teach the coalescer to coalesce vregs of different register classes. e.g. FR32 /
330 //===---------------------------------------------------------------------===//
332 Adding to the list of cmp / test poor codegen issues:
334 int test(__m128 *A, __m128 *B) {
335 if (_mm_comige_ss(*A, *B))
355 Note the setae, movzbl, cmpl, cmove can be replaced with a single cmovae. There
356 are a number of issues. 1) We are introducing a setcc between the result of the
357 intrisic call and select. 2) The intrinsic is expected to produce a i32 value
358 so a any extend (which becomes a zero extend) is added.
360 We probably need some kind of target DAG combine hook to fix this.
362 //===---------------------------------------------------------------------===//
364 We generate significantly worse code for this than GCC:
365 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=21150
366 http://gcc.gnu.org/bugzilla/attachment.cgi?id=8701
368 There is also one case we do worse on PPC.
370 //===---------------------------------------------------------------------===//
380 imull $3, 4(%esp), %eax
382 Perhaps this is what we really should generate is? Is imull three or four
383 cycles? Note: ICC generates this:
385 leal (%eax,%eax,2), %eax
387 The current instruction priority is based on pattern complexity. The former is
388 more "complex" because it folds a load so the latter will not be emitted.
390 Perhaps we should use AddedComplexity to give LEA32r a higher priority? We
391 should always try to match LEA first since the LEA matching code does some
392 estimate to determine whether the match is profitable.
394 However, if we care more about code size, then imull is better. It's two bytes
395 shorter than movl + leal.
397 //===---------------------------------------------------------------------===//
399 __builtin_ffs codegen is messy.
401 int ffs_(unsigned X) { return __builtin_ffs(X); }
424 Another example of __builtin_ffs (use predsimplify to eliminate a select):
426 int foo (unsigned long j) {
428 return __builtin_ffs (j) - 1;
433 //===---------------------------------------------------------------------===//
435 It appears gcc place string data with linkonce linkage in
436 .section __TEXT,__const_coal,coalesced instead of
437 .section __DATA,__const_coal,coalesced.
438 Take a look at darwin.h, there are other Darwin assembler directives that we
441 //===---------------------------------------------------------------------===//
443 define i32 @foo(i32* %a, i32 %t) {
447 cond_true: ; preds = %cond_true, %entry
448 %x.0.0 = phi i32 [ 0, %entry ], [ %tmp9, %cond_true ] ; <i32> [#uses=3]
449 %t_addr.0.0 = phi i32 [ %t, %entry ], [ %tmp7, %cond_true ] ; <i32> [#uses=1]
450 %tmp2 = getelementptr i32* %a, i32 %x.0.0 ; <i32*> [#uses=1]
451 %tmp3 = load i32* %tmp2 ; <i32> [#uses=1]
452 %tmp5 = add i32 %t_addr.0.0, %x.0.0 ; <i32> [#uses=1]
453 %tmp7 = add i32 %tmp5, %tmp3 ; <i32> [#uses=2]
454 %tmp9 = add i32 %x.0.0, 1 ; <i32> [#uses=2]
455 %tmp = icmp sgt i32 %tmp9, 39 ; <i1> [#uses=1]
456 br i1 %tmp, label %bb12, label %cond_true
458 bb12: ; preds = %cond_true
461 is pessimized by -loop-reduce and -indvars
463 //===---------------------------------------------------------------------===//
465 u32 to float conversion improvement:
467 float uint32_2_float( unsigned u ) {
468 float fl = (int) (u & 0xffff);
469 float fh = (int) (u >> 16);
474 00000000 subl $0x04,%esp
475 00000003 movl 0x08(%esp,1),%eax
476 00000007 movl %eax,%ecx
477 00000009 shrl $0x10,%ecx
478 0000000c cvtsi2ss %ecx,%xmm0
479 00000010 andl $0x0000ffff,%eax
480 00000015 cvtsi2ss %eax,%xmm1
481 00000019 mulss 0x00000078,%xmm0
482 00000021 addss %xmm1,%xmm0
483 00000025 movss %xmm0,(%esp,1)
484 0000002a flds (%esp,1)
485 0000002d addl $0x04,%esp
488 //===---------------------------------------------------------------------===//
490 When using fastcc abi, align stack slot of argument of type double on 8 byte
491 boundary to improve performance.
493 //===---------------------------------------------------------------------===//
497 int f(int a, int b) {
498 if (a == 4 || a == 6)
510 //===---------------------------------------------------------------------===//
512 GCC's ix86_expand_int_movcc function (in i386.c) has a ton of interesting
513 simplifications for integer "x cmp y ? a : b". For example, instead of:
516 void f(int X, int Y) {
543 int usesbb(unsigned int a, unsigned int b) {
544 return (a < b ? -1 : 0);
558 movl $4294967295, %ecx
562 //===---------------------------------------------------------------------===//
564 Currently we don't have elimination of redundant stack manipulations. Consider
569 call fastcc void %test1( )
570 call fastcc void %test2( sbyte* cast (void ()* %test1 to sbyte*) )
574 declare fastcc void %test1()
576 declare fastcc void %test2(sbyte*)
579 This currently compiles to:
589 The add\sub pair is really unneeded here.
591 //===---------------------------------------------------------------------===//
593 Consider the expansion of:
595 define i32 @test3(i32 %X) {
596 %tmp1 = urem i32 %X, 255
600 Currently it compiles to:
603 movl $2155905153, %ecx
609 This could be "reassociated" into:
611 movl $2155905153, %eax
615 to avoid the copy. In fact, the existing two-address stuff would do this
616 except that mul isn't a commutative 2-addr instruction. I guess this has
617 to be done at isel time based on the #uses to mul?
619 //===---------------------------------------------------------------------===//
621 Make sure the instruction which starts a loop does not cross a cacheline
622 boundary. This requires knowning the exact length of each machine instruction.
623 That is somewhat complicated, but doable. Example 256.bzip2:
625 In the new trace, the hot loop has an instruction which crosses a cacheline
626 boundary. In addition to potential cache misses, this can't help decoding as I
627 imagine there has to be some kind of complicated decoder reset and realignment
628 to grab the bytes from the next cacheline.
630 532 532 0x3cfc movb (1809(%esp, %esi), %bl <<<--- spans 2 64 byte lines
631 942 942 0x3d03 movl %dh, (1809(%esp, %esi)
632 937 937 0x3d0a incl %esi
633 3 3 0x3d0b cmpb %bl, %dl
634 27 27 0x3d0d jnz 0x000062db <main+11707>
636 //===---------------------------------------------------------------------===//
638 In c99 mode, the preprocessor doesn't like assembly comments like #TRUNCATE.
640 //===---------------------------------------------------------------------===//
642 This could be a single 16-bit load.
645 if ((p[0] == 1) & (p[1] == 2)) return 1;
649 //===---------------------------------------------------------------------===//
651 We should inline lrintf and probably other libc functions.
653 //===---------------------------------------------------------------------===//
655 Start using the flags more. For example, compile:
657 int add_zf(int *x, int y, int a, int b) {
681 int add_zf(int *x, int y, int a, int b) {
705 //===---------------------------------------------------------------------===//
707 These two functions have identical effects:
709 unsigned int f(unsigned int i, unsigned int n) {++i; if (i == n) ++i; return i;}
710 unsigned int f2(unsigned int i, unsigned int n) {++i; i += i == n; return i;}
712 We currently compile them to:
720 jne LBB1_2 #UnifiedReturnBlock
724 LBB1_2: #UnifiedReturnBlock
734 leal 1(%ecx,%eax), %eax
737 both of which are inferior to GCC's:
755 //===---------------------------------------------------------------------===//
763 is currently compiled to:
774 It would be better to produce:
783 This can be applied to any no-return function call that takes no arguments etc.
784 Alternatively, the stack save/restore logic could be shrink-wrapped, producing
795 Both are useful in different situations. Finally, it could be shrink-wrapped
796 and tail called, like this:
803 pop %eax # realign stack.
806 Though this probably isn't worth it.
808 //===---------------------------------------------------------------------===//
810 We need to teach the codegen to convert two-address INC instructions to LEA
811 when the flags are dead (likewise dec). For example, on X86-64, compile:
813 int foo(int A, int B) {
832 ;; X's live range extends beyond the shift, so the register allocator
833 ;; cannot coalesce it with Y. Because of this, a copy needs to be
834 ;; emitted before the shift to save the register value before it is
835 ;; clobbered. However, this copy is not needed if the register
836 ;; allocator turns the shift into an LEA. This also occurs for ADD.
838 ; Check that the shift gets turned into an LEA.
839 ; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | \
840 ; RUN: not grep {mov E.X, E.X}
842 @G = external global i32 ; <i32*> [#uses=3]
844 define i32 @test1(i32 %X, i32 %Y) {
845 %Z = add i32 %X, %Y ; <i32> [#uses=1]
846 volatile store i32 %Y, i32* @G
847 volatile store i32 %Z, i32* @G
851 define i32 @test2(i32 %X) {
852 %Z = add i32 %X, 1 ; <i32> [#uses=1]
853 volatile store i32 %Z, i32* @G
857 //===---------------------------------------------------------------------===//
859 Sometimes it is better to codegen subtractions from a constant (e.g. 7-x) with
860 a neg instead of a sub instruction. Consider:
862 int test(char X) { return 7-X; }
864 we currently produce:
871 We would use one fewer register if codegen'd as:
878 Note that this isn't beneficial if the load can be folded into the sub. In
879 this case, we want a sub:
881 int test(int X) { return 7-X; }
887 //===---------------------------------------------------------------------===//
889 Leaf functions that require one 4-byte spill slot have a prolog like this:
895 and an epilog like this:
900 It would be smaller, and potentially faster, to push eax on entry and to
901 pop into a dummy register instead of using addl/subl of esp. Just don't pop
902 into any return registers :)
904 //===---------------------------------------------------------------------===//
906 The X86 backend should fold (branch (or (setcc, setcc))) into multiple
907 branches. We generate really poor code for:
909 double testf(double a) {
910 return a == 0.0 ? 0.0 : (a > 0.0 ? 1.0 : -1.0);
913 For example, the entry BB is:
918 movsd 24(%esp), %xmm1
923 jne LBB1_5 # UnifiedReturnBlock
927 it would be better to replace the last four instructions with:
933 We also codegen the inner ?: into a diamond:
935 cvtss2sd LCPI1_0(%rip), %xmm2
936 cvtss2sd LCPI1_1(%rip), %xmm3
938 ja LBB1_3 # cond_true
945 We should sink the load into xmm3 into the LBB1_2 block. This should
946 be pretty easy, and will nuke all the copies.
948 //===---------------------------------------------------------------------===//
952 inline std::pair<unsigned, bool> full_add(unsigned a, unsigned b)
953 { return std::make_pair(a + b, a + b < a); }
954 bool no_overflow(unsigned a, unsigned b)
955 { return !full_add(a, b).second; }
965 FIXME: That code looks wrong; bool return is normally defined as zext.
977 //===---------------------------------------------------------------------===//
979 Re-materialize MOV32r0 etc. with xor instead of changing them to moves if the
980 condition register is dead. xor reg reg is shorter than mov reg, #0.
982 //===---------------------------------------------------------------------===//
984 We aren't matching RMW instructions aggressively
985 enough. Here's a reduced testcase (more in PR1160):
987 define void @test(i32* %huge_ptr, i32* %target_ptr) {
988 %A = load i32* %huge_ptr ; <i32> [#uses=1]
989 %B = load i32* %target_ptr ; <i32> [#uses=1]
990 %C = or i32 %A, %B ; <i32> [#uses=1]
991 store i32 %C, i32* %target_ptr
995 $ llvm-as < t.ll | llc -march=x86-64
1003 That should be something like:
1010 //===---------------------------------------------------------------------===//
1014 bb114.preheader: ; preds = %cond_next94
1015 %tmp231232 = sext i16 %tmp62 to i32 ; <i32> [#uses=1]
1016 %tmp233 = sub i32 32, %tmp231232 ; <i32> [#uses=1]
1017 %tmp245246 = sext i16 %tmp65 to i32 ; <i32> [#uses=1]
1018 %tmp252253 = sext i16 %tmp68 to i32 ; <i32> [#uses=1]
1019 %tmp254 = sub i32 32, %tmp252253 ; <i32> [#uses=1]
1020 %tmp553554 = bitcast i16* %tmp37 to i8* ; <i8*> [#uses=2]
1021 %tmp583584 = sext i16 %tmp98 to i32 ; <i32> [#uses=1]
1022 %tmp585 = sub i32 32, %tmp583584 ; <i32> [#uses=1]
1023 %tmp614615 = sext i16 %tmp101 to i32 ; <i32> [#uses=1]
1024 %tmp621622 = sext i16 %tmp104 to i32 ; <i32> [#uses=1]
1025 %tmp623 = sub i32 32, %tmp621622 ; <i32> [#uses=1]
1030 LBB3_5: # bb114.preheader
1031 movswl -68(%ebp), %eax
1033 movl %ecx, -80(%ebp)
1034 subl %eax, -80(%ebp)
1035 movswl -52(%ebp), %eax
1036 movl %ecx, -84(%ebp)
1037 subl %eax, -84(%ebp)
1038 movswl -70(%ebp), %eax
1039 movl %ecx, -88(%ebp)
1040 subl %eax, -88(%ebp)
1041 movswl -50(%ebp), %eax
1043 movl %ecx, -76(%ebp)
1044 movswl -42(%ebp), %eax
1045 movl %eax, -92(%ebp)
1046 movswl -66(%ebp), %eax
1047 movl %eax, -96(%ebp)
1050 This appears to be bad because the RA is not folding the store to the stack
1051 slot into the movl. The above instructions could be:
1056 This seems like a cross between remat and spill folding.
1058 This has redundant subtractions of %eax from a stack slot. However, %ecx doesn't
1059 change, so we could simply subtract %eax from %ecx first and then use %ecx (or
1062 //===---------------------------------------------------------------------===//
1066 %tmp659 = icmp slt i16 %tmp654, 0 ; <i1> [#uses=1]
1067 br i1 %tmp659, label %cond_true662, label %cond_next715
1073 jns LBB4_109 # cond_next715
1075 Shark tells us that using %cx in the testw instruction is sub-optimal. It
1076 suggests using the 32-bit register (which is what ICC uses).
1078 //===---------------------------------------------------------------------===//
1082 void compare (long long foo) {
1083 if (foo < 4294967297LL)
1099 jne .LBB1_2 # UnifiedReturnBlock
1102 .LBB1_2: # UnifiedReturnBlock
1106 (also really horrible code on ppc). This is due to the expand code for 64-bit
1107 compares. GCC produces multiple branches, which is much nicer:
1128 //===---------------------------------------------------------------------===//
1130 Tail call optimization improvements: Tail call optimization currently
1131 pushes all arguments on the top of the stack (their normal place for
1132 non-tail call optimized calls) that source from the callers arguments
1133 or that source from a virtual register (also possibly sourcing from
1135 This is done to prevent overwriting of parameters (see example
1136 below) that might be used later.
1140 int callee(int32, int64);
1141 int caller(int32 arg1, int32 arg2) {
1142 int64 local = arg2 * 2;
1143 return callee(arg2, (int64)local);
1146 [arg1] [!arg2 no longer valid since we moved local onto it]
1150 Moving arg1 onto the stack slot of callee function would overwrite
1153 Possible optimizations:
1156 - Analyse the actual parameters of the callee to see which would
1157 overwrite a caller parameter which is used by the callee and only
1158 push them onto the top of the stack.
1160 int callee (int32 arg1, int32 arg2);
1161 int caller (int32 arg1, int32 arg2) {
1162 return callee(arg1,arg2);
1165 Here we don't need to write any variables to the top of the stack
1166 since they don't overwrite each other.
1168 int callee (int32 arg1, int32 arg2);
1169 int caller (int32 arg1, int32 arg2) {
1170 return callee(arg2,arg1);
1173 Here we need to push the arguments because they overwrite each
1176 //===---------------------------------------------------------------------===//
1181 unsigned long int z = 0;
1192 gcc compiles this to:
1218 jge LBB1_4 # cond_true
1221 addl $4294950912, %ecx
1231 1. LSR should rewrite the first cmp with induction variable %ecx.
1232 2. DAG combiner should fold
1238 //===---------------------------------------------------------------------===//
1240 define i64 @test(double %X) {
1241 %Y = fptosi double %X to i64
1249 movsd 24(%esp), %xmm0
1250 movsd %xmm0, 8(%esp)
1259 This should just fldl directly from the input stack slot.
1261 //===---------------------------------------------------------------------===//
1264 int foo (int x) { return (x & 65535) | 255; }
1266 Should compile into:
1269 movzwl 4(%esp), %eax
1280 //===---------------------------------------------------------------------===//
1282 We're codegen'ing multiply of long longs inefficiently:
1284 unsigned long long LLM(unsigned long long arg1, unsigned long long arg2) {
1288 We compile to (fomit-frame-pointer):
1296 imull 12(%esp), %esi
1298 imull 20(%esp), %ecx
1304 This looks like a scheduling deficiency and lack of remat of the load from
1305 the argument area. ICC apparently produces:
1308 imull 12(%esp), %ecx
1317 Note that it remat'd loads from 4(esp) and 12(esp). See this GCC PR:
1318 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=17236
1320 //===---------------------------------------------------------------------===//
1322 We can fold a store into "zeroing a reg". Instead of:
1325 movl %eax, 124(%esp)
1331 if the flags of the xor are dead.
1333 Likewise, we isel "x<<1" into "add reg,reg". If reg is spilled, this should
1334 be folded into: shl [mem], 1
1336 //===---------------------------------------------------------------------===//
1338 This testcase misses a read/modify/write opportunity (from PR1425):
1340 void vertical_decompose97iH1(int *b0, int *b1, int *b2, int width){
1342 for(i=0; i<width; i++)
1343 b1[i] += (1*(b0[i] + b2[i])+0)>>0;
1346 We compile it down to:
1349 movl (%esi,%edi,4), %ebx
1350 addl (%ecx,%edi,4), %ebx
1351 addl (%edx,%edi,4), %ebx
1352 movl %ebx, (%ecx,%edi,4)
1357 the inner loop should add to the memory location (%ecx,%edi,4), saving
1358 a mov. Something like:
1360 movl (%esi,%edi,4), %ebx
1361 addl (%edx,%edi,4), %ebx
1362 addl %ebx, (%ecx,%edi,4)
1364 Here is another interesting example:
1366 void vertical_compose97iH1(int *b0, int *b1, int *b2, int width){
1368 for(i=0; i<width; i++)
1369 b1[i] -= (1*(b0[i] + b2[i])+0)>>0;
1372 We miss the r/m/w opportunity here by using 2 subs instead of an add+sub[mem]:
1375 movl (%ecx,%edi,4), %ebx
1376 subl (%esi,%edi,4), %ebx
1377 subl (%edx,%edi,4), %ebx
1378 movl %ebx, (%ecx,%edi,4)
1383 Additionally, LSR should rewrite the exit condition of these loops to use
1384 a stride-4 IV, would would allow all the scales in the loop to go away.
1385 This would result in smaller code and more efficient microops.
1387 //===---------------------------------------------------------------------===//
1389 In SSE mode, we turn abs and neg into a load from the constant pool plus a xor
1390 or and instruction, for example:
1392 xorpd LCPI1_0, %xmm2
1394 However, if xmm2 gets spilled, we end up with really ugly code like this:
1397 xorpd LCPI1_0, %xmm0
1400 Since we 'know' that this is a 'neg', we can actually "fold" the spill into
1401 the neg/abs instruction, turning it into an *integer* operation, like this:
1403 xorl 2147483648, [mem+4] ## 2147483648 = (1 << 31)
1405 you could also use xorb, but xorl is less likely to lead to a partial register
1406 stall. Here is a contrived testcase:
1409 void test(double *P) {
1419 //===---------------------------------------------------------------------===//
1421 handling llvm.memory.barrier on pre SSE2 cpus
1424 lock ; mov %esp, %esp
1426 //===---------------------------------------------------------------------===//
1428 The generated code on x86 for checking for signed overflow on a multiply the
1429 obvious way is much longer than it needs to be.
1431 int x(int a, int b) {
1432 long long prod = (long long)a*b;
1433 return prod > 0x7FFFFFFF || prod < (-0x7FFFFFFF-1);
1436 See PR2053 for more details.
1438 //===---------------------------------------------------------------------===//
1440 We should investigate using cdq/ctld (effect: edx = sar eax, 31)
1441 more aggressively; it should cost the same as a move+shift on any modern
1442 processor, but it's a lot shorter. Downside is that it puts more
1443 pressure on register allocation because it has fixed operands.
1446 int abs(int x) {return x < 0 ? -x : x;}
1448 gcc compiles this to the following when using march/mtune=pentium2/3/4/m/etc.:
1456 //===---------------------------------------------------------------------===//
1459 int test(unsigned long a, unsigned long b) { return -(a < b); }
1461 We currently compile this to:
1463 define i32 @test(i32 %a, i32 %b) nounwind {
1464 %tmp3 = icmp ult i32 %a, %b ; <i1> [#uses=1]
1465 %tmp34 = zext i1 %tmp3 to i32 ; <i32> [#uses=1]
1466 %tmp5 = sub i32 0, %tmp34 ; <i32> [#uses=1]
1480 Several deficiencies here. First, we should instcombine zext+neg into sext:
1482 define i32 @test2(i32 %a, i32 %b) nounwind {
1483 %tmp3 = icmp ult i32 %a, %b ; <i1> [#uses=1]
1484 %tmp34 = sext i1 %tmp3 to i32 ; <i32> [#uses=1]
1488 However, before we can do that, we have to fix the bad codegen that we get for
1500 This code should be at least as good as the code above. Once this is fixed, we
1501 can optimize this specific case even more to:
1508 //===---------------------------------------------------------------------===//
1510 Take the following code (from
1511 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=16541):
1513 extern unsigned char first_one[65536];
1514 int FirstOnet(unsigned long long arg1)
1517 return (first_one[arg1 >> 48]);
1522 The following code is currently generated:
1527 jb .LBB1_2 # UnifiedReturnBlock
1530 movzbl first_one(%eax), %eax
1532 .LBB1_2: # UnifiedReturnBlock
1536 There are a few possible improvements here:
1537 1. We should be able to eliminate the dead load into %ecx
1538 2. We could change the "movl 8(%esp), %eax" into
1539 "movzwl 10(%esp), %eax"; this lets us change the cmpl
1540 into a testl, which is shorter, and eliminate the shift.
1542 We could also in theory eliminate the branch by using a conditional
1543 for the address of the load, but that seems unlikely to be worthwhile
1546 //===---------------------------------------------------------------------===//
1548 We compile this function:
1550 define i32 @foo(i32 %a, i32 %b, i32 %c, i8 zeroext %d) nounwind {
1552 %tmp2 = icmp eq i8 %d, 0 ; <i1> [#uses=1]
1553 br i1 %tmp2, label %bb7, label %bb
1555 bb: ; preds = %entry
1556 %tmp6 = add i32 %b, %a ; <i32> [#uses=1]
1559 bb7: ; preds = %entry
1560 %tmp10 = sub i32 %a, %c ; <i32> [#uses=1]
1580 The coalescer could coalesce "edx" with "eax" to avoid the movl in LBB1_2
1581 if it commuted the addl in LBB1_1.
1583 //===---------------------------------------------------------------------===//
1590 cvtss2sd LCPI1_0, %xmm1
1592 movsd 176(%esp), %xmm2
1597 mulsd LCPI1_23, %xmm4
1598 addsd LCPI1_24, %xmm4
1600 addsd LCPI1_25, %xmm4
1602 addsd LCPI1_26, %xmm4
1604 addsd LCPI1_27, %xmm4
1606 addsd LCPI1_28, %xmm4
1610 movsd 152(%esp), %xmm1
1612 movsd %xmm1, 152(%esp)
1616 LBB1_16: # bb358.loopexit
1617 movsd 152(%esp), %xmm0
1619 addsd LCPI1_22, %xmm0
1620 movsd %xmm0, 152(%esp)
1622 Rather than spilling the result of the last addsd in the loop, we should have
1623 insert a copy to split the interval (one for the duration of the loop, one
1624 extending to the fall through). The register pressure in the loop isn't high
1625 enough to warrant the spill.
1627 Also check why xmm7 is not used at all in the function.
1629 //===---------------------------------------------------------------------===//
1631 Legalize loses track of the fact that bools are always zero extended when in
1632 memory. This causes us to compile abort_gzip (from 164.gzip) from:
1634 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
1635 target triple = "i386-apple-darwin8"
1636 @in_exit.4870.b = internal global i1 false ; <i1*> [#uses=2]
1637 define fastcc void @abort_gzip() noreturn nounwind {
1639 %tmp.b.i = load i1* @in_exit.4870.b ; <i1> [#uses=1]
1640 br i1 %tmp.b.i, label %bb.i, label %bb4.i
1641 bb.i: ; preds = %entry
1642 tail call void @exit( i32 1 ) noreturn nounwind
1644 bb4.i: ; preds = %entry
1645 store i1 true, i1* @in_exit.4870.b
1646 tail call void @exit( i32 1 ) noreturn nounwind
1649 declare void @exit(i32) noreturn nounwind
1655 movb _in_exit.4870.b, %al
1662 //===---------------------------------------------------------------------===//
1666 int test(int x, int y) {
1678 it would be better to codegen as: x+~y (notl+addl)
1680 //===---------------------------------------------------------------------===//
1684 int foo(const char *str,...)
1686 __builtin_va_list a; int x;
1687 __builtin_va_start(a,str); x = __builtin_va_arg(a,int); __builtin_va_end(a);
1691 gets compiled into this on x86-64:
1693 movaps %xmm7, 160(%rsp)
1694 movaps %xmm6, 144(%rsp)
1695 movaps %xmm5, 128(%rsp)
1696 movaps %xmm4, 112(%rsp)
1697 movaps %xmm3, 96(%rsp)
1698 movaps %xmm2, 80(%rsp)
1699 movaps %xmm1, 64(%rsp)
1700 movaps %xmm0, 48(%rsp)
1707 movq %rax, 192(%rsp)
1708 leaq 208(%rsp), %rax
1709 movq %rax, 184(%rsp)
1712 movl 176(%rsp), %eax
1716 movq 184(%rsp), %rcx
1718 movq %rax, 184(%rsp)
1726 addq 192(%rsp), %rcx
1727 movl %eax, 176(%rsp)
1733 leaq 104(%rsp), %rax
1734 movq %rsi, -80(%rsp)
1736 movq %rax, -112(%rsp)
1737 leaq -88(%rsp), %rax
1738 movq %rax, -104(%rsp)
1742 movq -112(%rsp), %rdx
1750 addq -104(%rsp), %rdx
1752 movl %eax, -120(%rsp)
1757 and it gets compiled into this on x86:
1777 //===---------------------------------------------------------------------===//
1779 Teach tblgen not to check bitconvert source type in some cases. This allows us
1780 to consolidate the following patterns in X86InstrMMX.td:
1782 def : Pat<(v2i32 (bitconvert (i64 (vector_extract (v2i64 VR128:$src),
1784 (v2i32 (MMX_MOVDQ2Qrr VR128:$src))>;
1785 def : Pat<(v4i16 (bitconvert (i64 (vector_extract (v2i64 VR128:$src),
1787 (v4i16 (MMX_MOVDQ2Qrr VR128:$src))>;
1788 def : Pat<(v8i8 (bitconvert (i64 (vector_extract (v2i64 VR128:$src),
1790 (v8i8 (MMX_MOVDQ2Qrr VR128:$src))>;
1792 There are other cases in various td files.