1 //===---------------------------------------------------------------------===//
2 // Random ideas for the X86 backend.
3 //===---------------------------------------------------------------------===//
6 - Support for SSE4: http://www.intel.com/software/penryn
7 http://softwarecommunity.intel.com/isn/Downloads/Intel%20SSE4%20Programming%20Reference.pdf
11 //===---------------------------------------------------------------------===//
13 CodeGen/X86/lea-3.ll:test3 should be a single LEA, not a shift/move. The X86
14 backend knows how to three-addressify this shift, but it appears the register
15 allocator isn't even asking it to do so in this case. We should investigate
16 why this isn't happening, it could have significant impact on other important
17 cases for X86 as well.
19 //===---------------------------------------------------------------------===//
21 This should be one DIV/IDIV instruction, not a libcall:
23 unsigned test(unsigned long long X, unsigned Y) {
27 This can be done trivially with a custom legalizer. What about overflow
28 though? http://gcc.gnu.org/bugzilla/show_bug.cgi?id=14224
30 //===---------------------------------------------------------------------===//
32 Improvements to the multiply -> shift/add algorithm:
33 http://gcc.gnu.org/ml/gcc-patches/2004-08/msg01590.html
35 //===---------------------------------------------------------------------===//
37 Improve code like this (occurs fairly frequently, e.g. in LLVM):
38 long long foo(int x) { return 1LL << x; }
40 http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01109.html
41 http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01128.html
42 http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01136.html
44 Another useful one would be ~0ULL >> X and ~0ULL << X.
46 One better solution for 1LL << x is:
55 But that requires good 8-bit subreg support.
57 Also, this might be better. It's an extra shift, but it's one instruction
58 shorter, and doesn't stress 8-bit subreg support.
59 (From http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01148.html,
60 but without the unnecessary and.)
68 64-bit shifts (in general) expand to really bad code. Instead of using
69 cmovs, we should expand to a conditional branch like GCC produces.
71 //===---------------------------------------------------------------------===//
74 _Bool f(_Bool a) { return a!=1; }
81 (Although note that this isn't a legal way to express the code that llvm-gcc
82 currently generates for that function.)
84 //===---------------------------------------------------------------------===//
88 1. Dynamic programming based approach when compile time if not an
90 2. Code duplication (addressing mode) during isel.
91 3. Other ideas from "Register-Sensitive Selection, Duplication, and
92 Sequencing of Instructions".
93 4. Scheduling for reduced register pressure. E.g. "Minimum Register
94 Instruction Sequence Problem: Revisiting Optimal Code Generation for DAGs"
95 and other related papers.
96 http://citeseer.ist.psu.edu/govindarajan01minimum.html
98 //===---------------------------------------------------------------------===//
100 Should we promote i16 to i32 to avoid partial register update stalls?
102 //===---------------------------------------------------------------------===//
104 Leave any_extend as pseudo instruction and hint to register
105 allocator. Delay codegen until post register allocation.
106 Note. any_extend is now turned into an INSERT_SUBREG. We still need to teach
107 the coalescer how to deal with it though.
109 //===---------------------------------------------------------------------===//
111 It appears icc use push for parameter passing. Need to investigate.
113 //===---------------------------------------------------------------------===//
115 Only use inc/neg/not instructions on processors where they are faster than
116 add/sub/xor. They are slower on the P4 due to only updating some processor
119 //===---------------------------------------------------------------------===//
121 The instruction selector sometimes misses folding a load into a compare. The
122 pattern is written as (cmp reg, (load p)). Because the compare isn't
123 commutative, it is not matched with the load on both sides. The dag combiner
124 should be made smart enough to cannonicalize the load into the RHS of a compare
125 when it can invert the result of the compare for free.
127 //===---------------------------------------------------------------------===//
129 How about intrinsics? An example is:
130 *res = _mm_mulhi_epu16(*A, _mm_mul_epu32(*B, *C));
133 pmuludq (%eax), %xmm0
138 The transformation probably requires a X86 specific pass or a DAG combiner
139 target specific hook.
141 //===---------------------------------------------------------------------===//
143 In many cases, LLVM generates code like this:
152 on some processors (which ones?), it is more efficient to do this:
161 Doing this correctly is tricky though, as the xor clobbers the flags.
163 //===---------------------------------------------------------------------===//
165 We should generate bts/btr/etc instructions on targets where they are cheap or
166 when codesize is important. e.g., for:
168 void setbit(int *target, int bit) {
169 *target |= (1 << bit);
171 void clearbit(int *target, int bit) {
172 *target &= ~(1 << bit);
175 //===---------------------------------------------------------------------===//
177 Instead of the following for memset char*, 1, 10:
179 movl $16843009, 4(%edx)
180 movl $16843009, (%edx)
183 It might be better to generate
190 when we can spare a register. It reduces code size.
192 //===---------------------------------------------------------------------===//
194 Evaluate what the best way to codegen sdiv X, (2^C) is. For X/8, we currently
211 GCC knows several different ways to codegen it, one of which is this:
221 which is probably slower, but it's interesting at least :)
223 //===---------------------------------------------------------------------===//
225 We are currently lowering large (1MB+) memmove/memcpy to rep/stosl and rep/movsl
226 We should leave these as libcalls for everything over a much lower threshold,
227 since libc is hand tuned for medium and large mem ops (avoiding RFO for large
228 stores, TLB preheating, etc)
230 //===---------------------------------------------------------------------===//
232 Optimize this into something reasonable:
233 x * copysign(1.0, y) * copysign(1.0, z)
235 //===---------------------------------------------------------------------===//
237 Optimize copysign(x, *y) to use an integer load from y.
239 //===---------------------------------------------------------------------===//
241 %X = weak global int 0
244 %N = cast int %N to uint
245 %tmp.24 = setgt int %N, 0
246 br bool %tmp.24, label %no_exit, label %return
249 %indvar = phi uint [ 0, %entry ], [ %indvar.next, %no_exit ]
250 %i.0.0 = cast uint %indvar to int
251 volatile store int %i.0.0, int* %X
252 %indvar.next = add uint %indvar, 1
253 %exitcond = seteq uint %indvar.next, %N
254 br bool %exitcond, label %return, label %no_exit
268 jl LBB_foo_4 # return
269 LBB_foo_1: # no_exit.preheader
272 movl L_X$non_lazy_ptr, %edx
276 jne LBB_foo_2 # no_exit
277 LBB_foo_3: # return.loopexit
281 We should hoist "movl L_X$non_lazy_ptr, %edx" out of the loop after
282 remateralization is implemented. This can be accomplished with 1) a target
283 dependent LICM pass or 2) makeing SelectDAG represent the whole function.
285 //===---------------------------------------------------------------------===//
287 The following tests perform worse with LSR:
289 lambda, siod, optimizer-eval, ackermann, hash2, nestedloop, strcat, and Treesor.
291 //===---------------------------------------------------------------------===//
293 We are generating far worse code than gcc:
299 for (i = 0; i < N; i++) { X = i; Y = i*4; }
302 LBB1_1: # entry.bb_crit_edge
306 movl L_X$non_lazy_ptr, %esi
308 movl L_Y$non_lazy_ptr, %esi
318 movl L_X$non_lazy_ptr-"L00000000001$pb"(%ebx), %esi
319 movl L_Y$non_lazy_ptr-"L00000000001$pb"(%ebx), %ecx
322 leal 0(,%edx,4), %eax
328 This is due to the lack of post regalloc LICM.
330 //===---------------------------------------------------------------------===//
332 Teach the coalescer to coalesce vregs of different register classes. e.g. FR32 /
335 //===---------------------------------------------------------------------===//
343 Obviously it would have been better for the first mov (or any op) to store
344 directly %esp[0] if there are no other uses.
346 //===---------------------------------------------------------------------===//
348 Adding to the list of cmp / test poor codegen issues:
350 int test(__m128 *A, __m128 *B) {
351 if (_mm_comige_ss(*A, *B))
371 Note the setae, movzbl, cmpl, cmove can be replaced with a single cmovae. There
372 are a number of issues. 1) We are introducing a setcc between the result of the
373 intrisic call and select. 2) The intrinsic is expected to produce a i32 value
374 so a any extend (which becomes a zero extend) is added.
376 We probably need some kind of target DAG combine hook to fix this.
378 //===---------------------------------------------------------------------===//
380 We generate significantly worse code for this than GCC:
381 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=21150
382 http://gcc.gnu.org/bugzilla/attachment.cgi?id=8701
384 There is also one case we do worse on PPC.
386 //===---------------------------------------------------------------------===//
388 If shorter, we should use things like:
393 The former can also be used when the two-addressy nature of the 'and' would
394 require a copy to be inserted (in X86InstrInfo::convertToThreeAddress).
396 //===---------------------------------------------------------------------===//
398 Another instruction selector deficiency:
401 %tmp = load int (int)** %foo
402 %tmp = tail call int %tmp( int 3 )
408 movl L_foo$non_lazy_ptr, %eax
414 The current isel scheme will not allow the load to be folded in the call since
415 the load's chain result is read by the callseq_start.
417 //===---------------------------------------------------------------------===//
427 imull $3, 4(%esp), %eax
429 Perhaps this is what we really should generate is? Is imull three or four
430 cycles? Note: ICC generates this:
432 leal (%eax,%eax,2), %eax
434 The current instruction priority is based on pattern complexity. The former is
435 more "complex" because it folds a load so the latter will not be emitted.
437 Perhaps we should use AddedComplexity to give LEA32r a higher priority? We
438 should always try to match LEA first since the LEA matching code does some
439 estimate to determine whether the match is profitable.
441 However, if we care more about code size, then imull is better. It's two bytes
442 shorter than movl + leal.
444 //===---------------------------------------------------------------------===//
446 __builtin_ffs codegen is messy.
448 int ffs_(unsigned X) { return __builtin_ffs(X); }
471 Another example of __builtin_ffs (use predsimplify to eliminate a select):
473 int foo (unsigned long j) {
475 return __builtin_ffs (j) - 1;
480 //===---------------------------------------------------------------------===//
482 It appears gcc place string data with linkonce linkage in
483 .section __TEXT,__const_coal,coalesced instead of
484 .section __DATA,__const_coal,coalesced.
485 Take a look at darwin.h, there are other Darwin assembler directives that we
488 //===---------------------------------------------------------------------===//
490 define i32 @foo(i32* %a, i32 %t) {
494 cond_true: ; preds = %cond_true, %entry
495 %x.0.0 = phi i32 [ 0, %entry ], [ %tmp9, %cond_true ] ; <i32> [#uses=3]
496 %t_addr.0.0 = phi i32 [ %t, %entry ], [ %tmp7, %cond_true ] ; <i32> [#uses=1]
497 %tmp2 = getelementptr i32* %a, i32 %x.0.0 ; <i32*> [#uses=1]
498 %tmp3 = load i32* %tmp2 ; <i32> [#uses=1]
499 %tmp5 = add i32 %t_addr.0.0, %x.0.0 ; <i32> [#uses=1]
500 %tmp7 = add i32 %tmp5, %tmp3 ; <i32> [#uses=2]
501 %tmp9 = add i32 %x.0.0, 1 ; <i32> [#uses=2]
502 %tmp = icmp sgt i32 %tmp9, 39 ; <i1> [#uses=1]
503 br i1 %tmp, label %bb12, label %cond_true
505 bb12: ; preds = %cond_true
508 is pessimized by -loop-reduce and -indvars
510 //===---------------------------------------------------------------------===//
512 u32 to float conversion improvement:
514 float uint32_2_float( unsigned u ) {
515 float fl = (int) (u & 0xffff);
516 float fh = (int) (u >> 16);
521 00000000 subl $0x04,%esp
522 00000003 movl 0x08(%esp,1),%eax
523 00000007 movl %eax,%ecx
524 00000009 shrl $0x10,%ecx
525 0000000c cvtsi2ss %ecx,%xmm0
526 00000010 andl $0x0000ffff,%eax
527 00000015 cvtsi2ss %eax,%xmm1
528 00000019 mulss 0x00000078,%xmm0
529 00000021 addss %xmm1,%xmm0
530 00000025 movss %xmm0,(%esp,1)
531 0000002a flds (%esp,1)
532 0000002d addl $0x04,%esp
535 //===---------------------------------------------------------------------===//
537 When using fastcc abi, align stack slot of argument of type double on 8 byte
538 boundary to improve performance.
540 //===---------------------------------------------------------------------===//
544 int f(int a, int b) {
545 if (a == 4 || a == 6)
557 //===---------------------------------------------------------------------===//
559 GCC's ix86_expand_int_movcc function (in i386.c) has a ton of interesting
560 simplifications for integer "x cmp y ? a : b". For example, instead of:
563 void f(int X, int Y) {
590 int usesbb(unsigned int a, unsigned int b) {
591 return (a < b ? -1 : 0);
605 movl $4294967295, %ecx
609 //===---------------------------------------------------------------------===//
611 Currently we don't have elimination of redundant stack manipulations. Consider
616 call fastcc void %test1( )
617 call fastcc void %test2( sbyte* cast (void ()* %test1 to sbyte*) )
621 declare fastcc void %test1()
623 declare fastcc void %test2(sbyte*)
626 This currently compiles to:
636 The add\sub pair is really unneeded here.
638 //===---------------------------------------------------------------------===//
640 Consider the expansion of:
642 define i32 @test3(i32 %X) {
643 %tmp1 = urem i32 %X, 255
647 Currently it compiles to:
650 movl $2155905153, %ecx
656 This could be "reassociated" into:
658 movl $2155905153, %eax
662 to avoid the copy. In fact, the existing two-address stuff would do this
663 except that mul isn't a commutative 2-addr instruction. I guess this has
664 to be done at isel time based on the #uses to mul?
666 //===---------------------------------------------------------------------===//
668 Make sure the instruction which starts a loop does not cross a cacheline
669 boundary. This requires knowning the exact length of each machine instruction.
670 That is somewhat complicated, but doable. Example 256.bzip2:
672 In the new trace, the hot loop has an instruction which crosses a cacheline
673 boundary. In addition to potential cache misses, this can't help decoding as I
674 imagine there has to be some kind of complicated decoder reset and realignment
675 to grab the bytes from the next cacheline.
677 532 532 0x3cfc movb (1809(%esp, %esi), %bl <<<--- spans 2 64 byte lines
678 942 942 0x3d03 movl %dh, (1809(%esp, %esi)
679 937 937 0x3d0a incl %esi
680 3 3 0x3d0b cmpb %bl, %dl
681 27 27 0x3d0d jnz 0x000062db <main+11707>
683 //===---------------------------------------------------------------------===//
685 In c99 mode, the preprocessor doesn't like assembly comments like #TRUNCATE.
687 //===---------------------------------------------------------------------===//
689 This could be a single 16-bit load.
692 if ((p[0] == 1) & (p[1] == 2)) return 1;
696 //===---------------------------------------------------------------------===//
698 We should inline lrintf and probably other libc functions.
700 //===---------------------------------------------------------------------===//
702 Start using the flags more. For example, compile:
704 int add_zf(int *x, int y, int a, int b) {
728 int add_zf(int *x, int y, int a, int b) {
752 //===---------------------------------------------------------------------===//
754 These two functions have identical effects:
756 unsigned int f(unsigned int i, unsigned int n) {++i; if (i == n) ++i; return i;}
757 unsigned int f2(unsigned int i, unsigned int n) {++i; i += i == n; return i;}
759 We currently compile them to:
767 jne LBB1_2 #UnifiedReturnBlock
771 LBB1_2: #UnifiedReturnBlock
781 leal 1(%ecx,%eax), %eax
784 both of which are inferior to GCC's:
802 //===---------------------------------------------------------------------===//
810 is currently compiled to:
821 It would be better to produce:
830 This can be applied to any no-return function call that takes no arguments etc.
831 Alternatively, the stack save/restore logic could be shrink-wrapped, producing
842 Both are useful in different situations. Finally, it could be shrink-wrapped
843 and tail called, like this:
850 pop %eax # realign stack.
853 Though this probably isn't worth it.
855 //===---------------------------------------------------------------------===//
857 We need to teach the codegen to convert two-address INC instructions to LEA
858 when the flags are dead (likewise dec). For example, on X86-64, compile:
860 int foo(int A, int B) {
879 ;; X's live range extends beyond the shift, so the register allocator
880 ;; cannot coalesce it with Y. Because of this, a copy needs to be
881 ;; emitted before the shift to save the register value before it is
882 ;; clobbered. However, this copy is not needed if the register
883 ;; allocator turns the shift into an LEA. This also occurs for ADD.
885 ; Check that the shift gets turned into an LEA.
886 ; RUN: llvm-as < %s | llc -march=x86 -x86-asm-syntax=intel | \
887 ; RUN: not grep {mov E.X, E.X}
889 @G = external global i32 ; <i32*> [#uses=3]
891 define i32 @test1(i32 %X, i32 %Y) {
892 %Z = add i32 %X, %Y ; <i32> [#uses=1]
893 volatile store i32 %Y, i32* @G
894 volatile store i32 %Z, i32* @G
898 define i32 @test2(i32 %X) {
899 %Z = add i32 %X, 1 ; <i32> [#uses=1]
900 volatile store i32 %Z, i32* @G
904 //===---------------------------------------------------------------------===//
906 Sometimes it is better to codegen subtractions from a constant (e.g. 7-x) with
907 a neg instead of a sub instruction. Consider:
909 int test(char X) { return 7-X; }
911 we currently produce:
918 We would use one fewer register if codegen'd as:
925 Note that this isn't beneficial if the load can be folded into the sub. In
926 this case, we want a sub:
928 int test(int X) { return 7-X; }
934 //===---------------------------------------------------------------------===//
936 This is a "commutable two-address" register coallescing deficiency:
938 define <4 x float> @test1(<4 x float> %V) {
940 %tmp8 = shufflevector <4 x float> %V, <4 x float> undef,
941 <4 x i32> < i32 3, i32 2, i32 1, i32 0 >
942 %add = add <4 x float> %tmp8, %V
949 pshufd $27, %xmm0, %xmm1
957 pshufd $27, %xmm0, %xmm1
961 //===---------------------------------------------------------------------===//
963 Leaf functions that require one 4-byte spill slot have a prolog like this:
969 and an epilog like this:
974 It would be smaller, and potentially faster, to push eax on entry and to
975 pop into a dummy register instead of using addl/subl of esp. Just don't pop
976 into any return registers :)
978 //===---------------------------------------------------------------------===//
980 The X86 backend should fold (branch (or (setcc, setcc))) into multiple
981 branches. We generate really poor code for:
983 double testf(double a) {
984 return a == 0.0 ? 0.0 : (a > 0.0 ? 1.0 : -1.0);
987 For example, the entry BB is:
992 movsd 24(%esp), %xmm1
997 jne LBB1_5 # UnifiedReturnBlock
1001 it would be better to replace the last four instructions with:
1007 We also codegen the inner ?: into a diamond:
1009 cvtss2sd LCPI1_0(%rip), %xmm2
1010 cvtss2sd LCPI1_1(%rip), %xmm3
1011 ucomisd %xmm1, %xmm0
1012 ja LBB1_3 # cond_true
1019 We should sink the load into xmm3 into the LBB1_2 block. This should
1020 be pretty easy, and will nuke all the copies.
1022 //===---------------------------------------------------------------------===//
1025 #include <algorithm>
1026 inline std::pair<unsigned, bool> full_add(unsigned a, unsigned b)
1027 { return std::make_pair(a + b, a + b < a); }
1028 bool no_overflow(unsigned a, unsigned b)
1029 { return !full_add(a, b).second; }
1039 FIXME: That code looks wrong; bool return is normally defined as zext.
1051 //===---------------------------------------------------------------------===//
1053 Re-materialize MOV32r0 etc. with xor instead of changing them to moves if the
1054 condition register is dead. xor reg reg is shorter than mov reg, #0.
1056 //===---------------------------------------------------------------------===//
1058 We aren't matching RMW instructions aggressively
1059 enough. Here's a reduced testcase (more in PR1160):
1061 define void @test(i32* %huge_ptr, i32* %target_ptr) {
1062 %A = load i32* %huge_ptr ; <i32> [#uses=1]
1063 %B = load i32* %target_ptr ; <i32> [#uses=1]
1064 %C = or i32 %A, %B ; <i32> [#uses=1]
1065 store i32 %C, i32* %target_ptr
1069 $ llvm-as < t.ll | llc -march=x86-64
1077 That should be something like:
1084 //===---------------------------------------------------------------------===//
1088 bb114.preheader: ; preds = %cond_next94
1089 %tmp231232 = sext i16 %tmp62 to i32 ; <i32> [#uses=1]
1090 %tmp233 = sub i32 32, %tmp231232 ; <i32> [#uses=1]
1091 %tmp245246 = sext i16 %tmp65 to i32 ; <i32> [#uses=1]
1092 %tmp252253 = sext i16 %tmp68 to i32 ; <i32> [#uses=1]
1093 %tmp254 = sub i32 32, %tmp252253 ; <i32> [#uses=1]
1094 %tmp553554 = bitcast i16* %tmp37 to i8* ; <i8*> [#uses=2]
1095 %tmp583584 = sext i16 %tmp98 to i32 ; <i32> [#uses=1]
1096 %tmp585 = sub i32 32, %tmp583584 ; <i32> [#uses=1]
1097 %tmp614615 = sext i16 %tmp101 to i32 ; <i32> [#uses=1]
1098 %tmp621622 = sext i16 %tmp104 to i32 ; <i32> [#uses=1]
1099 %tmp623 = sub i32 32, %tmp621622 ; <i32> [#uses=1]
1104 LBB3_5: # bb114.preheader
1105 movswl -68(%ebp), %eax
1107 movl %ecx, -80(%ebp)
1108 subl %eax, -80(%ebp)
1109 movswl -52(%ebp), %eax
1110 movl %ecx, -84(%ebp)
1111 subl %eax, -84(%ebp)
1112 movswl -70(%ebp), %eax
1113 movl %ecx, -88(%ebp)
1114 subl %eax, -88(%ebp)
1115 movswl -50(%ebp), %eax
1117 movl %ecx, -76(%ebp)
1118 movswl -42(%ebp), %eax
1119 movl %eax, -92(%ebp)
1120 movswl -66(%ebp), %eax
1121 movl %eax, -96(%ebp)
1124 This appears to be bad because the RA is not folding the store to the stack
1125 slot into the movl. The above instructions could be:
1130 This seems like a cross between remat and spill folding.
1132 This has redundant subtractions of %eax from a stack slot. However, %ecx doesn't
1133 change, so we could simply subtract %eax from %ecx first and then use %ecx (or
1136 //===---------------------------------------------------------------------===//
1140 cond_next603: ; preds = %bb493, %cond_true336, %cond_next599
1141 %v.21050.1 = phi i32 [ %v.21050.0, %cond_next599 ], [ %tmp344, %cond_true336 ], [ %v.2, %bb493 ] ; <i32> [#uses=1]
1142 %maxz.21051.1 = phi i32 [ %maxz.21051.0, %cond_next599 ], [ 0, %cond_true336 ], [ %maxz.2, %bb493 ] ; <i32> [#uses=2]
1143 %cnt.01055.1 = phi i32 [ %cnt.01055.0, %cond_next599 ], [ 0, %cond_true336 ], [ %cnt.0, %bb493 ] ; <i32> [#uses=2]
1144 %byteptr.9 = phi i8* [ %byteptr.12, %cond_next599 ], [ %byteptr.0, %cond_true336 ], [ %byteptr.10, %bb493 ] ; <i8*> [#uses=9]
1145 %bitptr.6 = phi i32 [ %tmp5571104.1, %cond_next599 ], [ %tmp4921049, %cond_true336 ], [ %bitptr.7, %bb493 ] ; <i32> [#uses=4]
1146 %source.5 = phi i32 [ %tmp602, %cond_next599 ], [ %source.0, %cond_true336 ], [ %source.6, %bb493 ] ; <i32> [#uses=7]
1147 %tmp606 = getelementptr %struct.const_tables* @tables, i32 0, i32 0, i32 %cnt.01055.1 ; <i8*> [#uses=1]
1148 %tmp607 = load i8* %tmp606, align 1 ; <i8> [#uses=1]
1152 LBB4_70: # cond_next603
1153 movl -20(%ebp), %esi
1154 movl L_tables$non_lazy_ptr-"L4$pb"(%esi), %esi
1156 However, ICC caches this information before the loop and produces this:
1158 movl 88(%esp), %eax #481.12
1160 //===---------------------------------------------------------------------===//
1164 %tmp659 = icmp slt i16 %tmp654, 0 ; <i1> [#uses=1]
1165 br i1 %tmp659, label %cond_true662, label %cond_next715
1171 jns LBB4_109 # cond_next715
1173 Shark tells us that using %cx in the testw instruction is sub-optimal. It
1174 suggests using the 32-bit register (which is what ICC uses).
1176 //===---------------------------------------------------------------------===//
1180 void compare (long long foo) {
1181 if (foo < 4294967297LL)
1197 jne .LBB1_2 # UnifiedReturnBlock
1200 .LBB1_2: # UnifiedReturnBlock
1204 (also really horrible code on ppc). This is due to the expand code for 64-bit
1205 compares. GCC produces multiple branches, which is much nicer:
1226 //===---------------------------------------------------------------------===//
1228 Tail call optimization improvements: Tail call optimization currently
1229 pushes all arguments on the top of the stack (their normal place for
1230 non-tail call optimized calls) that source from the callers arguments
1231 or that source from a virtual register (also possibly sourcing from
1233 This is done to prevent overwriting of parameters (see example
1234 below) that might be used later.
1238 int callee(int32, int64);
1239 int caller(int32 arg1, int32 arg2) {
1240 int64 local = arg2 * 2;
1241 return callee(arg2, (int64)local);
1244 [arg1] [!arg2 no longer valid since we moved local onto it]
1248 Moving arg1 onto the stack slot of callee function would overwrite
1251 Possible optimizations:
1254 - Analyse the actual parameters of the callee to see which would
1255 overwrite a caller parameter which is used by the callee and only
1256 push them onto the top of the stack.
1258 int callee (int32 arg1, int32 arg2);
1259 int caller (int32 arg1, int32 arg2) {
1260 return callee(arg1,arg2);
1263 Here we don't need to write any variables to the top of the stack
1264 since they don't overwrite each other.
1266 int callee (int32 arg1, int32 arg2);
1267 int caller (int32 arg1, int32 arg2) {
1268 return callee(arg2,arg1);
1271 Here we need to push the arguments because they overwrite each
1274 //===---------------------------------------------------------------------===//
1279 unsigned long int z = 0;
1290 gcc compiles this to:
1316 jge LBB1_4 # cond_true
1319 addl $4294950912, %ecx
1329 1. LSR should rewrite the first cmp with induction variable %ecx.
1330 2. DAG combiner should fold
1336 //===---------------------------------------------------------------------===//
1338 define i64 @test(double %X) {
1339 %Y = fptosi double %X to i64
1347 movsd 24(%esp), %xmm0
1348 movsd %xmm0, 8(%esp)
1357 This should just fldl directly from the input stack slot.
1359 //===---------------------------------------------------------------------===//
1362 int foo (int x) { return (x & 65535) | 255; }
1364 Should compile into:
1367 movzwl 4(%esp), %eax
1378 //===---------------------------------------------------------------------===//
1380 We're codegen'ing multiply of long longs inefficiently:
1382 unsigned long long LLM(unsigned long long arg1, unsigned long long arg2) {
1386 We compile to (fomit-frame-pointer):
1394 imull 12(%esp), %esi
1396 imull 20(%esp), %ecx
1402 This looks like a scheduling deficiency and lack of remat of the load from
1403 the argument area. ICC apparently produces:
1406 imull 12(%esp), %ecx
1415 Note that it remat'd loads from 4(esp) and 12(esp). See this GCC PR:
1416 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=17236
1418 //===---------------------------------------------------------------------===//
1420 We can fold a store into "zeroing a reg". Instead of:
1423 movl %eax, 124(%esp)
1429 if the flags of the xor are dead.
1431 Likewise, we isel "x<<1" into "add reg,reg". If reg is spilled, this should
1432 be folded into: shl [mem], 1
1434 //===---------------------------------------------------------------------===//
1436 This testcase misses a read/modify/write opportunity (from PR1425):
1438 void vertical_decompose97iH1(int *b0, int *b1, int *b2, int width){
1440 for(i=0; i<width; i++)
1441 b1[i] += (1*(b0[i] + b2[i])+0)>>0;
1444 We compile it down to:
1447 movl (%esi,%edi,4), %ebx
1448 addl (%ecx,%edi,4), %ebx
1449 addl (%edx,%edi,4), %ebx
1450 movl %ebx, (%ecx,%edi,4)
1455 the inner loop should add to the memory location (%ecx,%edi,4), saving
1456 a mov. Something like:
1458 movl (%esi,%edi,4), %ebx
1459 addl (%edx,%edi,4), %ebx
1460 addl %ebx, (%ecx,%edi,4)
1462 Here is another interesting example:
1464 void vertical_compose97iH1(int *b0, int *b1, int *b2, int width){
1466 for(i=0; i<width; i++)
1467 b1[i] -= (1*(b0[i] + b2[i])+0)>>0;
1470 We miss the r/m/w opportunity here by using 2 subs instead of an add+sub[mem]:
1473 movl (%ecx,%edi,4), %ebx
1474 subl (%esi,%edi,4), %ebx
1475 subl (%edx,%edi,4), %ebx
1476 movl %ebx, (%ecx,%edi,4)
1481 Additionally, LSR should rewrite the exit condition of these loops to use
1482 a stride-4 IV, would would allow all the scales in the loop to go away.
1483 This would result in smaller code and more efficient microops.
1485 //===---------------------------------------------------------------------===//
1487 In SSE mode, we turn abs and neg into a load from the constant pool plus a xor
1488 or and instruction, for example:
1490 xorpd LCPI1_0, %xmm2
1492 However, if xmm2 gets spilled, we end up with really ugly code like this:
1495 xorpd LCPI1_0, %xmm0
1498 Since we 'know' that this is a 'neg', we can actually "fold" the spill into
1499 the neg/abs instruction, turning it into an *integer* operation, like this:
1501 xorl 2147483648, [mem+4] ## 2147483648 = (1 << 31)
1503 you could also use xorb, but xorl is less likely to lead to a partial register
1504 stall. Here is a contrived testcase:
1507 void test(double *P) {
1517 //===---------------------------------------------------------------------===//
1519 handling llvm.memory.barrier on pre SSE2 cpus
1522 lock ; mov %esp, %esp
1524 //===---------------------------------------------------------------------===//
1526 The generated code on x86 for checking for signed overflow on a multiply the
1527 obvious way is much longer than it needs to be.
1529 int x(int a, int b) {
1530 long long prod = (long long)a*b;
1531 return prod > 0x7FFFFFFF || prod < (-0x7FFFFFFF-1);
1534 See PR2053 for more details.
1536 //===---------------------------------------------------------------------===//
1538 We should investigate using cdq/ctld (effect: edx = sar eax, 31)
1539 more aggressively; it should cost the same as a move+shift on any modern
1540 processor, but it's a lot shorter. Downside is that it puts more
1541 pressure on register allocation because it has fixed operands.
1544 int abs(int x) {return x < 0 ? -x : x;}
1546 gcc compiles this to the following when using march/mtune=pentium2/3/4/m/etc.:
1554 //===---------------------------------------------------------------------===//
1557 int test(unsigned long a, unsigned long b) { return -(a < b); }
1559 We currently compile this to:
1561 define i32 @test(i32 %a, i32 %b) nounwind {
1562 %tmp3 = icmp ult i32 %a, %b ; <i1> [#uses=1]
1563 %tmp34 = zext i1 %tmp3 to i32 ; <i32> [#uses=1]
1564 %tmp5 = sub i32 0, %tmp34 ; <i32> [#uses=1]
1578 Several deficiencies here. First, we should instcombine zext+neg into sext:
1580 define i32 @test2(i32 %a, i32 %b) nounwind {
1581 %tmp3 = icmp ult i32 %a, %b ; <i1> [#uses=1]
1582 %tmp34 = sext i1 %tmp3 to i32 ; <i32> [#uses=1]
1586 However, before we can do that, we have to fix the bad codegen that we get for
1598 This code should be at least as good as the code above. Once this is fixed, we
1599 can optimize this specific case even more to:
1606 //===---------------------------------------------------------------------===//