1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is a target description file for the Intel i386 architecture, referred
11 // to here as the "X86" architecture.
13 //===----------------------------------------------------------------------===//
15 // Get the target-independent interfaces which we are implementing...
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // X86 Subtarget state
23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
24 "64-bit mode (x86_64)">;
26 //===----------------------------------------------------------------------===//
27 // X86 Subtarget features
28 //===----------------------------------------------------------------------===//
30 def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true",
31 "Enable conditional move instructions">;
33 def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
34 "Support POPCNT instruction">;
37 def FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX",
38 "Enable MMX instructions">;
39 def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
40 "Enable SSE instructions",
41 // SSE codegen depends on cmovs, and all
42 // SSE1+ processors support them.
43 [FeatureMMX, FeatureCMOV]>;
44 def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
45 "Enable SSE2 instructions",
47 def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
48 "Enable SSE3 instructions",
50 def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
51 "Enable SSSE3 instructions",
53 def FeatureSSE41 : SubtargetFeature<"sse41", "X86SSELevel", "SSE41",
54 "Enable SSE 4.1 instructions",
56 def FeatureSSE42 : SubtargetFeature<"sse42", "X86SSELevel", "SSE42",
57 "Enable SSE 4.2 instructions",
59 def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
60 "Enable 3DNow! instructions",
62 def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
63 "Enable 3DNow! Athlon instructions",
65 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
66 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
67 // without disabling 64-bit mode.
68 def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true",
69 "Support 64-bit instructions",
71 def FeatureCMPXCHG16B : SubtargetFeature<"cmpxchg16b", "HasCmpxchg16b", "true",
72 "64-bit with cmpxchg16b",
74 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
75 "Bit testing of memory is slow">;
76 def FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem",
77 "IsUAMemFast", "true",
78 "Fast unaligned memory access">;
79 def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true",
80 "Support SSE 4a instructions",
83 def FeatureAVX : SubtargetFeature<"avx", "X86SSELevel", "AVX",
84 "Enable AVX instructions",
86 def FeatureAVX2 : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
87 "Enable AVX2 instructions",
89 def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
90 "Enable packed carry-less multiplication instructions",
92 def FeatureFMA : SubtargetFeature<"fma", "HasFMA", "true",
93 "Enable three-operand fused multiple-add",
95 def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true",
96 "Enable four-operand fused multiple-add",
97 [FeatureAVX, FeatureSSE4A]>;
98 def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true",
99 "Enable XOP instructions",
101 def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
102 "HasVectorUAMem", "true",
103 "Allow unaligned memory operands on vector/SIMD instructions">;
104 def FeatureAES : SubtargetFeature<"aes", "HasAES", "true",
105 "Enable AES instructions",
107 def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true",
108 "Support MOVBE instruction">;
109 def FeatureRDRAND : SubtargetFeature<"rdrand", "HasRDRAND", "true",
110 "Support RDRAND instruction">;
111 def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true",
112 "Support 16-bit floating point conversion instructions">;
113 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
114 "Support FS/GS Base instructions">;
115 def FeatureLZCNT : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
116 "Support LZCNT instruction">;
117 def FeatureBMI : SubtargetFeature<"bmi", "HasBMI", "true",
118 "Support BMI instructions">;
119 def FeatureBMI2 : SubtargetFeature<"bmi2", "HasBMI2", "true",
120 "Support BMI2 instructions">;
121 def FeatureRTM : SubtargetFeature<"rtm", "HasRTM", "true",
122 "Support RTM instructions">;
123 def FeatureADX : SubtargetFeature<"adx", "HasADX", "true",
124 "Support ADX instructions">;
125 def FeatureLeaForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
126 "Use LEA for adjusting the stack pointer">;
127 def FeatureSlowDivide : SubtargetFeature<"idiv-to-divb",
128 "HasSlowDivide", "true",
129 "Use small divide for positive values less than 256">;
130 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
131 "PadShortFunctions", "true",
132 "Pad short functions">;
134 //===----------------------------------------------------------------------===//
135 // X86 processors supported.
136 //===----------------------------------------------------------------------===//
138 include "X86Schedule.td"
140 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
141 "Intel Atom processors">;
143 class Proc<string Name, list<SubtargetFeature> Features>
144 : ProcessorModel<Name, GenericModel, Features>;
146 class AtomProc<string Name, list<SubtargetFeature> Features>
147 : ProcessorModel<Name, AtomModel, Features>;
149 def : Proc<"generic", []>;
150 def : Proc<"i386", []>;
151 def : Proc<"i486", []>;
152 def : Proc<"i586", []>;
153 def : Proc<"pentium", []>;
154 def : Proc<"pentium-mmx", [FeatureMMX]>;
155 def : Proc<"i686", []>;
156 def : Proc<"pentiumpro", [FeatureCMOV]>;
157 def : Proc<"pentium2", [FeatureMMX, FeatureCMOV]>;
158 def : Proc<"pentium3", [FeatureSSE1]>;
159 def : Proc<"pentium3m", [FeatureSSE1, FeatureSlowBTMem]>;
160 def : Proc<"pentium-m", [FeatureSSE2, FeatureSlowBTMem]>;
161 def : Proc<"pentium4", [FeatureSSE2]>;
162 def : Proc<"pentium4m", [FeatureSSE2, FeatureSlowBTMem]>;
163 def : Proc<"x86-64", [FeatureSSE2, Feature64Bit, FeatureSlowBTMem,
165 def : Proc<"yonah", [FeatureSSE3, FeatureSlowBTMem]>;
166 def : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>;
167 def : Proc<"nocona", [FeatureSSE3, FeatureCMPXCHG16B,
169 def : Proc<"core2", [FeatureSSSE3, FeatureCMPXCHG16B,
171 def : Proc<"penryn", [FeatureSSE41, FeatureCMPXCHG16B,
173 def : AtomProc<"atom", [ProcIntelAtom, FeatureSSSE3, FeatureCMPXCHG16B,
174 FeatureMOVBE, FeatureSlowBTMem, FeatureLeaForSP,
175 FeatureSlowDivide, FeaturePadShortFunctions]>;
176 // "Arrandale" along with corei3 and corei5
177 def : Proc<"corei7", [FeatureSSE42, FeatureCMPXCHG16B,
178 FeatureSlowBTMem, FeatureFastUAMem,
179 FeaturePOPCNT, FeatureAES]>;
180 def : Proc<"nehalem", [FeatureSSE42, FeatureCMPXCHG16B,
181 FeatureSlowBTMem, FeatureFastUAMem,
183 // Westmere is a similar machine to nehalem with some additional features.
184 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
185 def : Proc<"westmere", [FeatureSSE42, FeatureCMPXCHG16B,
186 FeatureSlowBTMem, FeatureFastUAMem,
187 FeaturePOPCNT, FeatureAES, FeaturePCLMUL]>;
189 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
190 // rather than a superset.
191 def : Proc<"corei7-avx", [FeatureAVX, FeatureCMPXCHG16B, FeatureFastUAMem,
192 FeaturePOPCNT, FeatureAES, FeaturePCLMUL]>;
194 def : Proc<"core-avx-i", [FeatureAVX, FeatureCMPXCHG16B, FeatureFastUAMem,
195 FeaturePOPCNT, FeatureAES, FeaturePCLMUL,
196 FeatureRDRAND, FeatureF16C, FeatureFSGSBase]>;
199 def : Proc<"core-avx2", [FeatureAVX2, FeatureCMPXCHG16B, FeatureFastUAMem,
200 FeaturePOPCNT, FeatureAES, FeaturePCLMUL,
201 FeatureRDRAND, FeatureF16C, FeatureFSGSBase,
202 FeatureMOVBE, FeatureLZCNT, FeatureBMI,
203 FeatureBMI2, FeatureFMA,
206 def : Proc<"k6", [FeatureMMX]>;
207 def : Proc<"k6-2", [Feature3DNow]>;
208 def : Proc<"k6-3", [Feature3DNow]>;
209 def : Proc<"athlon", [Feature3DNowA, FeatureSlowBTMem]>;
210 def : Proc<"athlon-tbird", [Feature3DNowA, FeatureSlowBTMem]>;
211 def : Proc<"athlon-4", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
212 def : Proc<"athlon-xp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
213 def : Proc<"athlon-mp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
214 def : Proc<"k8", [FeatureSSE2, Feature3DNowA, Feature64Bit,
216 def : Proc<"opteron", [FeatureSSE2, Feature3DNowA, Feature64Bit,
218 def : Proc<"athlon64", [FeatureSSE2, Feature3DNowA, Feature64Bit,
220 def : Proc<"athlon-fx", [FeatureSSE2, Feature3DNowA, Feature64Bit,
222 def : Proc<"k8-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
224 def : Proc<"opteron-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
226 def : Proc<"athlon64-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
228 def : Proc<"amdfam10", [FeatureSSE4A,
229 Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
230 FeaturePOPCNT, FeatureSlowBTMem]>;
232 def : Proc<"btver1", [FeatureSSSE3, FeatureSSE4A, FeatureCMPXCHG16B,
233 FeatureLZCNT, FeaturePOPCNT]>;
235 def : Proc<"bdver1", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
236 FeatureAES, FeaturePCLMUL,
237 FeatureLZCNT, FeaturePOPCNT]>;
238 // Enhanced Bulldozer
239 def : Proc<"bdver2", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
240 FeatureAES, FeaturePCLMUL,
241 FeatureF16C, FeatureLZCNT,
242 FeaturePOPCNT, FeatureBMI, FeatureFMA]>;
243 def : Proc<"geode", [Feature3DNowA]>;
245 def : Proc<"winchip-c6", [FeatureMMX]>;
246 def : Proc<"winchip2", [Feature3DNow]>;
247 def : Proc<"c3", [Feature3DNow]>;
248 def : Proc<"c3-2", [FeatureSSE1]>;
250 //===----------------------------------------------------------------------===//
251 // Register File Description
252 //===----------------------------------------------------------------------===//
254 include "X86RegisterInfo.td"
256 //===----------------------------------------------------------------------===//
257 // Instruction Descriptions
258 //===----------------------------------------------------------------------===//
260 include "X86InstrInfo.td"
262 def X86InstrInfo : InstrInfo;
264 //===----------------------------------------------------------------------===//
265 // Calling Conventions
266 //===----------------------------------------------------------------------===//
268 include "X86CallingConv.td"
271 //===----------------------------------------------------------------------===//
273 //===----------------------------------------------------------------------===//
275 def ATTAsmParser : AsmParser {
276 string AsmParserClassName = "AsmParser";
279 def ATTAsmParserVariant : AsmParserVariant {
282 // Discard comments in assembly strings.
283 string CommentDelimiter = "#";
285 // Recognize hard coded registers.
286 string RegisterPrefix = "%";
289 def IntelAsmParserVariant : AsmParserVariant {
292 // Discard comments in assembly strings.
293 string CommentDelimiter = ";";
295 // Recognize hard coded registers.
296 string RegisterPrefix = "";
299 //===----------------------------------------------------------------------===//
301 //===----------------------------------------------------------------------===//
303 // The X86 target supports two different syntaxes for emitting machine code.
304 // This is controlled by the -x86-asm-syntax={att|intel}
305 def ATTAsmWriter : AsmWriter {
306 string AsmWriterClassName = "ATTInstPrinter";
308 bit isMCAsmWriter = 1;
310 def IntelAsmWriter : AsmWriter {
311 string AsmWriterClassName = "IntelInstPrinter";
313 bit isMCAsmWriter = 1;
317 // Information about the instructions...
318 let InstructionSet = X86InstrInfo;
319 let AssemblyParsers = [ATTAsmParser];
320 let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
321 let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];