lib/Target/X86/X86.td

   1 //===- X86.td - Target definition file for the Intel X86 ---*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is a target description file for the Intel i386 architecture, refered to
  11 // here as the "X86" architecture.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 // Get the target-independent interfaces which we are implementing...
  16 //
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // X86 Subtarget features.
  21 //===----------------------------------------------------------------------===//
  22
  23 def FeatureMMX     : SubtargetFeature<"mmx","X86SSELevel", "MMX",
  24                                       "Enable MMX instructions">;
  25 def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
  26                                       "Enable SSE instructions",
  27                                       [FeatureMMX]>;
  28 def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
  29                                       "Enable SSE2 instructions",
  30                                       [FeatureSSE1]>;
  31 def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
  32                                       "Enable SSE3 instructions",
  33                                       [FeatureSSE2]>;
  34 def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
  35                                       "Enable SSSE3 instructions",
  36                                       [FeatureSSE3]>;
  37 def FeatureSSE41   : SubtargetFeature<"sse41", "X86SSELevel", "SSE41",
  38                                       "Enable SSE 4.1 instructions",
  39                                       [FeatureSSSE3]>;
  40 def FeatureSSE42   : SubtargetFeature<"sse42", "X86SSELevel", "SSE42",
  41                                       "Enable SSE 4.2 instructions",
  42                                       [FeatureSSE41]>;
  43 def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
  44                                       "Enable 3DNow! instructions">;
  45 def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
  46                                       "Enable 3DNow! Athlon instructions",
  47                                       [Feature3DNow]>;
  48 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
  49 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
  50 // without disabling 64-bit mode.
  51 def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
  52                                       "Support 64-bit instructions">;
  53 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
  54                                        "Bit testing of memory is slow">;
  55
  56 //===----------------------------------------------------------------------===//
  57 // X86 processors supported.
  58 //===----------------------------------------------------------------------===//
  59
  60 class Proc<string Name, list<SubtargetFeature> Features>
  61  : Processor<Name, NoItineraries, Features>;
  62
  63 def : Proc<"generic",         []>;
  64 def : Proc<"i386",            []>;
  65 def : Proc<"i486",            []>;
  66 def : Proc<"i586",            []>;
  67 def : Proc<"pentium",         []>;
  68 def : Proc<"pentium-mmx",     [FeatureMMX]>;
  69 def : Proc<"i686",            []>;
  70 def : Proc<"pentiumpro",      []>;
  71 def : Proc<"pentium2",        [FeatureMMX]>;
  72 def : Proc<"pentium3",        [FeatureSSE1]>;
  73 def : Proc<"pentium-m",       [FeatureSSE2, FeatureSlowBTMem]>;
  74 def : Proc<"pentium4",        [FeatureSSE2]>;
  75 def : Proc<"x86-64",          [FeatureSSE2,   Feature64Bit, FeatureSlowBTMem]>;
  76 def : Proc<"yonah",           [FeatureSSE3, FeatureSlowBTMem]>;
  77 def : Proc<"prescott",        [FeatureSSE3, FeatureSlowBTMem]>;
  78 def : Proc<"nocona",          [FeatureSSE3,   Feature64Bit, FeatureSlowBTMem]>;
  79 def : Proc<"core2",           [FeatureSSSE3,  Feature64Bit, FeatureSlowBTMem]>;
  80 def : Proc<"penryn",          [FeatureSSE41,  Feature64Bit, FeatureSlowBTMem]>;
  81 def : Proc<"atom",            [FeatureSSE3,   Feature64Bit, FeatureSlowBTMem]>;
  82 def : Proc<"corei7",          [FeatureSSE42,  Feature64Bit, FeatureSlowBTMem]>;
  83
  84 def : Proc<"k6",              [FeatureMMX]>;
  85 def : Proc<"k6-2",            [FeatureMMX,    Feature3DNow]>;
  86 def : Proc<"k6-3",            [FeatureMMX,    Feature3DNow]>;
  87 def : Proc<"athlon",          [FeatureMMX,    Feature3DNowA, FeatureSlowBTMem]>;
  88 def : Proc<"athlon-tbird",    [FeatureMMX,    Feature3DNowA, FeatureSlowBTMem]>;
  89 def : Proc<"athlon-4",        [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem]>;
  90 def : Proc<"athlon-xp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem]>;
  91 def : Proc<"athlon-mp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem]>;
  92 def : Proc<"k8",              [FeatureSSE2,   Feature3DNowA, Feature64Bit,
  93                                FeatureSlowBTMem]>;
  94 def : Proc<"opteron",         [FeatureSSE2,   Feature3DNowA, Feature64Bit,
  95                                FeatureSlowBTMem]>;
  96 def : Proc<"athlon64",        [FeatureSSE2,   Feature3DNowA, Feature64Bit,
  97                                FeatureSlowBTMem]>;
  98 def : Proc<"athlon-fx",       [FeatureSSE2,   Feature3DNowA, Feature64Bit,
  99                                FeatureSlowBTMem]>;
 100
 101 def : Proc<"winchip-c6",      [FeatureMMX]>;
 102 def : Proc<"winchip2",        [FeatureMMX, Feature3DNow]>;
 103 def : Proc<"c3",              [FeatureMMX, Feature3DNow]>;
 104 def : Proc<"c3-2",            [FeatureSSE1]>;
 105
 106 //===----------------------------------------------------------------------===//
 107 // Register File Description
 108 //===----------------------------------------------------------------------===//
 109
 110 include "X86RegisterInfo.td"
 111
 112 //===----------------------------------------------------------------------===//
 113 // Instruction Descriptions
 114 //===----------------------------------------------------------------------===//
 115
 116 include "X86InstrInfo.td"
 117
 118 def X86InstrInfo : InstrInfo {
 119
 120   // Define how we want to layout our TargetSpecific information field... This
 121   // should be kept up-to-date with the fields in the X86InstrInfo.h file.
 122   let TSFlagsFields = ["FormBits",
 123                        "hasOpSizePrefix",
 124                        "hasAdSizePrefix",
 125                        "Prefix",
 126                        "hasREX_WPrefix",
 127                        "ImmTypeBits",
 128                        "FPFormBits",
 129                        "hasLockPrefix",
 130                        "SegOvrBits",
 131                        "Opcode"];
 132   let TSFlagsShifts = [0,
 133                        6,
 134                        7,
 135                        8,
 136                        12,
 137                        13,
 138                        16,
 139                        19,
 140                        20,
 141                        24];
 142 }
 143
 144 //===----------------------------------------------------------------------===//
 145 // Calling Conventions
 146 //===----------------------------------------------------------------------===//
 147
 148 include "X86CallingConv.td"
 149
 150
 151 //===----------------------------------------------------------------------===//
 152 // Assembly Printers
 153 //===----------------------------------------------------------------------===//
 154
 155 // The X86 target supports two different syntaxes for emitting machine code.
 156 // This is controlled by the -x86-asm-syntax={att|intel}
 157 def ATTAsmWriter : AsmWriter {
 158   string AsmWriterClassName  = "ATTAsmPrinter";
 159   int Variant = 0;
 160 }
 161 def IntelAsmWriter : AsmWriter {
 162   string AsmWriterClassName  = "IntelAsmPrinter";
 163   int Variant = 1;
 164 }
 165
 166
 167 def X86 : Target {
 168   // Information about the instructions...
 169   let InstructionSet = X86InstrInfo;
 170
 171   let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
 172 }