1 //===- X86.td - Target definition file for the Intel X86 ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is a target description file for the Intel i386 architecture, refered to
11 // here as the "X86" architecture.
13 //===----------------------------------------------------------------------===//
15 // Get the target-independent interfaces which we are implementing...
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // X86 Subtarget features.
21 //===----------------------------------------------------------------------===//
23 def FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX",
24 "Enable MMX instructions">;
25 def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
26 "Enable SSE instructions",
28 def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
29 "Enable SSE2 instructions",
31 def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
32 "Enable SSE3 instructions",
34 def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
35 "Enable SSSE3 instructions",
37 def FeatureSSE41 : SubtargetFeature<"sse41", "X86SSELevel", "SSE41",
38 "Enable SSE 4.1 instructions",
40 def FeatureSSE42 : SubtargetFeature<"sse42", "X86SSELevel", "SSE42",
41 "Enable SSE 4.2 instructions",
43 def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
44 "Enable 3DNow! instructions">;
45 def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
46 "Enable 3DNow! Athlon instructions",
48 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
49 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
50 // without disabling 64-bit mode.
51 def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true",
52 "Support 64-bit instructions">;
53 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
54 "Bit testing of memory is slow">;
56 //===----------------------------------------------------------------------===//
57 // X86 processors supported.
58 //===----------------------------------------------------------------------===//
60 class Proc<string Name, list<SubtargetFeature> Features>
61 : Processor<Name, NoItineraries, Features>;
63 def : Proc<"generic", []>;
64 def : Proc<"i386", []>;
65 def : Proc<"i486", []>;
66 def : Proc<"i586", []>;
67 def : Proc<"pentium", []>;
68 def : Proc<"pentium-mmx", [FeatureMMX]>;
69 def : Proc<"i686", []>;
70 def : Proc<"pentiumpro", []>;
71 def : Proc<"pentium2", [FeatureMMX]>;
72 def : Proc<"pentium3", [FeatureSSE1]>;
73 def : Proc<"pentium-m", [FeatureSSE2, FeatureSlowBTMem]>;
74 def : Proc<"pentium4", [FeatureSSE2]>;
75 def : Proc<"x86-64", [FeatureSSE2, Feature64Bit, FeatureSlowBTMem]>;
76 def : Proc<"yonah", [FeatureSSE3, FeatureSlowBTMem]>;
77 def : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>;
78 def : Proc<"nocona", [FeatureSSE3, Feature64Bit, FeatureSlowBTMem]>;
79 def : Proc<"core2", [FeatureSSSE3, Feature64Bit, FeatureSlowBTMem]>;
80 def : Proc<"penryn", [FeatureSSE41, Feature64Bit, FeatureSlowBTMem]>;
81 def : Proc<"atom", [FeatureSSE3, Feature64Bit, FeatureSlowBTMem]>;
82 def : Proc<"corei7", [FeatureSSE42, Feature64Bit, FeatureSlowBTMem]>;
84 def : Proc<"k6", [FeatureMMX]>;
85 def : Proc<"k6-2", [FeatureMMX, Feature3DNow]>;
86 def : Proc<"k6-3", [FeatureMMX, Feature3DNow]>;
87 def : Proc<"athlon", [FeatureMMX, Feature3DNowA, FeatureSlowBTMem]>;
88 def : Proc<"athlon-tbird", [FeatureMMX, Feature3DNowA, FeatureSlowBTMem]>;
89 def : Proc<"athlon-4", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
90 def : Proc<"athlon-xp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
91 def : Proc<"athlon-mp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
92 def : Proc<"k8", [FeatureSSE2, Feature3DNowA, Feature64Bit,
94 def : Proc<"opteron", [FeatureSSE2, Feature3DNowA, Feature64Bit,
96 def : Proc<"athlon64", [FeatureSSE2, Feature3DNowA, Feature64Bit,
98 def : Proc<"athlon-fx", [FeatureSSE2, Feature3DNowA, Feature64Bit,
101 def : Proc<"winchip-c6", [FeatureMMX]>;
102 def : Proc<"winchip2", [FeatureMMX, Feature3DNow]>;
103 def : Proc<"c3", [FeatureMMX, Feature3DNow]>;
104 def : Proc<"c3-2", [FeatureSSE1]>;
106 //===----------------------------------------------------------------------===//
107 // Register File Description
108 //===----------------------------------------------------------------------===//
110 include "X86RegisterInfo.td"
112 //===----------------------------------------------------------------------===//
113 // Instruction Descriptions
114 //===----------------------------------------------------------------------===//
116 include "X86InstrInfo.td"
118 def X86InstrInfo : InstrInfo {
120 // Define how we want to layout our TargetSpecific information field... This
121 // should be kept up-to-date with the fields in the X86InstrInfo.h file.
122 let TSFlagsFields = ["FormBits",
132 let TSFlagsShifts = [0,
144 //===----------------------------------------------------------------------===//
145 // Calling Conventions
146 //===----------------------------------------------------------------------===//
148 include "X86CallingConv.td"
151 //===----------------------------------------------------------------------===//
153 //===----------------------------------------------------------------------===//
155 // The X86 target supports two different syntaxes for emitting machine code.
156 // This is controlled by the -x86-asm-syntax={att|intel}
157 def ATTAsmWriter : AsmWriter {
158 string AsmWriterClassName = "ATTAsmPrinter";
161 def IntelAsmWriter : AsmWriter {
162 string AsmWriterClassName = "IntelAsmPrinter";
168 // Information about the instructions...
169 let InstructionSet = X86InstrInfo;
171 let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];