1 //===- X86.td - Target definition file for the Intel X86 ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is a target description file for the Intel i386 architecture, referred to
11 // here as the "X86" architecture.
13 //===----------------------------------------------------------------------===//
15 // Get the target-independent interfaces which we are implementing...
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // X86 Subtarget state.
23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
24 "64-bit mode (x86_64)">;
26 def ModeNaCl : SubtargetFeature<"nacl-mode", "InNaClMode", "true",
27 "Native Client mode">;
29 //===----------------------------------------------------------------------===//
30 // X86 Subtarget features.
31 //===----------------------------------------------------------------------===//
33 def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true",
34 "Enable conditional move instructions">;
36 def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
37 "Support POPCNT instruction">;
40 def FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX",
41 "Enable MMX instructions">;
42 def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
43 "Enable SSE instructions",
44 // SSE codegen depends on cmovs, and all
45 // SSE1+ processors support them.
46 [FeatureMMX, FeatureCMOV]>;
47 def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
48 "Enable SSE2 instructions",
50 def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
51 "Enable SSE3 instructions",
53 def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
54 "Enable SSSE3 instructions",
56 def FeatureSSE41 : SubtargetFeature<"sse41", "X86SSELevel", "SSE41",
57 "Enable SSE 4.1 instructions",
59 def FeatureSSE42 : SubtargetFeature<"sse42", "X86SSELevel", "SSE42",
60 "Enable SSE 4.2 instructions",
61 [FeatureSSE41, FeaturePOPCNT]>;
62 def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
63 "Enable 3DNow! instructions",
65 def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
66 "Enable 3DNow! Athlon instructions",
68 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
69 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
70 // without disabling 64-bit mode.
71 def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true",
72 "Support 64-bit instructions",
74 def FeatureCMPXCHG16B : SubtargetFeature<"cmpxchg16b", "HasCmpxchg16b", "true",
75 "64-bit with cmpxchg16b",
77 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
78 "Bit testing of memory is slow">;
79 def FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem",
80 "IsUAMemFast", "true",
81 "Fast unaligned memory access">;
82 def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true",
83 "Support SSE 4a instructions",
86 def FeatureAVX : SubtargetFeature<"avx", "HasAVX", "true",
87 "Enable AVX instructions">;
88 def FeatureCLMUL : SubtargetFeature<"clmul", "HasCLMUL", "true",
89 "Enable carry-less multiplication instructions">;
90 def FeatureFMA3 : SubtargetFeature<"fma3", "HasFMA3", "true",
91 "Enable three-operand fused multiple-add">;
92 def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true",
93 "Enable four-operand fused multiple-add">;
94 def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
95 "HasVectorUAMem", "true",
96 "Allow unaligned memory operands on vector/SIMD instructions">;
97 def FeatureAES : SubtargetFeature<"aes", "HasAES", "true",
98 "Enable AES instructions">;
100 //===----------------------------------------------------------------------===//
101 // X86 processors supported.
102 //===----------------------------------------------------------------------===//
104 class Proc<string Name, list<SubtargetFeature> Features>
105 : Processor<Name, NoItineraries, Features>;
107 def : Proc<"generic", []>;
108 def : Proc<"i386", []>;
109 def : Proc<"i486", []>;
110 def : Proc<"i586", []>;
111 def : Proc<"pentium", []>;
112 def : Proc<"pentium-mmx", [FeatureMMX]>;
113 def : Proc<"i686", []>;
114 def : Proc<"pentiumpro", [FeatureCMOV]>;
115 def : Proc<"pentium2", [FeatureMMX, FeatureCMOV]>;
116 def : Proc<"pentium3", [FeatureSSE1]>;
117 def : Proc<"pentium3m", [FeatureSSE1, FeatureSlowBTMem]>;
118 def : Proc<"pentium-m", [FeatureSSE2, FeatureSlowBTMem]>;
119 def : Proc<"pentium4", [FeatureSSE2]>;
120 def : Proc<"pentium4m", [FeatureSSE2, FeatureSlowBTMem]>;
121 def : Proc<"x86-64", [FeatureSSE2, Feature64Bit, FeatureSlowBTMem]>;
122 def : Proc<"yonah", [FeatureSSE3, FeatureSlowBTMem]>;
123 def : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>;
124 def : Proc<"nocona", [FeatureSSE3, FeatureCMPXCHG16B,
126 def : Proc<"core2", [FeatureSSSE3, FeatureCMPXCHG16B,
128 def : Proc<"penryn", [FeatureSSE41, FeatureCMPXCHG16B,
130 def : Proc<"atom", [FeatureSSE3, FeatureCMPXCHG16B,
132 // "Arrandale" along with corei3 and corei5
133 def : Proc<"corei7", [FeatureSSE42, FeatureCMPXCHG16B,
134 FeatureSlowBTMem, FeatureFastUAMem, FeatureAES]>;
135 def : Proc<"nehalem", [FeatureSSE42, FeatureCMPXCHG16B,
136 FeatureSlowBTMem, FeatureFastUAMem]>;
137 // Westmere is a similar machine to nehalem with some additional features.
138 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
139 def : Proc<"westmere", [FeatureSSE42, FeatureCMPXCHG16B,
140 FeatureSlowBTMem, FeatureFastUAMem, FeatureAES,
142 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
143 // rather than a superset.
144 // FIXME: Disabling AVX for now since it's not ready.
145 def : Proc<"corei7-avx", [FeatureSSE42, FeatureCMPXCHG16B,
146 FeatureAES, FeatureCLMUL]>;
148 def : Proc<"k6", [FeatureMMX]>;
149 def : Proc<"k6-2", [Feature3DNow]>;
150 def : Proc<"k6-3", [Feature3DNow]>;
151 def : Proc<"athlon", [Feature3DNowA, FeatureSlowBTMem]>;
152 def : Proc<"athlon-tbird", [Feature3DNowA, FeatureSlowBTMem]>;
153 def : Proc<"athlon-4", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
154 def : Proc<"athlon-xp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
155 def : Proc<"athlon-mp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
156 def : Proc<"k8", [FeatureSSE2, Feature3DNowA, Feature64Bit,
158 def : Proc<"opteron", [FeatureSSE2, Feature3DNowA, Feature64Bit,
160 def : Proc<"athlon64", [FeatureSSE2, Feature3DNowA, Feature64Bit,
162 def : Proc<"athlon-fx", [FeatureSSE2, Feature3DNowA, Feature64Bit,
164 def : Proc<"k8-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
166 def : Proc<"opteron-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
168 def : Proc<"athlon64-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
170 def : Proc<"amdfam10", [FeatureSSE3, FeatureSSE4A,
171 Feature3DNowA, FeatureCMPXCHG16B,
173 def : Proc<"barcelona", [FeatureSSE3, FeatureSSE4A,
174 Feature3DNowA, FeatureCMPXCHG16B,
176 def : Proc<"istanbul", [Feature3DNowA, FeatureCMPXCHG16B,
177 FeatureSSE4A, Feature3DNowA]>;
178 def : Proc<"shanghai", [Feature3DNowA, FeatureCMPXCHG16B, FeatureSSE4A,
181 def : Proc<"winchip-c6", [FeatureMMX]>;
182 def : Proc<"winchip2", [Feature3DNow]>;
183 def : Proc<"c3", [Feature3DNow]>;
184 def : Proc<"c3-2", [FeatureSSE1]>;
186 //===----------------------------------------------------------------------===//
187 // Register File Description
188 //===----------------------------------------------------------------------===//
190 include "X86RegisterInfo.td"
192 //===----------------------------------------------------------------------===//
193 // Instruction Descriptions
194 //===----------------------------------------------------------------------===//
196 include "X86InstrInfo.td"
198 def X86InstrInfo : InstrInfo;
200 //===----------------------------------------------------------------------===//
201 // Calling Conventions
202 //===----------------------------------------------------------------------===//
204 include "X86CallingConv.td"
207 //===----------------------------------------------------------------------===//
209 //===----------------------------------------------------------------------===//
211 // Currently the X86 assembly parser only supports ATT syntax.
212 def ATTAsmParser : AsmParser {
213 string AsmParserClassName = "ATTAsmParser";
216 // Discard comments in assembly strings.
217 string CommentDelimiter = "#";
219 // Recognize hard coded registers.
220 string RegisterPrefix = "%";
223 //===----------------------------------------------------------------------===//
225 //===----------------------------------------------------------------------===//
227 // The X86 target supports two different syntaxes for emitting machine code.
228 // This is controlled by the -x86-asm-syntax={att|intel}
229 def ATTAsmWriter : AsmWriter {
230 string AsmWriterClassName = "ATTInstPrinter";
232 bit isMCAsmWriter = 1;
234 def IntelAsmWriter : AsmWriter {
235 string AsmWriterClassName = "IntelInstPrinter";
237 bit isMCAsmWriter = 1;
241 // Information about the instructions...
242 let InstructionSet = X86InstrInfo;
244 let AssemblyParsers = [ATTAsmParser];
246 let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];