1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is a target description file for the Intel i386 architecture, referred
11 // to here as the "X86" architecture.
13 //===----------------------------------------------------------------------===//
15 // Get the target-independent interfaces which we are implementing...
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // X86 Subtarget state
23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
24 "64-bit mode (x86_64)">;
25 def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",
26 "32-bit mode (80386)">;
27 def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
28 "16-bit mode (i8086)">;
30 //===----------------------------------------------------------------------===//
31 // X86 Subtarget features
32 //===----------------------------------------------------------------------===//
34 def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true",
35 "Enable conditional move instructions">;
37 def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
38 "Support POPCNT instruction">;
41 def FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX",
42 "Enable MMX instructions">;
43 def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
44 "Enable SSE instructions",
45 // SSE codegen depends on cmovs, and all
46 // SSE1+ processors support them.
47 [FeatureMMX, FeatureCMOV]>;
48 def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
49 "Enable SSE2 instructions",
51 def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
52 "Enable SSE3 instructions",
54 def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
55 "Enable SSSE3 instructions",
57 def FeatureSSE41 : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
58 "Enable SSE 4.1 instructions",
60 def FeatureSSE42 : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
61 "Enable SSE 4.2 instructions",
63 def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
64 "Enable 3DNow! instructions",
66 def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
67 "Enable 3DNow! Athlon instructions",
69 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
70 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
71 // without disabling 64-bit mode.
72 def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true",
73 "Support 64-bit instructions",
75 def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
76 "64-bit with cmpxchg16b",
78 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
79 "Bit testing of memory is slow">;
80 def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
81 "SHLD instruction is slow">;
82 // FIXME: This should not apply to CPUs that do not have SSE.
83 def FeatureSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16",
84 "IsUAMem16Slow", "true",
85 "Slow unaligned 16-byte memory access">;
86 def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
87 "IsUAMem32Slow", "true",
88 "Slow unaligned 32-byte memory access">;
89 def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true",
90 "Support SSE 4a instructions",
93 def FeatureAVX : SubtargetFeature<"avx", "X86SSELevel", "AVX",
94 "Enable AVX instructions",
96 def FeatureAVX2 : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
97 "Enable AVX2 instructions",
99 def FeatureAVX512 : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
100 "Enable AVX-512 instructions",
102 def FeatureERI : SubtargetFeature<"avx512er", "HasERI", "true",
103 "Enable AVX-512 Exponential and Reciprocal Instructions",
105 def FeatureCDI : SubtargetFeature<"avx512cd", "HasCDI", "true",
106 "Enable AVX-512 Conflict Detection Instructions",
108 def FeaturePFI : SubtargetFeature<"avx512pf", "HasPFI", "true",
109 "Enable AVX-512 PreFetch Instructions",
111 def FeatureDQI : SubtargetFeature<"avx512dq", "HasDQI", "true",
112 "Enable AVX-512 Doubleword and Quadword Instructions",
114 def FeatureBWI : SubtargetFeature<"avx512bw", "HasBWI", "true",
115 "Enable AVX-512 Byte and Word Instructions",
117 def FeatureVLX : SubtargetFeature<"avx512vl", "HasVLX", "true",
118 "Enable AVX-512 Vector Length eXtensions",
120 def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
121 "Enable packed carry-less multiplication instructions",
123 def FeatureFMA : SubtargetFeature<"fma", "HasFMA", "true",
124 "Enable three-operand fused multiple-add",
126 def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true",
127 "Enable four-operand fused multiple-add",
128 [FeatureAVX, FeatureSSE4A]>;
129 def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true",
130 "Enable XOP instructions",
132 def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem",
133 "HasSSEUnalignedMem", "true",
134 "Allow unaligned memory operands with SSE instructions">;
135 def FeatureAES : SubtargetFeature<"aes", "HasAES", "true",
136 "Enable AES instructions",
138 def FeatureTBM : SubtargetFeature<"tbm", "HasTBM", "true",
139 "Enable TBM instructions">;
140 def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true",
141 "Support MOVBE instruction">;
142 def FeatureRDRAND : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
143 "Support RDRAND instruction">;
144 def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true",
145 "Support 16-bit floating point conversion instructions",
147 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
148 "Support FS/GS Base instructions">;
149 def FeatureLZCNT : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
150 "Support LZCNT instruction">;
151 def FeatureBMI : SubtargetFeature<"bmi", "HasBMI", "true",
152 "Support BMI instructions">;
153 def FeatureBMI2 : SubtargetFeature<"bmi2", "HasBMI2", "true",
154 "Support BMI2 instructions">;
155 def FeatureRTM : SubtargetFeature<"rtm", "HasRTM", "true",
156 "Support RTM instructions">;
157 def FeatureHLE : SubtargetFeature<"hle", "HasHLE", "true",
159 def FeatureADX : SubtargetFeature<"adx", "HasADX", "true",
160 "Support ADX instructions">;
161 def FeatureSHA : SubtargetFeature<"sha", "HasSHA", "true",
162 "Enable SHA instructions",
164 def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
165 "Support PRFCHW instructions">;
166 def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true",
167 "Support RDSEED instruction">;
168 def FeatureMPX : SubtargetFeature<"mpx", "HasMPX", "true",
169 "Support MPX instructions">;
170 def FeatureLeaForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
171 "Use LEA for adjusting the stack pointer">;
172 def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
173 "HasSlowDivide32", "true",
174 "Use 8-bit divide for positive values less than 256">;
175 def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divw",
176 "HasSlowDivide64", "true",
177 "Use 16-bit divide for positive values less than 65536">;
178 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
179 "PadShortFunctions", "true",
180 "Pad short functions">;
181 // TODO: This feature ought to be renamed.
182 // What it really refers to are CPUs for which certain instructions
183 // (which ones besides the example below?) are microcoded.
184 // The best examples of this are the memory forms of CALL and PUSH
185 // instructions, which should be avoided in favor of a MOV + register CALL/PUSH.
186 def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect",
187 "CallRegIndirect", "true",
188 "Call register indirect">;
189 def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
190 "LEA instruction needs inputs at AG stage">;
191 def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
192 "LEA instruction with certain arguments is slow">;
193 def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
194 "INC and DEC instructions are slower than ADD and SUB">;
196 : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
197 "Use software floating point features.">;
199 //===----------------------------------------------------------------------===//
200 // X86 processors supported.
201 //===----------------------------------------------------------------------===//
203 include "X86Schedule.td"
205 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
206 "Intel Atom processors">;
207 def ProcIntelSLM : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM",
208 "Intel Silvermont processors">;
210 class Proc<string Name, list<SubtargetFeature> Features>
211 : ProcessorModel<Name, GenericModel, Features>;
213 def : Proc<"generic", [FeatureSlowUAMem16]>;
214 def : Proc<"i386", [FeatureSlowUAMem16]>;
215 def : Proc<"i486", [FeatureSlowUAMem16]>;
216 def : Proc<"i586", [FeatureSlowUAMem16]>;
217 def : Proc<"pentium", [FeatureSlowUAMem16]>;
218 def : Proc<"pentium-mmx", [FeatureSlowUAMem16, FeatureMMX]>;
219 def : Proc<"i686", [FeatureSlowUAMem16]>;
220 def : Proc<"pentiumpro", [FeatureSlowUAMem16, FeatureCMOV]>;
221 def : Proc<"pentium2", [FeatureSlowUAMem16, FeatureMMX, FeatureCMOV]>;
222 def : Proc<"pentium3", [FeatureSlowUAMem16, FeatureSSE1]>;
223 def : Proc<"pentium3m", [FeatureSlowUAMem16, FeatureSSE1,
225 def : Proc<"pentium-m", [FeatureSlowUAMem16, FeatureSSE2,
227 def : Proc<"pentium4", [FeatureSlowUAMem16, FeatureSSE2]>;
228 def : Proc<"pentium4m", [FeatureSlowUAMem16, FeatureSSE2,
232 def : ProcessorModel<"yonah", SandyBridgeModel,
233 [FeatureSlowUAMem16, FeatureSSE3, FeatureSlowBTMem]>;
236 def : Proc<"prescott", [FeatureSlowUAMem16, FeatureSSE3, FeatureSlowBTMem]>;
237 def : Proc<"nocona", [FeatureSlowUAMem16, FeatureSSE3, FeatureCMPXCHG16B,
240 // Intel Core 2 Solo/Duo.
241 def : ProcessorModel<"core2", SandyBridgeModel,
242 [FeatureSlowUAMem16, FeatureSSSE3, FeatureCMPXCHG16B,
244 def : ProcessorModel<"penryn", SandyBridgeModel,
245 [FeatureSlowUAMem16, FeatureSSE41, FeatureCMPXCHG16B,
249 class BonnellProc<string Name> : ProcessorModel<Name, AtomModel, [
259 FeatureCallRegIndirect,
261 FeaturePadShortFunctions
263 def : BonnellProc<"bonnell">;
264 def : BonnellProc<"atom">; // Pin the generic name to the baseline.
266 class SilvermontProc<string Name> : ProcessorModel<Name, SLMModel, [
275 FeatureCallRegIndirect,
281 def : SilvermontProc<"silvermont">;
282 def : SilvermontProc<"slm">; // Legacy alias.
284 // "Arrandale" along with corei3 and corei5
285 class NehalemProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
291 def : NehalemProc<"nehalem">;
292 def : NehalemProc<"corei7">;
294 // Westmere is a similar machine to nehalem with some additional features.
295 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
296 class WestmereProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
304 def : WestmereProc<"westmere">;
306 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
307 // rather than a superset.
308 class SandyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
317 def : SandyBridgeProc<"sandybridge">;
318 def : SandyBridgeProc<"corei7-avx">; // Legacy alias.
320 class IvyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
332 def : IvyBridgeProc<"ivybridge">;
333 def : IvyBridgeProc<"core-avx-i">; // Legacy alias.
335 class HaswellProc<string Name> : ProcessorModel<Name, HaswellModel, [
354 def : HaswellProc<"haswell">;
355 def : HaswellProc<"core-avx2">; // Legacy alias.
357 class BroadwellProc<string Name> : ProcessorModel<Name, HaswellModel, [
378 def : BroadwellProc<"broadwell">;
380 // FIXME: define KNL model
381 class KnightsLandingProc<string Name> : ProcessorModel<Name, HaswellModel,
382 [FeatureAVX512, FeatureERI, FeatureCDI, FeaturePFI,
383 FeatureCMPXCHG16B, FeaturePOPCNT,
384 FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C,
385 FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI,
386 FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE,
387 FeatureSlowIncDec, FeatureMPX]>;
388 def : KnightsLandingProc<"knl">;
390 // FIXME: define SKX model
391 class SkylakeProc<string Name> : ProcessorModel<Name, HaswellModel,
392 [FeatureAVX512, FeatureCDI,
393 FeatureDQI, FeatureBWI, FeatureVLX,
394 FeatureCMPXCHG16B, FeatureSlowBTMem,
395 FeaturePOPCNT, FeatureAES, FeaturePCLMUL, FeatureRDRAND,
396 FeatureF16C, FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT,
397 FeatureBMI, FeatureBMI2, FeatureFMA, FeatureRTM,
398 FeatureHLE, FeatureADX, FeatureRDSEED, FeatureSlowIncDec,
400 def : SkylakeProc<"skylake">;
401 def : SkylakeProc<"skx">; // Legacy alias.
406 def : Proc<"k6", [FeatureSlowUAMem16, FeatureMMX]>;
407 def : Proc<"k6-2", [FeatureSlowUAMem16, Feature3DNow]>;
408 def : Proc<"k6-3", [FeatureSlowUAMem16, Feature3DNow]>;
409 def : Proc<"athlon", [FeatureSlowUAMem16, Feature3DNowA,
410 FeatureSlowBTMem, FeatureSlowSHLD]>;
411 def : Proc<"athlon-tbird", [FeatureSlowUAMem16, Feature3DNowA,
412 FeatureSlowBTMem, FeatureSlowSHLD]>;
413 def : Proc<"athlon-4", [FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA,
414 FeatureSlowBTMem, FeatureSlowSHLD]>;
415 def : Proc<"athlon-xp", [FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA,
416 FeatureSlowBTMem, FeatureSlowSHLD]>;
417 def : Proc<"athlon-mp", [FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA,
418 FeatureSlowBTMem, FeatureSlowSHLD]>;
419 def : Proc<"k8", [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
420 Feature64Bit, FeatureSlowBTMem,
422 def : Proc<"opteron", [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
423 Feature64Bit, FeatureSlowBTMem,
425 def : Proc<"athlon64", [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
426 Feature64Bit, FeatureSlowBTMem,
428 def : Proc<"athlon-fx", [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
429 Feature64Bit, FeatureSlowBTMem,
431 def : Proc<"k8-sse3", [FeatureSlowUAMem16, FeatureSSE3, Feature3DNowA,
432 FeatureCMPXCHG16B, FeatureSlowBTMem,
434 def : Proc<"opteron-sse3", [FeatureSlowUAMem16, FeatureSSE3, Feature3DNowA,
435 FeatureCMPXCHG16B, FeatureSlowBTMem,
437 def : Proc<"athlon64-sse3", [FeatureSlowUAMem16, FeatureSSE3, Feature3DNowA,
438 FeatureCMPXCHG16B, FeatureSlowBTMem,
440 def : Proc<"amdfam10", [FeatureSSE4A,
441 Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
442 FeaturePOPCNT, FeatureSlowBTMem,
444 def : Proc<"barcelona", [FeatureSSE4A,
445 Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
446 FeaturePOPCNT, FeatureSlowBTMem,
450 def : Proc<"btver1", [FeatureSSSE3, FeatureSSE4A, FeatureCMPXCHG16B,
451 FeaturePRFCHW, FeatureLZCNT, FeaturePOPCNT,
455 def : ProcessorModel<"btver2", BtVer2Model,
456 [FeatureAVX, FeatureSSE4A, FeatureCMPXCHG16B,
457 FeaturePRFCHW, FeatureAES, FeaturePCLMUL,
458 FeatureBMI, FeatureF16C, FeatureMOVBE,
459 FeatureLZCNT, FeaturePOPCNT,
463 def : Proc<"bdver1", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
464 FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
465 FeatureAVX, FeatureSSE4A, FeatureLZCNT,
466 FeaturePOPCNT, FeatureSlowSHLD]>;
468 def : Proc<"bdver2", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
469 FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
470 FeatureAVX, FeatureSSE4A, FeatureF16C,
471 FeatureLZCNT, FeaturePOPCNT, FeatureBMI,
472 FeatureTBM, FeatureFMA, FeatureSlowSHLD]>;
475 def : Proc<"bdver3", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
476 FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
477 FeatureAVX, FeatureSSE4A, FeatureF16C,
478 FeatureLZCNT, FeaturePOPCNT, FeatureBMI,
479 FeatureTBM, FeatureFMA, FeatureSlowSHLD,
483 def : Proc<"bdver4", [FeatureAVX2, FeatureXOP, FeatureFMA4,
484 FeatureCMPXCHG16B, FeatureAES, FeaturePRFCHW,
485 FeaturePCLMUL, FeatureF16C, FeatureLZCNT,
486 FeaturePOPCNT, FeatureBMI, FeatureBMI2,
487 FeatureTBM, FeatureFMA, FeatureSSE4A,
490 def : Proc<"geode", [FeatureSlowUAMem16, Feature3DNowA]>;
492 def : Proc<"winchip-c6", [FeatureSlowUAMem16, FeatureMMX]>;
493 def : Proc<"winchip2", [FeatureSlowUAMem16, Feature3DNow]>;
494 def : Proc<"c3", [FeatureSlowUAMem16, Feature3DNow]>;
495 def : Proc<"c3-2", [FeatureSlowUAMem16, FeatureSSE1]>;
497 // We also provide a generic 64-bit specific x86 processor model which tries to
498 // be good for modern chips without enabling instruction set encodings past the
499 // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
500 // modern 64-bit x86 chip, and enables features that are generally beneficial.
502 // We currently use the Sandy Bridge model as the default scheduling model as
503 // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
504 // covers a huge swath of x86 processors. If there are specific scheduling
505 // knobs which need to be tuned differently for AMD chips, we might consider
506 // forming a common base for them.
507 def : ProcessorModel<"x86-64", SandyBridgeModel,
508 [FeatureSSE2, Feature64Bit, FeatureSlowBTMem]>;
510 //===----------------------------------------------------------------------===//
511 // Register File Description
512 //===----------------------------------------------------------------------===//
514 include "X86RegisterInfo.td"
516 //===----------------------------------------------------------------------===//
517 // Instruction Descriptions
518 //===----------------------------------------------------------------------===//
520 include "X86InstrInfo.td"
522 def X86InstrInfo : InstrInfo;
524 //===----------------------------------------------------------------------===//
525 // Calling Conventions
526 //===----------------------------------------------------------------------===//
528 include "X86CallingConv.td"
531 //===----------------------------------------------------------------------===//
533 //===----------------------------------------------------------------------===//
535 def ATTAsmParser : AsmParser {
536 string AsmParserClassName = "AsmParser";
539 def ATTAsmParserVariant : AsmParserVariant {
545 // Discard comments in assembly strings.
546 string CommentDelimiter = "#";
548 // Recognize hard coded registers.
549 string RegisterPrefix = "%";
552 def IntelAsmParserVariant : AsmParserVariant {
556 string Name = "intel";
558 // Discard comments in assembly strings.
559 string CommentDelimiter = ";";
561 // Recognize hard coded registers.
562 string RegisterPrefix = "";
565 //===----------------------------------------------------------------------===//
567 //===----------------------------------------------------------------------===//
569 // The X86 target supports two different syntaxes for emitting machine code.
570 // This is controlled by the -x86-asm-syntax={att|intel}
571 def ATTAsmWriter : AsmWriter {
572 string AsmWriterClassName = "ATTInstPrinter";
575 def IntelAsmWriter : AsmWriter {
576 string AsmWriterClassName = "IntelInstPrinter";
581 // Information about the instructions...
582 let InstructionSet = X86InstrInfo;
583 let AssemblyParsers = [ATTAsmParser];
584 let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
585 let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];