1 //===- X86.td - Target definition file for the Intel X86 ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is a target description file for the Intel i386 architecture, referred to
11 // here as the "X86" architecture.
13 //===----------------------------------------------------------------------===//
15 // Get the target-independent interfaces which we are implementing...
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // X86 Subtarget state.
23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
24 "64-bit mode (x86_64)">;
26 //===----------------------------------------------------------------------===//
27 // X86 Subtarget features.
28 //===----------------------------------------------------------------------===//
30 def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true",
31 "Enable conditional move instructions">;
33 def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
34 "Support POPCNT instruction">;
37 def FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX",
38 "Enable MMX instructions">;
39 def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
40 "Enable SSE instructions",
41 // SSE codegen depends on cmovs, and all
42 // SSE1+ processors support them.
43 [FeatureMMX, FeatureCMOV]>;
44 def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
45 "Enable SSE2 instructions",
47 def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
48 "Enable SSE3 instructions",
50 def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
51 "Enable SSSE3 instructions",
53 def FeatureSSE41 : SubtargetFeature<"sse41", "X86SSELevel", "SSE41",
54 "Enable SSE 4.1 instructions",
56 def FeatureSSE42 : SubtargetFeature<"sse42", "X86SSELevel", "SSE42",
57 "Enable SSE 4.2 instructions",
58 [FeatureSSE41, FeaturePOPCNT]>;
59 def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
60 "Enable 3DNow! instructions",
62 def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
63 "Enable 3DNow! Athlon instructions",
65 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
66 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
67 // without disabling 64-bit mode.
68 def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true",
69 "Support 64-bit instructions",
71 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
72 "Bit testing of memory is slow">;
73 def FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem",
74 "IsUAMemFast", "true",
75 "Fast unaligned memory access">;
76 def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true",
77 "Support SSE 4a instructions",
80 def FeatureAVX : SubtargetFeature<"avx", "HasAVX", "true",
81 "Enable AVX instructions">;
82 def FeatureCLMUL : SubtargetFeature<"clmul", "HasCLMUL", "true",
83 "Enable carry-less multiplication instructions">;
84 def FeatureFMA3 : SubtargetFeature<"fma3", "HasFMA3", "true",
85 "Enable three-operand fused multiple-add">;
86 def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true",
87 "Enable four-operand fused multiple-add">;
88 def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
89 "HasVectorUAMem", "true",
90 "Allow unaligned memory operands on vector/SIMD instructions">;
91 def FeatureAES : SubtargetFeature<"aes", "HasAES", "true",
92 "Enable AES instructions">;
94 //===----------------------------------------------------------------------===//
95 // X86 processors supported.
96 //===----------------------------------------------------------------------===//
98 class Proc<string Name, list<SubtargetFeature> Features>
99 : Processor<Name, NoItineraries, Features>;
101 def : Proc<"generic", []>;
102 def : Proc<"i386", []>;
103 def : Proc<"i486", []>;
104 def : Proc<"i586", []>;
105 def : Proc<"pentium", []>;
106 def : Proc<"pentium-mmx", [FeatureMMX]>;
107 def : Proc<"i686", []>;
108 def : Proc<"pentiumpro", [FeatureCMOV]>;
109 def : Proc<"pentium2", [FeatureMMX, FeatureCMOV]>;
110 def : Proc<"pentium3", [FeatureSSE1]>;
111 def : Proc<"pentium3m", [FeatureSSE1, FeatureSlowBTMem]>;
112 def : Proc<"pentium-m", [FeatureSSE2, FeatureSlowBTMem]>;
113 def : Proc<"pentium4", [FeatureSSE2]>;
114 def : Proc<"pentium4m", [FeatureSSE2, FeatureSlowBTMem]>;
115 def : Proc<"x86-64", [FeatureSSE2, Feature64Bit, FeatureSlowBTMem]>;
116 def : Proc<"yonah", [FeatureSSE3, FeatureSlowBTMem]>;
117 def : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>;
118 def : Proc<"nocona", [FeatureSSE3, Feature64Bit, FeatureSlowBTMem]>;
119 def : Proc<"core2", [FeatureSSSE3, Feature64Bit, FeatureSlowBTMem]>;
120 def : Proc<"penryn", [FeatureSSE41, Feature64Bit, FeatureSlowBTMem]>;
121 def : Proc<"atom", [FeatureSSE3, Feature64Bit, FeatureSlowBTMem]>;
122 // "Arrandale" along with corei3 and corei5
123 def : Proc<"corei7", [FeatureSSE42, Feature64Bit, FeatureSlowBTMem,
124 FeatureFastUAMem, FeatureAES]>;
125 def : Proc<"nehalem", [FeatureSSE42, Feature64Bit, FeatureSlowBTMem,
127 // Westmere is a similar machine to nehalem with some additional features.
128 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
129 def : Proc<"westmere", [FeatureSSE42, Feature64Bit, FeatureSlowBTMem,
130 FeatureFastUAMem, FeatureAES, FeatureCLMUL]>;
131 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
132 // rather than a superset.
133 // FIXME: Disabling AVX for now since it's not ready.
134 def : Proc<"corei7-avx", [FeatureSSE42, Feature64Bit,
135 FeatureAES, FeatureCLMUL]>;
137 def : Proc<"k6", [FeatureMMX]>;
138 def : Proc<"k6-2", [Feature3DNow]>;
139 def : Proc<"k6-3", [Feature3DNow]>;
140 def : Proc<"athlon", [Feature3DNowA, FeatureSlowBTMem]>;
141 def : Proc<"athlon-tbird", [Feature3DNowA, FeatureSlowBTMem]>;
142 def : Proc<"athlon-4", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
143 def : Proc<"athlon-xp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
144 def : Proc<"athlon-mp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
145 def : Proc<"k8", [FeatureSSE2, Feature3DNowA, Feature64Bit,
147 def : Proc<"opteron", [FeatureSSE2, Feature3DNowA, Feature64Bit,
149 def : Proc<"athlon64", [FeatureSSE2, Feature3DNowA, Feature64Bit,
151 def : Proc<"athlon-fx", [FeatureSSE2, Feature3DNowA, Feature64Bit,
153 def : Proc<"k8-sse3", [FeatureSSE3, Feature3DNowA, Feature64Bit,
155 def : Proc<"opteron-sse3", [FeatureSSE3, Feature3DNowA, Feature64Bit,
157 def : Proc<"athlon64-sse3", [FeatureSSE3, Feature3DNowA, Feature64Bit,
159 def : Proc<"amdfam10", [FeatureSSE3, FeatureSSE4A,
160 Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>;
161 def : Proc<"barcelona", [FeatureSSE3, FeatureSSE4A,
162 Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>;
163 def : Proc<"istanbul", [Feature3DNowA, Feature64Bit, FeatureSSE4A,
165 def : Proc<"shanghai", [Feature3DNowA, Feature64Bit, FeatureSSE4A,
168 def : Proc<"winchip-c6", [FeatureMMX]>;
169 def : Proc<"winchip2", [Feature3DNow]>;
170 def : Proc<"c3", [Feature3DNow]>;
171 def : Proc<"c3-2", [FeatureSSE1]>;
173 //===----------------------------------------------------------------------===//
174 // Register File Description
175 //===----------------------------------------------------------------------===//
177 include "X86RegisterInfo.td"
179 //===----------------------------------------------------------------------===//
180 // Instruction Descriptions
181 //===----------------------------------------------------------------------===//
183 include "X86InstrInfo.td"
185 def X86InstrInfo : InstrInfo;
187 //===----------------------------------------------------------------------===//
188 // Calling Conventions
189 //===----------------------------------------------------------------------===//
191 include "X86CallingConv.td"
194 //===----------------------------------------------------------------------===//
196 //===----------------------------------------------------------------------===//
198 // Currently the X86 assembly parser only supports ATT syntax.
199 def ATTAsmParser : AsmParser {
200 string AsmParserClassName = "ATTAsmParser";
203 // Discard comments in assembly strings.
204 string CommentDelimiter = "#";
206 // Recognize hard coded registers.
207 string RegisterPrefix = "%";
210 //===----------------------------------------------------------------------===//
212 //===----------------------------------------------------------------------===//
214 // The X86 target supports two different syntaxes for emitting machine code.
215 // This is controlled by the -x86-asm-syntax={att|intel}
216 def ATTAsmWriter : AsmWriter {
217 string AsmWriterClassName = "ATTInstPrinter";
219 bit isMCAsmWriter = 1;
221 def IntelAsmWriter : AsmWriter {
222 string AsmWriterClassName = "IntelInstPrinter";
224 bit isMCAsmWriter = 1;
228 // Information about the instructions...
229 let InstructionSet = X86InstrInfo;
231 let AssemblyParsers = [ATTAsmParser];
233 let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];