1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is a target description file for the Intel i386 architecture, referred
11 // to here as the "X86" architecture.
13 //===----------------------------------------------------------------------===//
15 // Get the target-independent interfaces which we are implementing...
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // X86 Subtarget state
23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
24 "64-bit mode (x86_64)">;
25 def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",
26 "32-bit mode (80386)">;
27 def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
28 "16-bit mode (i8086)">;
30 //===----------------------------------------------------------------------===//
31 // X86 Subtarget features
32 //===----------------------------------------------------------------------===//
34 def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true",
35 "Enable conditional move instructions">;
37 def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
38 "Support POPCNT instruction">;
40 def FeatureFXSR : SubtargetFeature<"fxsr", "HasFXSR", "true",
41 "Support fxsave/fxrestore instructions">;
43 def FeatureXSAVE : SubtargetFeature<"xsave", "HasXSAVE", "true",
44 "Support xsave instructions">;
46 def FeatureXSAVEOPT: SubtargetFeature<"xsaveopt", "HasXSAVEOPT", "true",
47 "Support xsaveopt instructions">;
49 def FeatureXSAVEC : SubtargetFeature<"xsavec", "HasXSAVEC", "true",
50 "Support xsavec instructions">;
52 def FeatureXSAVES : SubtargetFeature<"xsaves", "HasXSAVES", "true",
53 "Support xsaves instructions">;
55 def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
56 "Enable SSE instructions",
57 // SSE codegen depends on cmovs, and all
58 // SSE1+ processors support them.
60 def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
61 "Enable SSE2 instructions",
63 def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
64 "Enable SSE3 instructions",
66 def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
67 "Enable SSSE3 instructions",
69 def FeatureSSE41 : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
70 "Enable SSE 4.1 instructions",
72 def FeatureSSE42 : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
73 "Enable SSE 4.2 instructions",
75 // The MMX subtarget feature is separate from the rest of the SSE features
76 // because it's important (for odd compatibility reasons) to be able to
77 // turn it off explicitly while allowing SSE+ to be on.
78 def FeatureMMX : SubtargetFeature<"mmx","X863DNowLevel", "MMX",
79 "Enable MMX instructions">;
80 def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
81 "Enable 3DNow! instructions",
83 def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
84 "Enable 3DNow! Athlon instructions",
86 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
87 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
88 // without disabling 64-bit mode.
89 def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true",
90 "Support 64-bit instructions",
92 def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
93 "64-bit with cmpxchg16b",
95 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
96 "Bit testing of memory is slow">;
97 def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
98 "SHLD instruction is slow">;
99 // FIXME: This should not apply to CPUs that do not have SSE.
100 def FeatureSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16",
101 "IsUAMem16Slow", "true",
102 "Slow unaligned 16-byte memory access">;
103 def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
104 "IsUAMem32Slow", "true",
105 "Slow unaligned 32-byte memory access">;
106 def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true",
107 "Support SSE 4a instructions",
110 def FeatureAVX : SubtargetFeature<"avx", "X86SSELevel", "AVX",
111 "Enable AVX instructions",
113 def FeatureAVX2 : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
114 "Enable AVX2 instructions",
116 def FeatureAVX512 : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
117 "Enable AVX-512 instructions",
119 def FeatureERI : SubtargetFeature<"avx512er", "HasERI", "true",
120 "Enable AVX-512 Exponential and Reciprocal Instructions",
122 def FeatureCDI : SubtargetFeature<"avx512cd", "HasCDI", "true",
123 "Enable AVX-512 Conflict Detection Instructions",
125 def FeaturePFI : SubtargetFeature<"avx512pf", "HasPFI", "true",
126 "Enable AVX-512 PreFetch Instructions",
128 def FeatureDQI : SubtargetFeature<"avx512dq", "HasDQI", "true",
129 "Enable AVX-512 Doubleword and Quadword Instructions",
131 def FeatureBWI : SubtargetFeature<"avx512bw", "HasBWI", "true",
132 "Enable AVX-512 Byte and Word Instructions",
134 def FeatureVLX : SubtargetFeature<"avx512vl", "HasVLX", "true",
135 "Enable AVX-512 Vector Length eXtensions",
137 def FeaturePKU : SubtargetFeature<"pku", "HasPKU", "true",
138 "Enable protection keys">;
139 def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
140 "Enable packed carry-less multiplication instructions",
142 def FeatureFMA : SubtargetFeature<"fma", "HasFMA", "true",
143 "Enable three-operand fused multiple-add",
145 def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true",
146 "Enable four-operand fused multiple-add",
147 [FeatureAVX, FeatureSSE4A]>;
148 def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true",
149 "Enable XOP instructions",
151 def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem",
152 "HasSSEUnalignedMem", "true",
153 "Allow unaligned memory operands with SSE instructions">;
154 def FeatureAES : SubtargetFeature<"aes", "HasAES", "true",
155 "Enable AES instructions",
157 def FeatureTBM : SubtargetFeature<"tbm", "HasTBM", "true",
158 "Enable TBM instructions">;
159 def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true",
160 "Support MOVBE instruction">;
161 def FeatureRDRAND : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
162 "Support RDRAND instruction">;
163 def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true",
164 "Support 16-bit floating point conversion instructions",
166 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
167 "Support FS/GS Base instructions">;
168 def FeatureLZCNT : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
169 "Support LZCNT instruction">;
170 def FeatureBMI : SubtargetFeature<"bmi", "HasBMI", "true",
171 "Support BMI instructions">;
172 def FeatureBMI2 : SubtargetFeature<"bmi2", "HasBMI2", "true",
173 "Support BMI2 instructions">;
174 def FeatureRTM : SubtargetFeature<"rtm", "HasRTM", "true",
175 "Support RTM instructions">;
176 def FeatureHLE : SubtargetFeature<"hle", "HasHLE", "true",
178 def FeatureADX : SubtargetFeature<"adx", "HasADX", "true",
179 "Support ADX instructions">;
180 def FeatureSHA : SubtargetFeature<"sha", "HasSHA", "true",
181 "Enable SHA instructions",
183 def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
184 "Support PRFCHW instructions">;
185 def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true",
186 "Support RDSEED instruction">;
187 def FeatureLAHFSAHF : SubtargetFeature<"sahf", "HasLAHFSAHF", "true",
188 "Support LAHF and SAHF instructions">;
189 def FeatureMPX : SubtargetFeature<"mpx", "HasMPX", "true",
190 "Support MPX instructions">;
191 def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
192 "Use LEA for adjusting the stack pointer">;
193 def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
194 "HasSlowDivide32", "true",
195 "Use 8-bit divide for positive values less than 256">;
196 def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divw",
197 "HasSlowDivide64", "true",
198 "Use 16-bit divide for positive values less than 65536">;
199 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
200 "PadShortFunctions", "true",
201 "Pad short functions">;
202 // TODO: This feature ought to be renamed.
203 // What it really refers to are CPUs for which certain instructions
204 // (which ones besides the example below?) are microcoded.
205 // The best examples of this are the memory forms of CALL and PUSH
206 // instructions, which should be avoided in favor of a MOV + register CALL/PUSH.
207 def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect",
208 "CallRegIndirect", "true",
209 "Call register indirect">;
210 def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
211 "LEA instruction needs inputs at AG stage">;
212 def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
213 "LEA instruction with certain arguments is slow">;
214 def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
215 "INC and DEC instructions are slower than ADD and SUB">;
217 : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
218 "Use software floating point features.">;
220 //===----------------------------------------------------------------------===//
221 // X86 processors supported.
222 //===----------------------------------------------------------------------===//
224 include "X86Schedule.td"
226 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
227 "Intel Atom processors">;
228 def ProcIntelSLM : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM",
229 "Intel Silvermont processors">;
231 class Proc<string Name, list<SubtargetFeature> Features>
232 : ProcessorModel<Name, GenericModel, Features>;
234 def : Proc<"generic", [FeatureSlowUAMem16]>;
235 def : Proc<"i386", [FeatureSlowUAMem16]>;
236 def : Proc<"i486", [FeatureSlowUAMem16]>;
237 def : Proc<"i586", [FeatureSlowUAMem16]>;
238 def : Proc<"pentium", [FeatureSlowUAMem16]>;
239 def : Proc<"pentium-mmx", [FeatureSlowUAMem16, FeatureMMX]>;
240 def : Proc<"i686", [FeatureSlowUAMem16]>;
241 def : Proc<"pentiumpro", [FeatureSlowUAMem16, FeatureCMOV]>;
242 def : Proc<"pentium2", [FeatureSlowUAMem16, FeatureMMX, FeatureCMOV,
244 def : Proc<"pentium3", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE1,
246 def : Proc<"pentium3m", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE1,
247 FeatureFXSR, FeatureSlowBTMem]>;
248 def : Proc<"pentium-m", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE2,
249 FeatureFXSR, FeatureSlowBTMem]>;
250 def : Proc<"pentium4", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE2,
252 def : Proc<"pentium4m", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE2,
253 FeatureFXSR, FeatureSlowBTMem]>;
256 def : ProcessorModel<"yonah", SandyBridgeModel,
257 [FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, FeatureFXSR,
261 def : Proc<"prescott",
262 [FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, FeatureFXSR,
264 def : Proc<"nocona", [
273 // Intel Core 2 Solo/Duo.
274 def : ProcessorModel<"core2", SandyBridgeModel, [
283 def : ProcessorModel<"penryn", SandyBridgeModel, [
294 class BonnellProc<string Name> : ProcessorModel<Name, AtomModel, [
306 FeatureCallRegIndirect,
308 FeaturePadShortFunctions,
311 def : BonnellProc<"bonnell">;
312 def : BonnellProc<"atom">; // Pin the generic name to the baseline.
314 class SilvermontProc<string Name> : ProcessorModel<Name, SLMModel, [
325 FeatureCallRegIndirect,
332 def : SilvermontProc<"silvermont">;
333 def : SilvermontProc<"slm">; // Legacy alias.
335 // "Arrandale" along with corei3 and corei5
336 class NehalemProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
345 def : NehalemProc<"nehalem">;
346 def : NehalemProc<"corei7">;
348 // Westmere is a similar machine to nehalem with some additional features.
349 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
350 class WestmereProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
361 def : WestmereProc<"westmere">;
363 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
364 // rather than a superset.
365 class SandyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
379 def : SandyBridgeProc<"sandybridge">;
380 def : SandyBridgeProc<"corei7-avx">; // Legacy alias.
382 class IvyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
399 def : IvyBridgeProc<"ivybridge">;
400 def : IvyBridgeProc<"core-avx-i">; // Legacy alias.
402 class HaswellProc<string Name> : ProcessorModel<Name, HaswellModel, [
426 def : HaswellProc<"haswell">;
427 def : HaswellProc<"core-avx2">; // Legacy alias.
429 class BroadwellProc<string Name> : ProcessorModel<Name, HaswellModel, [
455 def : BroadwellProc<"broadwell">;
457 // FIXME: define KNL model
458 class KnightsLandingProc<string Name> : ProcessorModel<Name, HaswellModel, [
485 def : KnightsLandingProc<"knl">;
487 // FIXME: define SKX model
488 class SkylakeProc<string Name> : ProcessorModel<Name, HaswellModel, [
522 def : SkylakeProc<"skylake">;
523 def : SkylakeProc<"skx">; // Legacy alias.
528 def : Proc<"k6", [FeatureSlowUAMem16, FeatureMMX]>;
529 def : Proc<"k6-2", [FeatureSlowUAMem16, Feature3DNow]>;
530 def : Proc<"k6-3", [FeatureSlowUAMem16, Feature3DNow]>;
531 def : Proc<"athlon", [FeatureSlowUAMem16, Feature3DNowA,
532 FeatureSlowBTMem, FeatureSlowSHLD]>;
533 def : Proc<"athlon-tbird", [FeatureSlowUAMem16, Feature3DNowA,
534 FeatureSlowBTMem, FeatureSlowSHLD]>;
535 def : Proc<"athlon-4", [FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA,
536 FeatureFXSR, FeatureSlowBTMem, FeatureSlowSHLD]>;
537 def : Proc<"athlon-xp", [FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA,
538 FeatureFXSR, FeatureSlowBTMem, FeatureSlowSHLD]>;
539 def : Proc<"athlon-mp", [FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA,
540 FeatureFXSR, FeatureSlowBTMem, FeatureSlowSHLD]>;
541 def : Proc<"k8", [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
542 FeatureFXSR, Feature64Bit, FeatureSlowBTMem,
544 def : Proc<"opteron", [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
545 FeatureFXSR, Feature64Bit, FeatureSlowBTMem,
547 def : Proc<"athlon64", [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
548 FeatureFXSR, Feature64Bit, FeatureSlowBTMem,
550 def : Proc<"athlon-fx", [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
551 FeatureFXSR, Feature64Bit, FeatureSlowBTMem,
553 def : Proc<"k8-sse3", [FeatureSlowUAMem16, FeatureSSE3, Feature3DNowA,
554 FeatureFXSR, FeatureCMPXCHG16B, FeatureSlowBTMem,
556 def : Proc<"opteron-sse3", [FeatureSlowUAMem16, FeatureSSE3, Feature3DNowA,
557 FeatureFXSR, FeatureCMPXCHG16B, FeatureSlowBTMem,
559 def : Proc<"athlon64-sse3", [FeatureSlowUAMem16, FeatureSSE3, Feature3DNowA,
560 FeatureFXSR, FeatureCMPXCHG16B, FeatureSlowBTMem,
562 def : Proc<"amdfam10", [FeatureSSE4A, Feature3DNowA, FeatureFXSR,
563 FeatureCMPXCHG16B, FeatureLZCNT, FeaturePOPCNT,
564 FeatureSlowBTMem, FeatureSlowSHLD, FeatureLAHFSAHF]>;
565 def : Proc<"barcelona", [FeatureSSE4A, Feature3DNowA, FeatureFXSR,
566 FeatureCMPXCHG16B, FeatureLZCNT, FeaturePOPCNT,
567 FeatureSlowBTMem, FeatureSlowSHLD, FeatureLAHFSAHF]>;
570 def : Proc<"btver1", [
585 def : ProcessorModel<"btver2", BtVer2Model, [
606 def : Proc<"bdver1", [
624 def : Proc<"bdver2", [
647 def : Proc<"bdver3", [
672 def : Proc<"bdver4", [
695 def : Proc<"geode", [FeatureSlowUAMem16, Feature3DNowA]>;
697 def : Proc<"winchip-c6", [FeatureSlowUAMem16, FeatureMMX]>;
698 def : Proc<"winchip2", [FeatureSlowUAMem16, Feature3DNow]>;
699 def : Proc<"c3", [FeatureSlowUAMem16, Feature3DNow]>;
700 def : Proc<"c3-2", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE1, FeatureFXSR]>;
702 // We also provide a generic 64-bit specific x86 processor model which tries to
703 // be good for modern chips without enabling instruction set encodings past the
704 // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
705 // modern 64-bit x86 chip, and enables features that are generally beneficial.
707 // We currently use the Sandy Bridge model as the default scheduling model as
708 // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
709 // covers a huge swath of x86 processors. If there are specific scheduling
710 // knobs which need to be tuned differently for AMD chips, we might consider
711 // forming a common base for them.
712 def : ProcessorModel<"x86-64", SandyBridgeModel,
713 [FeatureMMX, FeatureSSE2, FeatureFXSR, Feature64Bit,
716 //===----------------------------------------------------------------------===//
717 // Register File Description
718 //===----------------------------------------------------------------------===//
720 include "X86RegisterInfo.td"
722 //===----------------------------------------------------------------------===//
723 // Instruction Descriptions
724 //===----------------------------------------------------------------------===//
726 include "X86InstrInfo.td"
728 def X86InstrInfo : InstrInfo;
730 //===----------------------------------------------------------------------===//
731 // Calling Conventions
732 //===----------------------------------------------------------------------===//
734 include "X86CallingConv.td"
737 //===----------------------------------------------------------------------===//
739 //===----------------------------------------------------------------------===//
741 def ATTAsmParserVariant : AsmParserVariant {
747 // Discard comments in assembly strings.
748 string CommentDelimiter = "#";
750 // Recognize hard coded registers.
751 string RegisterPrefix = "%";
754 def IntelAsmParserVariant : AsmParserVariant {
758 string Name = "intel";
760 // Discard comments in assembly strings.
761 string CommentDelimiter = ";";
763 // Recognize hard coded registers.
764 string RegisterPrefix = "";
767 //===----------------------------------------------------------------------===//
769 //===----------------------------------------------------------------------===//
771 // The X86 target supports two different syntaxes for emitting machine code.
772 // This is controlled by the -x86-asm-syntax={att|intel}
773 def ATTAsmWriter : AsmWriter {
774 string AsmWriterClassName = "ATTInstPrinter";
777 def IntelAsmWriter : AsmWriter {
778 string AsmWriterClassName = "IntelInstPrinter";
783 // Information about the instructions...
784 let InstructionSet = X86InstrInfo;
785 let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
786 let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];