lib/Target/X86/X86.td

   1 //===- X86.td - Target definition file for the Intel X86 arch ---*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file was developed by the LLVM research group and is distributed under
   6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is a target description file for the Intel i386 architecture, refered to
  11 // here as the "X86" architecture.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 // Get the target-independent interfaces which we are implementing...
  16 //
  17 include "../Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // X86 Subtarget features.
  21 //===----------------------------------------------------------------------===//
  22
  23 def FeatureMMX     : SubtargetFeature<"mmx","X86SSELevel", "MMX",
  24                                       "Enable MMX instructions">;
  25 def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
  26                                       "Enable SSE instructions",
  27                                       [FeatureMMX]>;
  28 def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
  29                                       "Enable SSE2 instructions",
  30                                       [FeatureSSE1]>;
  31 def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
  32                                       "Enable SSE3 instructions",
  33                                       [FeatureSSE2]>;
  34 def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
  35                                       "Enable SSSE3 instructions",
  36                                       [FeatureSSE3]>;
  37 def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
  38                                       "Enable 3DNow! instructions">;
  39 def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
  40                                       "Enable 3DNow! Athlon instructions",
  41                                       [Feature3DNow]>;
  42 def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
  43                                       "Support 64-bit instructions",
  44                                       [FeatureSSE2]>;
  45
  46 //===----------------------------------------------------------------------===//
  47 // X86 processors supported.
  48 //===----------------------------------------------------------------------===//
  49
  50 class Proc<string Name, list<SubtargetFeature> Features>
  51  : Processor<Name, NoItineraries, Features>;
  52
  53 def : Proc<"generic",         []>;
  54 def : Proc<"i386",            []>;
  55 def : Proc<"i486",            []>;
  56 def : Proc<"pentium",         []>;
  57 def : Proc<"pentium-mmx",     [FeatureMMX]>;
  58 def : Proc<"i686",            []>;
  59 def : Proc<"pentiumpro",      []>;
  60 def : Proc<"pentium2",        [FeatureMMX]>;
  61 def : Proc<"pentium3",        [FeatureSSE1]>;
  62 def : Proc<"pentium-m",       [FeatureSSE2]>;
  63 def : Proc<"pentium4",        [FeatureSSE2]>;
  64 def : Proc<"x86-64",          [Feature64Bit]>;
  65 def : Proc<"yonah",           [FeatureSSE3]>;
  66 def : Proc<"prescott",        [FeatureSSE3]>;
  67 def : Proc<"nocona",          [FeatureSSE3]>;
  68 def : Proc<"core2",           [FeatureSSSE3]>;
  69
  70 def : Proc<"k6",              [FeatureMMX]>;
  71 def : Proc<"k6-2",            [FeatureMMX,    Feature3DNow]>;
  72 def : Proc<"k6-3",            [FeatureMMX,    Feature3DNow]>;
  73 def : Proc<"athlon",          [FeatureMMX,    Feature3DNowA]>;
  74 def : Proc<"athlon-tbird",    [FeatureMMX,    Feature3DNowA]>;
  75 def : Proc<"athlon-4",        [FeatureSSE1,   Feature3DNowA]>;
  76 def : Proc<"athlon-xp",       [FeatureSSE1,   Feature3DNowA]>;
  77 def : Proc<"athlon-mp",       [FeatureSSE1,   Feature3DNowA]>;
  78 def : Proc<"k8",              [Feature3DNowA, Feature64Bit]>;
  79 def : Proc<"opteron",         [Feature3DNowA, Feature64Bit]>;
  80 def : Proc<"athlon64",        [Feature3DNowA, Feature64Bit]>;
  81 def : Proc<"athlon-fx",       [Feature3DNowA, Feature64Bit]>;
  82
  83 def : Proc<"winchip-c6",      [FeatureMMX]>;
  84 def : Proc<"winchip2",        [FeatureMMX, Feature3DNow]>;
  85 def : Proc<"c3",              [FeatureMMX, Feature3DNow]>;
  86 def : Proc<"c3-2",            [FeatureSSE1]>;
  87
  88 //===----------------------------------------------------------------------===//
  89 // Register File Description
  90 //===----------------------------------------------------------------------===//
  91
  92 include "X86RegisterInfo.td"
  93
  94 //===----------------------------------------------------------------------===//
  95 // Instruction Descriptions
  96 //===----------------------------------------------------------------------===//
  97
  98 include "X86InstrInfo.td"
  99
 100 def X86InstrInfo : InstrInfo {
 101
 102   // Define how we want to layout our TargetSpecific information field... This
 103   // should be kept up-to-date with the fields in the X86InstrInfo.h file.
 104   let TSFlagsFields = ["FormBits",
 105                        "hasOpSizePrefix",
 106                        "hasAdSizePrefix",
 107                        "Prefix",
 108                        "hasREX_WPrefix",
 109                        "ImmTypeBits",
 110                        "FPFormBits",
 111                        "Opcode"];
 112   let TSFlagsShifts = [0,
 113                        6,
 114                        7,
 115                        8,
 116                        12,
 117                        13,
 118                        16,
 119                        24];
 120 }
 121
 122 //===----------------------------------------------------------------------===//
 123 // Calling Conventions
 124 //===----------------------------------------------------------------------===//
 125
 126 include "X86CallingConv.td"
 127
 128
 129 //===----------------------------------------------------------------------===//
 130 // Assembly Printers
 131 //===----------------------------------------------------------------------===//
 132
 133 // The X86 target supports two different syntaxes for emitting machine code.
 134 // This is controlled by the -x86-asm-syntax={att|intel}
 135 def ATTAsmWriter : AsmWriter {
 136   string AsmWriterClassName  = "ATTAsmPrinter";
 137   int Variant = 0;
 138 }
 139 def IntelAsmWriter : AsmWriter {
 140   string AsmWriterClassName  = "IntelAsmPrinter";
 141   int Variant = 1;
 142 }
 143
 144
 145 def X86 : Target {
 146   // Information about the instructions...
 147   let InstructionSet = X86InstrInfo;
 148
 149   let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
 150 }