lib/Target/X86/X86.td

   1 //===- X86.td - Target definition file for the Intel X86 arch ---*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file was developed by the LLVM research group and is distributed under
   6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is a target description file for the Intel i386 architecture, refered to
  11 // here as the "X86" architecture.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 // Get the target-independent interfaces which we are implementing...
  16 //
  17 include "../Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // X86 Subtarget features.
  21 //
  22
  23 def Feature64Bit     : SubtargetFeature<"64bit", "Is64Bit", "true",
  24                                         "Enable 64-bit instructions">;
  25 def FeatureMMX       : SubtargetFeature<"mmx","X86SSELevel", "MMX",
  26                                         "Enable MMX instructions">;
  27 def FeatureSSE1      : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
  28                                         "Enable SSE instructions">;
  29 def FeatureSSE2      : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
  30                                         "Enable SSE2 instructions">;
  31 def FeatureSSE3      : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
  32                                         "Enable SSE3 instructions">;
  33 def Feature3DNow     : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
  34                                         "Enable 3DNow! instructions">;
  35 def Feature3DNowA    : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
  36                                         "Enable 3DNow! Athlon instructions">;
  37
  38 //===----------------------------------------------------------------------===//
  39 // X86 processors supported.
  40 //===----------------------------------------------------------------------===//
  41
  42 class Proc<string Name, list<SubtargetFeature> Features>
  43  : Processor<Name, NoItineraries, Features>;
  44
  45 def : Proc<"generic",         []>;
  46 def : Proc<"i386",            []>;
  47 def : Proc<"i486",            []>;
  48 def : Proc<"pentium",         []>;
  49 def : Proc<"pentium-mmx",     [FeatureMMX]>;
  50 def : Proc<"i686",            []>;
  51 def : Proc<"pentiumpro",      []>;
  52 def : Proc<"pentium2",        [FeatureMMX]>;
  53 def : Proc<"pentium3",        [FeatureMMX, FeatureSSE1]>;
  54 def : Proc<"pentium-m",       [FeatureMMX, FeatureSSE1, FeatureSSE2]>;
  55 def : Proc<"pentium4",        [FeatureMMX, FeatureSSE1, FeatureSSE2]>;
  56 def : Proc<"x86-64",          [FeatureMMX, FeatureSSE1, FeatureSSE2,
  57                                Feature64Bit]>;
  58 def : Proc<"yonah",           [FeatureMMX, FeatureSSE1, FeatureSSE2,
  59                                FeatureSSE3]>;
  60 def : Proc<"prescott",        [FeatureMMX, FeatureSSE1, FeatureSSE2,
  61                                FeatureSSE3]>;
  62 def : Proc<"nocona",          [FeatureMMX, FeatureSSE1, FeatureSSE2,
  63                                FeatureSSE3, Feature64Bit]>;
  64
  65 def : Proc<"k6",              [FeatureMMX]>;
  66 def : Proc<"k6-2",            [FeatureMMX, Feature3DNow]>;
  67 def : Proc<"k6-3",            [FeatureMMX, Feature3DNow]>;
  68 def : Proc<"athlon",          [FeatureMMX, Feature3DNow, Feature3DNowA]>;
  69 def : Proc<"athlon-tbird",    [FeatureMMX, Feature3DNow, Feature3DNowA]>;
  70 def : Proc<"athlon-4",        [FeatureMMX, FeatureSSE1, Feature3DNow,
  71                                Feature3DNowA]>;
  72 def : Proc<"athlon-xp",       [FeatureMMX, FeatureSSE1, Feature3DNow,
  73                                Feature3DNowA]>;
  74 def : Proc<"athlon-mp",       [FeatureMMX, FeatureSSE1, Feature3DNow,
  75                                Feature3DNowA]>;
  76 def : Proc<"k8",              [FeatureMMX, FeatureSSE1, FeatureSSE2,
  77                                Feature3DNow, Feature3DNowA, Feature64Bit]>;
  78 def : Proc<"opteron",         [FeatureMMX, FeatureSSE1, FeatureSSE2,
  79                                Feature3DNow, Feature3DNowA, Feature64Bit]>;
  80 def : Proc<"athlon64",        [FeatureMMX, FeatureSSE1, FeatureSSE2,
  81                                Feature3DNow, Feature3DNowA, Feature64Bit]>;
  82 def : Proc<"athlon-fx",       [FeatureMMX, FeatureSSE1, FeatureSSE2,
  83                                Feature3DNow, Feature3DNowA, Feature64Bit]>;
  84
  85 def : Proc<"winchip-c6",      [FeatureMMX]>;
  86 def : Proc<"winchip2",        [FeatureMMX, Feature3DNow]>;
  87 def : Proc<"c3",              [FeatureMMX, Feature3DNow]>;
  88 def : Proc<"c3-2",            [FeatureMMX, FeatureSSE1]>;
  89
  90 //===----------------------------------------------------------------------===//
  91 // Register File Description
  92 //===----------------------------------------------------------------------===//
  93
  94 include "X86RegisterInfo.td"
  95
  96 //===----------------------------------------------------------------------===//
  97 // Instruction Descriptions
  98 //===----------------------------------------------------------------------===//
  99
 100 include "X86InstrInfo.td"
 101
 102 def X86InstrInfo : InstrInfo {
 103
 104   // Define how we want to layout our TargetSpecific information field... This
 105   // should be kept up-to-date with the fields in the X86InstrInfo.h file.
 106   let TSFlagsFields = ["FormBits",
 107                        "hasOpSizePrefix",
 108                        "Prefix",
 109                        "ImmTypeBits",
 110                        "FPFormBits",
 111                        "Opcode"];
 112   let TSFlagsShifts = [0,
 113                        6,
 114                        7,
 115                        11,
 116                        13,
 117                        17];
 118 }
 119
 120 // The X86 target supports two different syntaxes for emitting machine code.
 121 // This is controlled by the -x86-asm-syntax={att|intel}
 122 def ATTAsmWriter : AsmWriter {
 123   string AsmWriterClassName  = "ATTAsmPrinter";
 124   int Variant = 0;
 125 }
 126 def IntelAsmWriter : AsmWriter {
 127   string AsmWriterClassName  = "IntelAsmPrinter";
 128   int Variant = 1;
 129 }
 130
 131
 132 def X86 : Target {
 133   // Specify the callee saved registers.
 134   let CalleeSavedRegisters = [ESI, EDI, EBX, EBP];
 135
 136   // Yes, pointers are 32-bits in size.
 137   let PointerType = i32;
 138
 139   // Information about the instructions...
 140   let InstructionSet = X86InstrInfo;
 141
 142   let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
 143 }