1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is a target description file for the Intel i386 architecture, referred
11 // to here as the "X86" architecture.
13 //===----------------------------------------------------------------------===//
15 // Get the target-independent interfaces which we are implementing...
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // X86 Subtarget state
23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
24 "64-bit mode (x86_64)">;
25 def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",
26 "32-bit mode (80386)">;
27 def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
28 "16-bit mode (i8086)">;
30 //===----------------------------------------------------------------------===//
31 // X86 Subtarget features
32 //===----------------------------------------------------------------------===//
34 def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true",
35 "Enable conditional move instructions">;
37 def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
38 "Support POPCNT instruction">;
41 def FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX",
42 "Enable MMX instructions">;
43 def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
44 "Enable SSE instructions",
45 // SSE codegen depends on cmovs, and all
46 // SSE1+ processors support them.
47 [FeatureMMX, FeatureCMOV]>;
48 def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
49 "Enable SSE2 instructions",
51 def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
52 "Enable SSE3 instructions",
54 def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
55 "Enable SSSE3 instructions",
57 def FeatureSSE41 : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
58 "Enable SSE 4.1 instructions",
60 def FeatureSSE42 : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
61 "Enable SSE 4.2 instructions",
63 def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
64 "Enable 3DNow! instructions",
66 def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
67 "Enable 3DNow! Athlon instructions",
69 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
70 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
71 // without disabling 64-bit mode.
72 def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true",
73 "Support 64-bit instructions",
75 def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
76 "64-bit with cmpxchg16b",
78 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
79 "Bit testing of memory is slow">;
80 def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
81 "SHLD instruction is slow">;
82 // FIXME: This is a 16-byte (SSE/AVX) feature; we should rename it to make that
83 // explicit. Also, it seems this would be the default state for most chips
84 // going forward, so it would probably be better to negate the logic and
85 // match the 32-byte "slow mem" feature below.
86 def FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem",
87 "IsUAMemFast", "true",
88 "Fast unaligned memory access">;
89 def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
90 "IsUAMem32Slow", "true",
91 "Slow unaligned 32-byte memory access">;
92 def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true",
93 "Support SSE 4a instructions",
96 def FeatureAVX : SubtargetFeature<"avx", "X86SSELevel", "AVX",
97 "Enable AVX instructions",
99 def FeatureAVX2 : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
100 "Enable AVX2 instructions",
102 def FeatureAVX512 : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
103 "Enable AVX-512 instructions",
105 def FeatureERI : SubtargetFeature<"avx512er", "HasERI", "true",
106 "Enable AVX-512 Exponential and Reciprocal Instructions",
108 def FeatureCDI : SubtargetFeature<"avx512cd", "HasCDI", "true",
109 "Enable AVX-512 Conflict Detection Instructions",
111 def FeaturePFI : SubtargetFeature<"avx512pf", "HasPFI", "true",
112 "Enable AVX-512 PreFetch Instructions",
114 def FeatureDQI : SubtargetFeature<"avx512dq", "HasDQI", "true",
115 "Enable AVX-512 Doubleword and Quadword Instructions",
117 def FeatureBWI : SubtargetFeature<"avx512bw", "HasBWI", "true",
118 "Enable AVX-512 Byte and Word Instructions",
120 def FeatureVLX : SubtargetFeature<"avx512vl", "HasVLX", "true",
121 "Enable AVX-512 Vector Length eXtensions",
123 def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
124 "Enable packed carry-less multiplication instructions",
126 def FeatureFMA : SubtargetFeature<"fma", "HasFMA", "true",
127 "Enable three-operand fused multiple-add",
129 def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true",
130 "Enable four-operand fused multiple-add",
131 [FeatureAVX, FeatureSSE4A]>;
132 def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true",
133 "Enable XOP instructions",
135 def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
136 "HasVectorUAMem", "true",
137 "Allow unaligned memory operands on vector/SIMD instructions">;
138 def FeatureAES : SubtargetFeature<"aes", "HasAES", "true",
139 "Enable AES instructions",
141 def FeatureTBM : SubtargetFeature<"tbm", "HasTBM", "true",
142 "Enable TBM instructions">;
143 def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true",
144 "Support MOVBE instruction">;
145 def FeatureRDRAND : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
146 "Support RDRAND instruction">;
147 def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true",
148 "Support 16-bit floating point conversion instructions",
150 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
151 "Support FS/GS Base instructions">;
152 def FeatureLZCNT : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
153 "Support LZCNT instruction">;
154 def FeatureBMI : SubtargetFeature<"bmi", "HasBMI", "true",
155 "Support BMI instructions">;
156 def FeatureBMI2 : SubtargetFeature<"bmi2", "HasBMI2", "true",
157 "Support BMI2 instructions">;
158 def FeatureRTM : SubtargetFeature<"rtm", "HasRTM", "true",
159 "Support RTM instructions">;
160 def FeatureHLE : SubtargetFeature<"hle", "HasHLE", "true",
162 def FeatureADX : SubtargetFeature<"adx", "HasADX", "true",
163 "Support ADX instructions">;
164 def FeatureSHA : SubtargetFeature<"sha", "HasSHA", "true",
165 "Enable SHA instructions",
167 def FeatureSGX : SubtargetFeature<"sgx", "HasSGX", "true",
168 "Support SGX instructions">;
169 def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
170 "Support PRFCHW instructions">;
171 def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true",
172 "Support RDSEED instruction">;
173 def FeatureSMAP : SubtargetFeature<"smap", "HasSMAP", "true",
174 "Support SMAP instructions">;
175 def FeatureLeaForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
176 "Use LEA for adjusting the stack pointer">;
177 def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
178 "HasSlowDivide32", "true",
179 "Use 8-bit divide for positive values less than 256">;
180 def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divw",
181 "HasSlowDivide64", "true",
182 "Use 16-bit divide for positive values less than 65536">;
183 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
184 "PadShortFunctions", "true",
185 "Pad short functions">;
186 def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect",
187 "CallRegIndirect", "true",
188 "Call register indirect">;
189 def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
190 "LEA instruction needs inputs at AG stage">;
191 def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
192 "LEA instruction with certain arguments is slow">;
193 def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
194 "INC and DEC instructions are slower than ADD and SUB">;
195 def FeatureUseSqrtEst : SubtargetFeature<"use-sqrt-est", "UseSqrtEst", "true",
196 "Use RSQRT* to optimize square root calculations">;
197 def FeatureUseRecipEst : SubtargetFeature<"use-recip-est", "UseReciprocalEst",
198 "true", "Use RCP* to optimize division calculations">;
200 //===----------------------------------------------------------------------===//
201 // X86 processors supported.
202 //===----------------------------------------------------------------------===//
204 include "X86Schedule.td"
206 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
207 "Intel Atom processors">;
208 def ProcIntelSLM : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM",
209 "Intel Silvermont processors">;
211 class Proc<string Name, list<SubtargetFeature> Features>
212 : ProcessorModel<Name, GenericModel, Features>;
214 def : Proc<"generic", []>;
215 def : Proc<"i386", []>;
216 def : Proc<"i486", []>;
217 def : Proc<"i586", []>;
218 def : Proc<"pentium", []>;
219 def : Proc<"pentium-mmx", [FeatureMMX]>;
220 def : Proc<"i686", []>;
221 def : Proc<"pentiumpro", [FeatureCMOV]>;
222 def : Proc<"pentium2", [FeatureMMX, FeatureCMOV]>;
223 def : Proc<"pentium3", [FeatureSSE1]>;
224 def : Proc<"pentium3m", [FeatureSSE1, FeatureSlowBTMem]>;
225 def : Proc<"pentium-m", [FeatureSSE2, FeatureSlowBTMem]>;
226 def : Proc<"pentium4", [FeatureSSE2]>;
227 def : Proc<"pentium4m", [FeatureSSE2, FeatureSlowBTMem]>;
230 def : ProcessorModel<"yonah", SandyBridgeModel,
231 [FeatureSSE3, FeatureSlowBTMem]>;
234 def : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>;
235 def : Proc<"nocona", [FeatureSSE3, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
237 // Intel Core 2 Solo/Duo.
238 def : ProcessorModel<"core2", SandyBridgeModel,
239 [FeatureSSSE3, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
240 def : ProcessorModel<"penryn", SandyBridgeModel,
241 [FeatureSSE41, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
244 class BonnellProc<string Name> : ProcessorModel<Name, AtomModel, [
253 FeatureCallRegIndirect,
255 FeaturePadShortFunctions
257 def : BonnellProc<"bonnell">;
258 def : BonnellProc<"atom">; // Pin the generic name to the baseline.
260 class SilvermontProc<string Name> : ProcessorModel<Name, SLMModel, [
269 FeatureCallRegIndirect,
276 def : SilvermontProc<"silvermont">;
277 def : SilvermontProc<"slm">; // Legacy alias.
279 // "Arrandale" along with corei3 and corei5
280 class NehalemProc<string Name, list<SubtargetFeature> AdditionalFeatures>
281 : ProcessorModel<Name, SandyBridgeModel, !listconcat([
288 AdditionalFeatures)>;
289 def : NehalemProc<"nehalem", []>;
290 def : NehalemProc<"corei7", [FeatureAES]>;
292 // Westmere is a similar machine to nehalem with some additional features.
293 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
294 class WestmereProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
303 def : WestmereProc<"westmere">;
305 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
306 // rather than a superset.
307 class SandyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
317 def : SandyBridgeProc<"sandybridge">;
318 def : SandyBridgeProc<"corei7-avx">; // Legacy alias.
320 class IvyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
333 def : IvyBridgeProc<"ivybridge">;
334 def : IvyBridgeProc<"core-avx-i">; // Legacy alias.
336 class HaswellProc<string Name> : ProcessorModel<Name, HaswellModel, [
356 def : HaswellProc<"haswell">;
357 def : HaswellProc<"core-avx2">; // Legacy alias.
359 class BroadwellProc<string Name> : ProcessorModel<Name, HaswellModel, [
382 def : BroadwellProc<"broadwell">;
384 // FIXME: define KNL model
385 class KnightsLandingProc<string Name> : ProcessorModel<Name, HaswellModel,
386 [FeatureAVX512, FeatureERI, FeatureCDI, FeaturePFI,
387 FeatureCMPXCHG16B, FeatureFastUAMem, FeaturePOPCNT,
388 FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C,
389 FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI,
390 FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE,
391 FeatureSlowIncDec, FeatureVectorUAMem]>;
392 def : KnightsLandingProc<"knl">;
394 // FIXME: define SKX model
395 class SkylakeProc<string Name> : ProcessorModel<Name, HaswellModel,
396 [FeatureAVX512, FeatureCDI,
397 FeatureDQI, FeatureBWI, FeatureVLX,
398 FeatureCMPXCHG16B, FeatureFastUAMem, FeaturePOPCNT,
399 FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C,
400 FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI,
401 FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE,
402 FeatureSlowIncDec, FeatureSGX, FeatureVectorUAMem]>;
403 def : SkylakeProc<"skylake">;
404 def : SkylakeProc<"skx">; // Legacy alias.
409 def : Proc<"k6", [FeatureMMX]>;
410 def : Proc<"k6-2", [Feature3DNow]>;
411 def : Proc<"k6-3", [Feature3DNow]>;
412 def : Proc<"athlon", [Feature3DNowA, FeatureSlowBTMem,
414 def : Proc<"athlon-tbird", [Feature3DNowA, FeatureSlowBTMem,
416 def : Proc<"athlon-4", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem,
418 def : Proc<"athlon-xp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem,
420 def : Proc<"athlon-mp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem,
422 def : Proc<"k8", [FeatureSSE2, Feature3DNowA, Feature64Bit,
423 FeatureSlowBTMem, FeatureSlowSHLD]>;
424 def : Proc<"opteron", [FeatureSSE2, Feature3DNowA, Feature64Bit,
425 FeatureSlowBTMem, FeatureSlowSHLD]>;
426 def : Proc<"athlon64", [FeatureSSE2, Feature3DNowA, Feature64Bit,
427 FeatureSlowBTMem, FeatureSlowSHLD]>;
428 def : Proc<"athlon-fx", [FeatureSSE2, Feature3DNowA, Feature64Bit,
429 FeatureSlowBTMem, FeatureSlowSHLD]>;
430 def : Proc<"k8-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
431 FeatureSlowBTMem, FeatureSlowSHLD]>;
432 def : Proc<"opteron-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
433 FeatureSlowBTMem, FeatureSlowSHLD]>;
434 def : Proc<"athlon64-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
435 FeatureSlowBTMem, FeatureSlowSHLD]>;
436 def : Proc<"amdfam10", [FeatureSSE4A,
437 Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
438 FeaturePOPCNT, FeatureSlowBTMem,
440 def : Proc<"barcelona", [FeatureSSE4A,
441 Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
442 FeaturePOPCNT, FeatureSlowBTMem,
445 def : Proc<"btver1", [FeatureSSSE3, FeatureSSE4A, FeatureCMPXCHG16B,
446 FeaturePRFCHW, FeatureLZCNT, FeaturePOPCNT,
450 def : ProcessorModel<"btver2", BtVer2Model,
451 [FeatureAVX, FeatureSSE4A, FeatureCMPXCHG16B,
452 FeaturePRFCHW, FeatureAES, FeaturePCLMUL,
453 FeatureBMI, FeatureF16C, FeatureMOVBE,
454 FeatureLZCNT, FeaturePOPCNT, FeatureFastUAMem,
455 FeatureSlowSHLD, FeatureUseSqrtEst, FeatureUseRecipEst]>;
457 // TODO: We should probably add 'FeatureFastUAMem' to all of the AMD chips.
460 def : Proc<"bdver1", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
461 FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
462 FeatureAVX, FeatureSSE4A, FeatureLZCNT,
463 FeaturePOPCNT, FeatureSlowSHLD]>;
465 def : Proc<"bdver2", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
466 FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
467 FeatureAVX, FeatureSSE4A, FeatureF16C,
468 FeatureLZCNT, FeaturePOPCNT, FeatureBMI,
469 FeatureTBM, FeatureFMA, FeatureSlowSHLD]>;
472 def : Proc<"bdver3", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
473 FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
474 FeatureAVX, FeatureSSE4A, FeatureF16C,
475 FeatureLZCNT, FeaturePOPCNT, FeatureBMI,
476 FeatureTBM, FeatureFMA, FeatureSlowSHLD,
480 def : Proc<"bdver4", [FeatureAVX2, FeatureXOP, FeatureFMA4,
481 FeatureCMPXCHG16B, FeatureAES, FeaturePRFCHW,
482 FeaturePCLMUL, FeatureF16C, FeatureLZCNT,
483 FeaturePOPCNT, FeatureBMI, FeatureBMI2,
484 FeatureTBM, FeatureFMA, FeatureSSE4A,
487 def : Proc<"geode", [Feature3DNowA]>;
489 def : Proc<"winchip-c6", [FeatureMMX]>;
490 def : Proc<"winchip2", [Feature3DNow]>;
491 def : Proc<"c3", [Feature3DNow]>;
492 def : Proc<"c3-2", [FeatureSSE1]>;
494 // We also provide a generic 64-bit specific x86 processor model which tries to
495 // be good for modern chips without enabling instruction set encodings past the
496 // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
497 // modern 64-bit x86 chip, and enables features that are generally beneficial.
499 // We currently use the Sandy Bridge model as the default scheduling model as
500 // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
501 // covers a huge swath of x86 processors. If there are specific scheduling
502 // knobs which need to be tuned differently for AMD chips, we might consider
503 // forming a common base for them.
504 def : ProcessorModel<"x86-64", SandyBridgeModel,
505 [FeatureSSE2, Feature64Bit, FeatureSlowBTMem,
508 //===----------------------------------------------------------------------===//
509 // Register File Description
510 //===----------------------------------------------------------------------===//
512 include "X86RegisterInfo.td"
514 //===----------------------------------------------------------------------===//
515 // Instruction Descriptions
516 //===----------------------------------------------------------------------===//
518 include "X86InstrInfo.td"
520 def X86InstrInfo : InstrInfo;
522 //===----------------------------------------------------------------------===//
523 // Calling Conventions
524 //===----------------------------------------------------------------------===//
526 include "X86CallingConv.td"
529 //===----------------------------------------------------------------------===//
531 //===----------------------------------------------------------------------===//
533 def ATTAsmParser : AsmParser {
534 string AsmParserClassName = "AsmParser";
537 def ATTAsmParserVariant : AsmParserVariant {
543 // Discard comments in assembly strings.
544 string CommentDelimiter = "#";
546 // Recognize hard coded registers.
547 string RegisterPrefix = "%";
550 def IntelAsmParserVariant : AsmParserVariant {
554 string Name = "intel";
556 // Discard comments in assembly strings.
557 string CommentDelimiter = ";";
559 // Recognize hard coded registers.
560 string RegisterPrefix = "";
563 //===----------------------------------------------------------------------===//
565 //===----------------------------------------------------------------------===//
567 // The X86 target supports two different syntaxes for emitting machine code.
568 // This is controlled by the -x86-asm-syntax={att|intel}
569 def ATTAsmWriter : AsmWriter {
570 string AsmWriterClassName = "ATTInstPrinter";
573 def IntelAsmWriter : AsmWriter {
574 string AsmWriterClassName = "IntelInstPrinter";
579 // Information about the instructions...
580 let InstructionSet = X86InstrInfo;
581 let AssemblyParsers = [ATTAsmParser];
582 let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
583 let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];