1 //===- X86.td - Target definition file for the Intel X86 ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is a target description file for the Intel i386 architecture, referred
11 // to here as the "X86" architecture.
13 //===----------------------------------------------------------------------===//
15 // Get the target-independent interfaces which we are implementing...
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // X86 Subtarget state.
23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
24 "64-bit mode (x86_64)">;
26 //===----------------------------------------------------------------------===//
27 // X86 Subtarget features.
28 //===----------------------------------------------------------------------===//
30 def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true",
31 "Enable conditional move instructions">;
33 def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
34 "Support POPCNT instruction">;
37 def FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX",
38 "Enable MMX instructions">;
39 def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
40 "Enable SSE instructions",
41 // SSE codegen depends on cmovs, and all
42 // SSE1+ processors support them.
43 [FeatureMMX, FeatureCMOV]>;
44 def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
45 "Enable SSE2 instructions",
47 def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
48 "Enable SSE3 instructions",
50 def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
51 "Enable SSSE3 instructions",
53 def FeatureSSE41 : SubtargetFeature<"sse41", "X86SSELevel", "SSE41",
54 "Enable SSE 4.1 instructions",
56 def FeatureSSE42 : SubtargetFeature<"sse42", "X86SSELevel", "SSE42",
57 "Enable SSE 4.2 instructions",
59 def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
60 "Enable 3DNow! instructions",
62 def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
63 "Enable 3DNow! Athlon instructions",
65 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
66 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
67 // without disabling 64-bit mode.
68 def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true",
69 "Support 64-bit instructions",
71 def FeatureCMPXCHG16B : SubtargetFeature<"cmpxchg16b", "HasCmpxchg16b", "true",
72 "64-bit with cmpxchg16b",
74 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
75 "Bit testing of memory is slow">;
76 def FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem",
77 "IsUAMemFast", "true",
78 "Fast unaligned memory access">;
79 def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true",
80 "Support SSE 4a instructions">;
82 def FeatureAVX : SubtargetFeature<"avx", "HasAVX", "true",
83 "Enable AVX instructions">;
84 def FeatureAVX2 : SubtargetFeature<"avx2", "HasAVX2", "true",
85 "Enable AVX2 instructions",
87 def FeatureCLMUL : SubtargetFeature<"clmul", "HasCLMUL", "true",
88 "Enable carry-less multiplication instructions">;
89 def FeatureFMA3 : SubtargetFeature<"fma3", "HasFMA3", "true",
90 "Enable three-operand fused multiple-add">;
91 def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true",
92 "Enable four-operand fused multiple-add">;
93 def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true",
94 "Enable XOP instructions">;
95 def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
96 "HasVectorUAMem", "true",
97 "Allow unaligned memory operands on vector/SIMD instructions">;
98 def FeatureAES : SubtargetFeature<"aes", "HasAES", "true",
99 "Enable AES instructions">;
100 def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true",
101 "Support MOVBE instruction">;
102 def FeatureRDRAND : SubtargetFeature<"rdrand", "HasRDRAND", "true",
103 "Support RDRAND instruction">;
104 def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true",
105 "Support 16-bit floating point conversion instructions">;
106 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
107 "Support FS/GS Base instructions">;
108 def FeatureLZCNT : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
109 "Support LZCNT instruction">;
110 def FeatureBMI : SubtargetFeature<"bmi", "HasBMI", "true",
111 "Support BMI instructions">;
112 def FeatureBMI2 : SubtargetFeature<"bmi2", "HasBMI2", "true",
113 "Support BMI2 instructions">;
115 //===----------------------------------------------------------------------===//
116 // X86 processors supported.
117 //===----------------------------------------------------------------------===//
119 class Proc<string Name, list<SubtargetFeature> Features>
120 : Processor<Name, NoItineraries, Features>;
122 def : Proc<"generic", []>;
123 def : Proc<"i386", []>;
124 def : Proc<"i486", []>;
125 def : Proc<"i586", []>;
126 def : Proc<"pentium", []>;
127 def : Proc<"pentium-mmx", [FeatureMMX]>;
128 def : Proc<"i686", []>;
129 def : Proc<"pentiumpro", [FeatureCMOV]>;
130 def : Proc<"pentium2", [FeatureMMX, FeatureCMOV]>;
131 def : Proc<"pentium3", [FeatureSSE1]>;
132 def : Proc<"pentium3m", [FeatureSSE1, FeatureSlowBTMem]>;
133 def : Proc<"pentium-m", [FeatureSSE2, FeatureSlowBTMem]>;
134 def : Proc<"pentium4", [FeatureSSE2]>;
135 def : Proc<"pentium4m", [FeatureSSE2, FeatureSlowBTMem]>;
136 def : Proc<"x86-64", [FeatureSSE2, Feature64Bit, FeatureSlowBTMem]>;
137 def : Proc<"yonah", [FeatureSSE3, FeatureSlowBTMem]>;
138 def : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>;
139 def : Proc<"nocona", [FeatureSSE3, FeatureCMPXCHG16B,
141 def : Proc<"core2", [FeatureSSSE3, FeatureCMPXCHG16B,
143 def : Proc<"penryn", [FeatureSSE41, FeatureCMPXCHG16B,
145 def : Proc<"atom", [FeatureSSE3, FeatureCMPXCHG16B, FeatureMOVBE,
147 // "Arrandale" along with corei3 and corei5
148 def : Proc<"corei7", [FeatureSSE42, FeatureCMPXCHG16B,
149 FeatureSlowBTMem, FeatureFastUAMem, FeatureAES]>;
150 def : Proc<"nehalem", [FeatureSSE42, FeatureCMPXCHG16B,
151 FeatureSlowBTMem, FeatureFastUAMem]>;
152 // Westmere is a similar machine to nehalem with some additional features.
153 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
154 def : Proc<"westmere", [FeatureSSE42, FeatureCMPXCHG16B,
155 FeatureSlowBTMem, FeatureFastUAMem, FeatureAES,
158 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
159 // rather than a superset.
160 // FIXME: Disabling AVX for now since it's not ready.
161 def : Proc<"corei7-avx", [FeatureSSE42, FeatureCMPXCHG16B,
162 FeatureAES, FeatureCLMUL]>;
164 def : Proc<"core-avx-i", [FeatureSSE42, FeatureCMPXCHG16B,
165 FeatureAES, FeatureCLMUL,
166 FeatureRDRAND, FeatureF16C, FeatureFSGSBase]>;
169 // FIXME: Disabling AVX/AVX2 for now since it's not ready.
170 def : Proc<"core-avx2", [FeatureSSE42, FeatureCMPXCHG16B, FeatureAES,
171 FeatureCLMUL, FeatureRDRAND, FeatureF16C,
172 FeatureFSGSBase, FeatureFMA3, FeatureMOVBE,
173 FeatureLZCNT, FeatureBMI, FeatureBMI2]>;
175 def : Proc<"k6", [FeatureMMX]>;
176 def : Proc<"k6-2", [Feature3DNow]>;
177 def : Proc<"k6-3", [Feature3DNow]>;
178 def : Proc<"athlon", [Feature3DNowA, FeatureSlowBTMem]>;
179 def : Proc<"athlon-tbird", [Feature3DNowA, FeatureSlowBTMem]>;
180 def : Proc<"athlon-4", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
181 def : Proc<"athlon-xp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
182 def : Proc<"athlon-mp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
183 def : Proc<"k8", [FeatureSSE2, Feature3DNowA, Feature64Bit,
185 def : Proc<"opteron", [FeatureSSE2, Feature3DNowA, Feature64Bit,
187 def : Proc<"athlon64", [FeatureSSE2, Feature3DNowA, Feature64Bit,
189 def : Proc<"athlon-fx", [FeatureSSE2, Feature3DNowA, Feature64Bit,
191 def : Proc<"k8-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
193 def : Proc<"opteron-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
195 def : Proc<"athlon64-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
197 def : Proc<"amdfam10", [FeatureSSE3, FeatureSSE4A,
198 Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
200 // FIXME: Disabling AVX for now since it's not ready.
201 def : Proc<"bdver1", [FeatureSSE42, FeatureSSE4A, FeatureCMPXCHG16B,
202 FeatureAES, FeatureCLMUL, FeatureFMA4,
203 FeatureXOP, FeatureLZCNT]>;
204 def : Proc<"bdver2", [FeatureSSE42, FeatureSSE4A, FeatureCMPXCHG16B,
205 FeatureAES, FeatureCLMUL, FeatureFMA4,
206 FeatureXOP, FeatureF16C, FeatureLZCNT,
209 def : Proc<"winchip-c6", [FeatureMMX]>;
210 def : Proc<"winchip2", [Feature3DNow]>;
211 def : Proc<"c3", [Feature3DNow]>;
212 def : Proc<"c3-2", [FeatureSSE1]>;
214 //===----------------------------------------------------------------------===//
215 // Register File Description
216 //===----------------------------------------------------------------------===//
218 include "X86RegisterInfo.td"
220 //===----------------------------------------------------------------------===//
221 // Instruction Descriptions
222 //===----------------------------------------------------------------------===//
224 include "X86InstrInfo.td"
226 def X86InstrInfo : InstrInfo;
228 //===----------------------------------------------------------------------===//
229 // Calling Conventions
230 //===----------------------------------------------------------------------===//
232 include "X86CallingConv.td"
235 //===----------------------------------------------------------------------===//
237 //===----------------------------------------------------------------------===//
239 // Currently the X86 assembly parser only supports ATT syntax.
240 def ATTAsmParser : AsmParser {
241 string AsmParserClassName = "ATTAsmParser";
244 // Discard comments in assembly strings.
245 string CommentDelimiter = "#";
247 // Recognize hard coded registers.
248 string RegisterPrefix = "%";
251 //===----------------------------------------------------------------------===//
253 //===----------------------------------------------------------------------===//
255 // The X86 target supports two different syntaxes for emitting machine code.
256 // This is controlled by the -x86-asm-syntax={att|intel}
257 def ATTAsmWriter : AsmWriter {
258 string AsmWriterClassName = "ATTInstPrinter";
260 bit isMCAsmWriter = 1;
262 def IntelAsmWriter : AsmWriter {
263 string AsmWriterClassName = "IntelInstPrinter";
265 bit isMCAsmWriter = 1;
269 // Information about the instructions...
270 let InstructionSet = X86InstrInfo;
272 let AssemblyParsers = [ATTAsmParser];
274 let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];