1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is a target description file for the Intel i386 architecture, referred
11 // to here as the "X86" architecture.
13 //===----------------------------------------------------------------------===//
15 // Get the target-independent interfaces which we are implementing...
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // X86 Subtarget state
23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
24 "64-bit mode (x86_64)">;
25 def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",
26 "32-bit mode (80386)">;
27 def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
28 "16-bit mode (i8086)">;
30 //===----------------------------------------------------------------------===//
31 // X86 Subtarget features
32 //===----------------------------------------------------------------------===//
34 def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true",
35 "Enable conditional move instructions">;
37 def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
38 "Support POPCNT instruction">;
41 def FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX",
42 "Enable MMX instructions">;
43 def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
44 "Enable SSE instructions",
45 // SSE codegen depends on cmovs, and all
46 // SSE1+ processors support them.
47 [FeatureMMX, FeatureCMOV]>;
48 def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
49 "Enable SSE2 instructions",
51 def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
52 "Enable SSE3 instructions",
54 def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
55 "Enable SSSE3 instructions",
57 def FeatureSSE41 : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
58 "Enable SSE 4.1 instructions",
60 def FeatureSSE42 : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
61 "Enable SSE 4.2 instructions",
63 def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
64 "Enable 3DNow! instructions",
66 def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
67 "Enable 3DNow! Athlon instructions",
69 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
70 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
71 // without disabling 64-bit mode.
72 def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true",
73 "Support 64-bit instructions",
75 def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
76 "64-bit with cmpxchg16b",
78 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
79 "Bit testing of memory is slow">;
80 def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
81 "SHLD instruction is slow">;
82 def FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem",
83 "IsUAMemFast", "true",
84 "Fast unaligned memory access">;
85 def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true",
86 "Support SSE 4a instructions",
89 def FeatureAVX : SubtargetFeature<"avx", "X86SSELevel", "AVX",
90 "Enable AVX instructions",
92 def FeatureAVX2 : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
93 "Enable AVX2 instructions",
95 def FeatureAVX512 : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
96 "Enable AVX-512 instructions",
98 def FeatureERI : SubtargetFeature<"avx512er", "HasERI", "true",
99 "Enable AVX-512 Exponential and Reciprocal Instructions",
101 def FeatureCDI : SubtargetFeature<"avx512cd", "HasCDI", "true",
102 "Enable AVX-512 Conflict Detection Instructions",
104 def FeaturePFI : SubtargetFeature<"avx512pf", "HasPFI", "true",
105 "Enable AVX-512 PreFetch Instructions",
107 def FeatureDQI : SubtargetFeature<"avx512dq", "HasDQI", "true",
108 "Enable AVX-512 Doubleword and Quadword Instructions",
110 def FeatureBWI : SubtargetFeature<"avx512bw", "HasBWI", "true",
111 "Enable AVX-512 Byte and Word Instructions",
113 def FeatureVLX : SubtargetFeature<"avx512vl", "HasVLX", "true",
114 "Enable AVX-512 Vector Length eXtensions",
116 def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
117 "Enable packed carry-less multiplication instructions",
119 def FeatureFMA : SubtargetFeature<"fma", "HasFMA", "true",
120 "Enable three-operand fused multiple-add",
122 def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true",
123 "Enable four-operand fused multiple-add",
124 [FeatureAVX, FeatureSSE4A]>;
125 def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true",
126 "Enable XOP instructions",
128 def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
129 "HasVectorUAMem", "true",
130 "Allow unaligned memory operands on vector/SIMD instructions">;
131 def FeatureAES : SubtargetFeature<"aes", "HasAES", "true",
132 "Enable AES instructions",
134 def FeatureTBM : SubtargetFeature<"tbm", "HasTBM", "true",
135 "Enable TBM instructions">;
136 def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true",
137 "Support MOVBE instruction">;
138 def FeatureRDRAND : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
139 "Support RDRAND instruction">;
140 def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true",
141 "Support 16-bit floating point conversion instructions",
143 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
144 "Support FS/GS Base instructions">;
145 def FeatureLZCNT : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
146 "Support LZCNT instruction">;
147 def FeatureBMI : SubtargetFeature<"bmi", "HasBMI", "true",
148 "Support BMI instructions">;
149 def FeatureBMI2 : SubtargetFeature<"bmi2", "HasBMI2", "true",
150 "Support BMI2 instructions">;
151 def FeatureRTM : SubtargetFeature<"rtm", "HasRTM", "true",
152 "Support RTM instructions">;
153 def FeatureHLE : SubtargetFeature<"hle", "HasHLE", "true",
155 def FeatureADX : SubtargetFeature<"adx", "HasADX", "true",
156 "Support ADX instructions">;
157 def FeatureSHA : SubtargetFeature<"sha", "HasSHA", "true",
158 "Enable SHA instructions",
160 def FeatureSGX : SubtargetFeature<"sgx", "HasSGX", "true",
161 "Support SGX instructions">;
162 def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
163 "Support PRFCHW instructions">;
164 def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true",
165 "Support RDSEED instruction">;
166 def FeatureSMAP : SubtargetFeature<"smap", "HasSMAP", "true",
167 "Support SMAP instructions">;
168 def FeatureLeaForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
169 "Use LEA for adjusting the stack pointer">;
170 def FeatureSlowDivide : SubtargetFeature<"idiv-to-divb",
171 "HasSlowDivide", "true",
172 "Use small divide for positive values less than 256">;
173 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
174 "PadShortFunctions", "true",
175 "Pad short functions">;
176 def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect",
177 "CallRegIndirect", "true",
178 "Call register indirect">;
179 def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
180 "LEA instruction needs inputs at AG stage">;
181 def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
182 "LEA instruction with certain arguments is slow">;
183 def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
184 "INC and DEC instructions are slower than ADD and SUB">;
186 //===----------------------------------------------------------------------===//
187 // X86 processors supported.
188 //===----------------------------------------------------------------------===//
190 include "X86Schedule.td"
192 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
193 "Intel Atom processors">;
194 def ProcIntelSLM : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM",
195 "Intel Silvermont processors">;
197 class Proc<string Name, list<SubtargetFeature> Features>
198 : ProcessorModel<Name, GenericModel, Features>;
200 def : Proc<"generic", []>;
201 def : Proc<"i386", []>;
202 def : Proc<"i486", []>;
203 def : Proc<"i586", []>;
204 def : Proc<"pentium", []>;
205 def : Proc<"pentium-mmx", [FeatureMMX]>;
206 def : Proc<"i686", []>;
207 def : Proc<"pentiumpro", [FeatureCMOV]>;
208 def : Proc<"pentium2", [FeatureMMX, FeatureCMOV]>;
209 def : Proc<"pentium3", [FeatureSSE1]>;
210 def : Proc<"pentium3m", [FeatureSSE1, FeatureSlowBTMem]>;
211 def : Proc<"pentium-m", [FeatureSSE2, FeatureSlowBTMem]>;
212 def : Proc<"pentium4", [FeatureSSE2]>;
213 def : Proc<"pentium4m", [FeatureSSE2, FeatureSlowBTMem]>;
216 def : ProcessorModel<"yonah", SandyBridgeModel,
217 [FeatureSSE3, FeatureSlowBTMem]>;
220 def : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>;
221 def : Proc<"nocona", [FeatureSSE3, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
223 // Intel Core 2 Solo/Duo.
224 def : ProcessorModel<"core2", SandyBridgeModel,
225 [FeatureSSSE3, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
226 def : ProcessorModel<"penryn", SandyBridgeModel,
227 [FeatureSSE41, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
230 def : ProcessorModel<"atom", AtomModel,
231 [ProcIntelAtom, FeatureSSSE3, FeatureCMPXCHG16B,
232 FeatureMOVBE, FeatureSlowBTMem, FeatureLeaForSP,
234 FeatureCallRegIndirect,
236 FeaturePadShortFunctions]>;
239 def : ProcessorModel<"slm", SLMModel, [ProcIntelSLM,
240 FeatureSSE42, FeatureCMPXCHG16B,
241 FeatureMOVBE, FeaturePOPCNT,
242 FeaturePCLMUL, FeatureAES,
243 FeatureCallRegIndirect,
245 FeatureSlowLEA, FeatureSlowIncDec,
246 FeatureSlowBTMem, FeatureFastUAMem]>;
247 // "Arrandale" along with corei3 and corei5
248 def : ProcessorModel<"corei7", SandyBridgeModel,
249 [FeatureSSE42, FeatureCMPXCHG16B, FeatureSlowBTMem,
250 FeatureFastUAMem, FeaturePOPCNT, FeatureAES]>;
252 def : ProcessorModel<"nehalem", SandyBridgeModel,
253 [FeatureSSE42, FeatureCMPXCHG16B, FeatureSlowBTMem,
254 FeatureFastUAMem, FeaturePOPCNT]>;
255 // Westmere is a similar machine to nehalem with some additional features.
256 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
257 def : ProcessorModel<"westmere", SandyBridgeModel,
258 [FeatureSSE42, FeatureCMPXCHG16B, FeatureSlowBTMem,
259 FeatureFastUAMem, FeaturePOPCNT, FeatureAES,
262 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
263 // rather than a superset.
264 def : ProcessorModel<"corei7-avx", SandyBridgeModel,
265 [FeatureAVX, FeatureCMPXCHG16B, FeatureFastUAMem,
266 FeaturePOPCNT, FeatureAES, FeaturePCLMUL]>;
268 def : ProcessorModel<"core-avx-i", SandyBridgeModel,
269 [FeatureAVX, FeatureCMPXCHG16B, FeatureFastUAMem,
270 FeaturePOPCNT, FeatureAES, FeaturePCLMUL, FeatureRDRAND,
271 FeatureF16C, FeatureFSGSBase]>;
274 def : ProcessorModel<"core-avx2", HaswellModel,
275 [FeatureAVX2, FeatureCMPXCHG16B, FeatureFastUAMem,
276 FeaturePOPCNT, FeatureAES, FeaturePCLMUL, FeatureRDRAND,
277 FeatureF16C, FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT,
278 FeatureBMI, FeatureBMI2, FeatureFMA, FeatureRTM,
282 def : ProcessorModel<"broadwell", HaswellModel,
283 [FeatureAVX2, FeatureCMPXCHG16B, FeatureFastUAMem,
284 FeaturePOPCNT, FeatureAES, FeaturePCLMUL, FeatureRDRAND,
285 FeatureF16C, FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT,
286 FeatureBMI, FeatureBMI2, FeatureFMA, FeatureRTM,
287 FeatureHLE, FeatureADX, FeatureRDSEED, FeatureSMAP]>;
289 // FIXME: define KNL model
290 def : ProcessorModel<"knl", HaswellModel,
291 [FeatureAVX512, FeatureERI, FeatureCDI, FeaturePFI,
292 FeatureCMPXCHG16B, FeatureFastUAMem, FeaturePOPCNT,
293 FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C,
294 FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI,
295 FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE,
299 // FIXME: define SKX model
300 def : ProcessorModel<"skx", HaswellModel,
301 [FeatureAVX512, FeatureCDI,
302 FeatureDQI, FeatureBWI, FeatureVLX,
303 FeatureCMPXCHG16B, FeatureFastUAMem, FeaturePOPCNT,
304 FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C,
305 FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI,
306 FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE,
307 FeatureSlowIncDec, FeatureSGX]>;
309 def : Proc<"k6", [FeatureMMX]>;
310 def : Proc<"k6-2", [Feature3DNow]>;
311 def : Proc<"k6-3", [Feature3DNow]>;
312 def : Proc<"athlon", [Feature3DNowA, FeatureSlowBTMem,
314 def : Proc<"athlon-tbird", [Feature3DNowA, FeatureSlowBTMem,
316 def : Proc<"athlon-4", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem,
318 def : Proc<"athlon-xp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem,
320 def : Proc<"athlon-mp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem,
322 def : Proc<"k8", [FeatureSSE2, Feature3DNowA, Feature64Bit,
323 FeatureSlowBTMem, FeatureSlowSHLD]>;
324 def : Proc<"opteron", [FeatureSSE2, Feature3DNowA, Feature64Bit,
325 FeatureSlowBTMem, FeatureSlowSHLD]>;
326 def : Proc<"athlon64", [FeatureSSE2, Feature3DNowA, Feature64Bit,
327 FeatureSlowBTMem, FeatureSlowSHLD]>;
328 def : Proc<"athlon-fx", [FeatureSSE2, Feature3DNowA, Feature64Bit,
329 FeatureSlowBTMem, FeatureSlowSHLD]>;
330 def : Proc<"k8-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
331 FeatureSlowBTMem, FeatureSlowSHLD]>;
332 def : Proc<"opteron-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
333 FeatureSlowBTMem, FeatureSlowSHLD]>;
334 def : Proc<"athlon64-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
335 FeatureSlowBTMem, FeatureSlowSHLD]>;
336 def : Proc<"amdfam10", [FeatureSSE4A,
337 Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
338 FeaturePOPCNT, FeatureSlowBTMem,
341 def : Proc<"btver1", [FeatureSSSE3, FeatureSSE4A, FeatureCMPXCHG16B,
342 FeaturePRFCHW, FeatureLZCNT, FeaturePOPCNT,
346 def : ProcessorModel<"btver2", BtVer2Model,
347 [FeatureAVX, FeatureSSE4A, FeatureCMPXCHG16B,
348 FeaturePRFCHW, FeatureAES, FeaturePCLMUL,
349 FeatureBMI, FeatureF16C, FeatureMOVBE,
350 FeatureLZCNT, FeaturePOPCNT, FeatureSlowSHLD]>;
353 def : Proc<"bdver1", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
354 FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
355 FeatureLZCNT, FeaturePOPCNT, FeatureSlowSHLD]>;
357 def : Proc<"bdver2", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
358 FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
359 FeatureF16C, FeatureLZCNT,
360 FeaturePOPCNT, FeatureBMI, FeatureTBM,
361 FeatureFMA, FeatureSlowSHLD]>;
364 def : Proc<"bdver3", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
365 FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
366 FeatureF16C, FeatureLZCNT,
367 FeaturePOPCNT, FeatureBMI, FeatureTBM,
368 FeatureFMA, FeatureFSGSBase]>;
371 def : Proc<"bdver4", [FeatureAVX2, FeatureXOP, FeatureFMA4,
372 FeatureCMPXCHG16B, FeatureAES, FeaturePRFCHW,
373 FeaturePCLMUL, FeatureF16C, FeatureLZCNT,
374 FeaturePOPCNT, FeatureBMI, FeatureBMI2,
375 FeatureTBM, FeatureFMA, FeatureFSGSBase]>;
377 def : Proc<"geode", [Feature3DNowA]>;
379 def : Proc<"winchip-c6", [FeatureMMX]>;
380 def : Proc<"winchip2", [Feature3DNow]>;
381 def : Proc<"c3", [Feature3DNow]>;
382 def : Proc<"c3-2", [FeatureSSE1]>;
384 // We also provide a generic 64-bit specific x86 processor model which tries to
385 // be good for modern chips without enabling instruction set encodings past the
386 // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
387 // modern 64-bit x86 chip, and enables features that are generally beneficial.
389 // We currently use the Sandy Bridge model as the default scheduling model as
390 // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
391 // covers a huge swath of x86 processors. If there are specific scheduling
392 // knobs which need to be tuned differently for AMD chips, we might consider
393 // forming a common base for them.
394 def : ProcessorModel<"x86-64", SandyBridgeModel,
395 [FeatureSSE2, Feature64Bit, FeatureSlowBTMem,
398 //===----------------------------------------------------------------------===//
399 // Register File Description
400 //===----------------------------------------------------------------------===//
402 include "X86RegisterInfo.td"
404 //===----------------------------------------------------------------------===//
405 // Instruction Descriptions
406 //===----------------------------------------------------------------------===//
408 include "X86InstrInfo.td"
410 def X86InstrInfo : InstrInfo;
412 //===----------------------------------------------------------------------===//
413 // Calling Conventions
414 //===----------------------------------------------------------------------===//
416 include "X86CallingConv.td"
419 //===----------------------------------------------------------------------===//
421 //===----------------------------------------------------------------------===//
423 def ATTAsmParser : AsmParser {
424 string AsmParserClassName = "AsmParser";
427 def ATTAsmParserVariant : AsmParserVariant {
433 // Discard comments in assembly strings.
434 string CommentDelimiter = "#";
436 // Recognize hard coded registers.
437 string RegisterPrefix = "%";
440 def IntelAsmParserVariant : AsmParserVariant {
444 string Name = "intel";
446 // Discard comments in assembly strings.
447 string CommentDelimiter = ";";
449 // Recognize hard coded registers.
450 string RegisterPrefix = "";
453 //===----------------------------------------------------------------------===//
455 //===----------------------------------------------------------------------===//
457 // The X86 target supports two different syntaxes for emitting machine code.
458 // This is controlled by the -x86-asm-syntax={att|intel}
459 def ATTAsmWriter : AsmWriter {
460 string AsmWriterClassName = "ATTInstPrinter";
463 def IntelAsmWriter : AsmWriter {
464 string AsmWriterClassName = "IntelInstPrinter";
469 // Information about the instructions...
470 let InstructionSet = X86InstrInfo;
471 let AssemblyParsers = [ATTAsmParser];
472 let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
473 let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];