1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is a target description file for the Intel i386 architecture, referred
11 // to here as the "X86" architecture.
13 //===----------------------------------------------------------------------===//
15 // Get the target-independent interfaces which we are implementing...
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // X86 Subtarget state
23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
24 "64-bit mode (x86_64)">;
25 def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",
26 "32-bit mode (80386)">;
27 def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
28 "16-bit mode (i8086)">;
30 //===----------------------------------------------------------------------===//
31 // X86 Subtarget features
32 //===----------------------------------------------------------------------===//
34 def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true",
35 "Enable conditional move instructions">;
37 def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
38 "Support POPCNT instruction">;
41 def FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX",
42 "Enable MMX instructions">;
43 def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
44 "Enable SSE instructions",
45 // SSE codegen depends on cmovs, and all
46 // SSE1+ processors support them.
47 [FeatureMMX, FeatureCMOV]>;
48 def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
49 "Enable SSE2 instructions",
51 def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
52 "Enable SSE3 instructions",
54 def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
55 "Enable SSSE3 instructions",
57 def FeatureSSE41 : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
58 "Enable SSE 4.1 instructions",
60 def FeatureSSE42 : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
61 "Enable SSE 4.2 instructions",
63 def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
64 "Enable 3DNow! instructions",
66 def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
67 "Enable 3DNow! Athlon instructions",
69 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
70 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
71 // without disabling 64-bit mode.
72 def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true",
73 "Support 64-bit instructions",
75 def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
76 "64-bit with cmpxchg16b",
78 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
79 "Bit testing of memory is slow">;
80 def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
81 "SHLD instruction is slow">;
82 def FeatureSlowUAMem : SubtargetFeature<"slow-unaligned-mem-under-32",
83 "IsUAMemUnder32Slow", "true",
84 "Slow unaligned 16-byte-or-less memory access">;
85 def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
86 "IsUAMem32Slow", "true",
87 "Slow unaligned 32-byte memory access">;
88 def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true",
89 "Support SSE 4a instructions",
92 def FeatureAVX : SubtargetFeature<"avx", "X86SSELevel", "AVX",
93 "Enable AVX instructions",
95 def FeatureAVX2 : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
96 "Enable AVX2 instructions",
98 def FeatureAVX512 : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
99 "Enable AVX-512 instructions",
101 def FeatureERI : SubtargetFeature<"avx512er", "HasERI", "true",
102 "Enable AVX-512 Exponential and Reciprocal Instructions",
104 def FeatureCDI : SubtargetFeature<"avx512cd", "HasCDI", "true",
105 "Enable AVX-512 Conflict Detection Instructions",
107 def FeaturePFI : SubtargetFeature<"avx512pf", "HasPFI", "true",
108 "Enable AVX-512 PreFetch Instructions",
110 def FeatureDQI : SubtargetFeature<"avx512dq", "HasDQI", "true",
111 "Enable AVX-512 Doubleword and Quadword Instructions",
113 def FeatureBWI : SubtargetFeature<"avx512bw", "HasBWI", "true",
114 "Enable AVX-512 Byte and Word Instructions",
116 def FeatureVLX : SubtargetFeature<"avx512vl", "HasVLX", "true",
117 "Enable AVX-512 Vector Length eXtensions",
119 def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
120 "Enable packed carry-less multiplication instructions",
122 def FeatureFMA : SubtargetFeature<"fma", "HasFMA", "true",
123 "Enable three-operand fused multiple-add",
125 def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true",
126 "Enable four-operand fused multiple-add",
127 [FeatureAVX, FeatureSSE4A]>;
128 def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true",
129 "Enable XOP instructions",
131 def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem",
132 "HasSSEUnalignedMem", "true",
133 "Allow unaligned memory operands with SSE instructions">;
134 def FeatureAES : SubtargetFeature<"aes", "HasAES", "true",
135 "Enable AES instructions",
137 def FeatureTBM : SubtargetFeature<"tbm", "HasTBM", "true",
138 "Enable TBM instructions">;
139 def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true",
140 "Support MOVBE instruction">;
141 def FeatureRDRAND : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
142 "Support RDRAND instruction">;
143 def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true",
144 "Support 16-bit floating point conversion instructions",
146 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
147 "Support FS/GS Base instructions">;
148 def FeatureLZCNT : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
149 "Support LZCNT instruction">;
150 def FeatureBMI : SubtargetFeature<"bmi", "HasBMI", "true",
151 "Support BMI instructions">;
152 def FeatureBMI2 : SubtargetFeature<"bmi2", "HasBMI2", "true",
153 "Support BMI2 instructions">;
154 def FeatureRTM : SubtargetFeature<"rtm", "HasRTM", "true",
155 "Support RTM instructions">;
156 def FeatureHLE : SubtargetFeature<"hle", "HasHLE", "true",
158 def FeatureADX : SubtargetFeature<"adx", "HasADX", "true",
159 "Support ADX instructions">;
160 def FeatureSHA : SubtargetFeature<"sha", "HasSHA", "true",
161 "Enable SHA instructions",
163 def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
164 "Support PRFCHW instructions">;
165 def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true",
166 "Support RDSEED instruction">;
167 def FeatureMPX : SubtargetFeature<"mpx", "HasMPX", "true",
168 "Support MPX instructions">;
169 def FeatureLeaForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
170 "Use LEA for adjusting the stack pointer">;
171 def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
172 "HasSlowDivide32", "true",
173 "Use 8-bit divide for positive values less than 256">;
174 def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divw",
175 "HasSlowDivide64", "true",
176 "Use 16-bit divide for positive values less than 65536">;
177 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
178 "PadShortFunctions", "true",
179 "Pad short functions">;
180 // TODO: This feature ought to be renamed.
181 // What it really refers to are CPUs for which certain instructions
182 // (which ones besides the example below?) are microcoded.
183 // The best examples of this are the memory forms of CALL and PUSH
184 // instructions, which should be avoided in favor of a MOV + register CALL/PUSH.
185 def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect",
186 "CallRegIndirect", "true",
187 "Call register indirect">;
188 def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
189 "LEA instruction needs inputs at AG stage">;
190 def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
191 "LEA instruction with certain arguments is slow">;
192 def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
193 "INC and DEC instructions are slower than ADD and SUB">;
195 : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
196 "Use software floating point features.">;
198 //===----------------------------------------------------------------------===//
199 // X86 processors supported.
200 //===----------------------------------------------------------------------===//
202 include "X86Schedule.td"
204 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
205 "Intel Atom processors">;
206 def ProcIntelSLM : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM",
207 "Intel Silvermont processors">;
209 class Proc<string Name, list<SubtargetFeature> Features>
210 : ProcessorModel<Name, GenericModel, Features>;
212 def : Proc<"generic", [FeatureSlowUAMem]>;
213 def : Proc<"i386", [FeatureSlowUAMem]>;
214 def : Proc<"i486", [FeatureSlowUAMem]>;
215 def : Proc<"i586", [FeatureSlowUAMem]>;
216 def : Proc<"pentium", [FeatureSlowUAMem]>;
217 def : Proc<"pentium-mmx", [FeatureSlowUAMem, FeatureMMX]>;
218 def : Proc<"i686", [FeatureSlowUAMem]>;
219 def : Proc<"pentiumpro", [FeatureSlowUAMem, FeatureCMOV]>;
220 def : Proc<"pentium2", [FeatureSlowUAMem, FeatureMMX, FeatureCMOV]>;
221 def : Proc<"pentium3", [FeatureSlowUAMem, FeatureSSE1]>;
222 def : Proc<"pentium3m", [FeatureSlowUAMem, FeatureSSE1, FeatureSlowBTMem]>;
223 def : Proc<"pentium-m", [FeatureSlowUAMem, FeatureSSE2, FeatureSlowBTMem]>;
224 def : Proc<"pentium4", [FeatureSlowUAMem, FeatureSSE2]>;
225 def : Proc<"pentium4m", [FeatureSlowUAMem, FeatureSSE2, FeatureSlowBTMem]>;
228 def : ProcessorModel<"yonah", SandyBridgeModel,
229 [FeatureSlowUAMem, FeatureSSE3, FeatureSlowBTMem]>;
232 def : Proc<"prescott", [FeatureSlowUAMem, FeatureSSE3, FeatureSlowBTMem]>;
233 def : Proc<"nocona", [FeatureSlowUAMem, FeatureSSE3, FeatureCMPXCHG16B,
236 // Intel Core 2 Solo/Duo.
237 def : ProcessorModel<"core2", SandyBridgeModel,
238 [FeatureSlowUAMem, FeatureSSSE3, FeatureCMPXCHG16B,
240 def : ProcessorModel<"penryn", SandyBridgeModel,
241 [FeatureSlowUAMem, FeatureSSE41, FeatureCMPXCHG16B,
245 class BonnellProc<string Name> : ProcessorModel<Name, AtomModel, [
255 FeatureCallRegIndirect,
257 FeaturePadShortFunctions
259 def : BonnellProc<"bonnell">;
260 def : BonnellProc<"atom">; // Pin the generic name to the baseline.
262 class SilvermontProc<string Name> : ProcessorModel<Name, SLMModel, [
271 FeatureCallRegIndirect,
277 def : SilvermontProc<"silvermont">;
278 def : SilvermontProc<"slm">; // Legacy alias.
280 // "Arrandale" along with corei3 and corei5
281 class NehalemProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
287 def : NehalemProc<"nehalem">;
288 def : NehalemProc<"corei7">;
290 // Westmere is a similar machine to nehalem with some additional features.
291 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
292 class WestmereProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
300 def : WestmereProc<"westmere">;
302 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
303 // rather than a superset.
304 class SandyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
313 def : SandyBridgeProc<"sandybridge">;
314 def : SandyBridgeProc<"corei7-avx">; // Legacy alias.
316 class IvyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
328 def : IvyBridgeProc<"ivybridge">;
329 def : IvyBridgeProc<"core-avx-i">; // Legacy alias.
331 class HaswellProc<string Name> : ProcessorModel<Name, HaswellModel, [
350 def : HaswellProc<"haswell">;
351 def : HaswellProc<"core-avx2">; // Legacy alias.
353 class BroadwellProc<string Name> : ProcessorModel<Name, HaswellModel, [
374 def : BroadwellProc<"broadwell">;
376 // FIXME: define KNL model
377 class KnightsLandingProc<string Name> : ProcessorModel<Name, HaswellModel,
378 [FeatureAVX512, FeatureERI, FeatureCDI, FeaturePFI,
379 FeatureCMPXCHG16B, FeaturePOPCNT,
380 FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C,
381 FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI,
382 FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE,
383 FeatureSlowIncDec, FeatureMPX]>;
384 def : KnightsLandingProc<"knl">;
386 // FIXME: define SKX model
387 class SkylakeProc<string Name> : ProcessorModel<Name, HaswellModel,
388 [FeatureAVX512, FeatureCDI,
389 FeatureDQI, FeatureBWI, FeatureVLX,
390 FeatureCMPXCHG16B, FeatureSlowBTMem,
391 FeaturePOPCNT, FeatureAES, FeaturePCLMUL, FeatureRDRAND,
392 FeatureF16C, FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT,
393 FeatureBMI, FeatureBMI2, FeatureFMA, FeatureRTM,
394 FeatureHLE, FeatureADX, FeatureRDSEED, FeatureSlowIncDec,
396 def : SkylakeProc<"skylake">;
397 def : SkylakeProc<"skx">; // Legacy alias.
402 def : Proc<"k6", [FeatureSlowUAMem, FeatureMMX]>;
403 def : Proc<"k6-2", [FeatureSlowUAMem, Feature3DNow]>;
404 def : Proc<"k6-3", [FeatureSlowUAMem, Feature3DNow]>;
405 def : Proc<"athlon", [FeatureSlowUAMem, Feature3DNowA,
406 FeatureSlowBTMem, FeatureSlowSHLD]>;
407 def : Proc<"athlon-tbird", [FeatureSlowUAMem, Feature3DNowA,
408 FeatureSlowBTMem, FeatureSlowSHLD]>;
409 def : Proc<"athlon-4", [FeatureSlowUAMem, FeatureSSE1, Feature3DNowA,
410 FeatureSlowBTMem, FeatureSlowSHLD]>;
411 def : Proc<"athlon-xp", [FeatureSlowUAMem, FeatureSSE1, Feature3DNowA,
412 FeatureSlowBTMem, FeatureSlowSHLD]>;
413 def : Proc<"athlon-mp", [FeatureSlowUAMem, FeatureSSE1, Feature3DNowA,
414 FeatureSlowBTMem, FeatureSlowSHLD]>;
415 def : Proc<"k8", [FeatureSlowUAMem, FeatureSSE2, Feature3DNowA,
416 Feature64Bit, FeatureSlowBTMem,
418 def : Proc<"opteron", [FeatureSlowUAMem, FeatureSSE2, Feature3DNowA,
419 Feature64Bit, FeatureSlowBTMem,
421 def : Proc<"athlon64", [FeatureSlowUAMem, FeatureSSE2, Feature3DNowA,
422 Feature64Bit, FeatureSlowBTMem,
424 def : Proc<"athlon-fx", [FeatureSlowUAMem, FeatureSSE2, Feature3DNowA,
425 Feature64Bit, FeatureSlowBTMem,
427 def : Proc<"k8-sse3", [FeatureSlowUAMem, FeatureSSE3, Feature3DNowA,
428 FeatureCMPXCHG16B, FeatureSlowBTMem,
430 def : Proc<"opteron-sse3", [FeatureSlowUAMem, FeatureSSE3, Feature3DNowA,
431 FeatureCMPXCHG16B, FeatureSlowBTMem,
433 def : Proc<"athlon64-sse3", [FeatureSlowUAMem, FeatureSSE3, Feature3DNowA,
434 FeatureCMPXCHG16B, FeatureSlowBTMem,
436 def : Proc<"amdfam10", [FeatureSSE4A,
437 Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
438 FeaturePOPCNT, FeatureSlowBTMem,
440 def : Proc<"barcelona", [FeatureSSE4A,
441 Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
442 FeaturePOPCNT, FeatureSlowBTMem,
446 def : Proc<"btver1", [FeatureSSSE3, FeatureSSE4A, FeatureCMPXCHG16B,
447 FeaturePRFCHW, FeatureLZCNT, FeaturePOPCNT,
451 def : ProcessorModel<"btver2", BtVer2Model,
452 [FeatureAVX, FeatureSSE4A, FeatureCMPXCHG16B,
453 FeaturePRFCHW, FeatureAES, FeaturePCLMUL,
454 FeatureBMI, FeatureF16C, FeatureMOVBE,
455 FeatureLZCNT, FeaturePOPCNT,
459 def : Proc<"bdver1", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
460 FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
461 FeatureAVX, FeatureSSE4A, FeatureLZCNT,
462 FeaturePOPCNT, FeatureSlowSHLD]>;
464 def : Proc<"bdver2", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
465 FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
466 FeatureAVX, FeatureSSE4A, FeatureF16C,
467 FeatureLZCNT, FeaturePOPCNT, FeatureBMI,
468 FeatureTBM, FeatureFMA, FeatureSlowSHLD]>;
471 def : Proc<"bdver3", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
472 FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
473 FeatureAVX, FeatureSSE4A, FeatureF16C,
474 FeatureLZCNT, FeaturePOPCNT, FeatureBMI,
475 FeatureTBM, FeatureFMA, FeatureSlowSHLD,
479 def : Proc<"bdver4", [FeatureAVX2, FeatureXOP, FeatureFMA4,
480 FeatureCMPXCHG16B, FeatureAES, FeaturePRFCHW,
481 FeaturePCLMUL, FeatureF16C, FeatureLZCNT,
482 FeaturePOPCNT, FeatureBMI, FeatureBMI2,
483 FeatureTBM, FeatureFMA, FeatureSSE4A,
486 def : Proc<"geode", [FeatureSlowUAMem, Feature3DNowA]>;
488 def : Proc<"winchip-c6", [FeatureSlowUAMem, FeatureMMX]>;
489 def : Proc<"winchip2", [FeatureSlowUAMem, Feature3DNow]>;
490 def : Proc<"c3", [FeatureSlowUAMem, Feature3DNow]>;
491 def : Proc<"c3-2", [FeatureSlowUAMem, FeatureSSE1]>;
493 // We also provide a generic 64-bit specific x86 processor model which tries to
494 // be good for modern chips without enabling instruction set encodings past the
495 // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
496 // modern 64-bit x86 chip, and enables features that are generally beneficial.
498 // We currently use the Sandy Bridge model as the default scheduling model as
499 // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
500 // covers a huge swath of x86 processors. If there are specific scheduling
501 // knobs which need to be tuned differently for AMD chips, we might consider
502 // forming a common base for them.
503 def : ProcessorModel<"x86-64", SandyBridgeModel,
504 [FeatureSSE2, Feature64Bit, FeatureSlowBTMem]>;
506 //===----------------------------------------------------------------------===//
507 // Register File Description
508 //===----------------------------------------------------------------------===//
510 include "X86RegisterInfo.td"
512 //===----------------------------------------------------------------------===//
513 // Instruction Descriptions
514 //===----------------------------------------------------------------------===//
516 include "X86InstrInfo.td"
518 def X86InstrInfo : InstrInfo;
520 //===----------------------------------------------------------------------===//
521 // Calling Conventions
522 //===----------------------------------------------------------------------===//
524 include "X86CallingConv.td"
527 //===----------------------------------------------------------------------===//
529 //===----------------------------------------------------------------------===//
531 def ATTAsmParser : AsmParser {
532 string AsmParserClassName = "AsmParser";
535 def ATTAsmParserVariant : AsmParserVariant {
541 // Discard comments in assembly strings.
542 string CommentDelimiter = "#";
544 // Recognize hard coded registers.
545 string RegisterPrefix = "%";
548 def IntelAsmParserVariant : AsmParserVariant {
552 string Name = "intel";
554 // Discard comments in assembly strings.
555 string CommentDelimiter = ";";
557 // Recognize hard coded registers.
558 string RegisterPrefix = "";
561 //===----------------------------------------------------------------------===//
563 //===----------------------------------------------------------------------===//
565 // The X86 target supports two different syntaxes for emitting machine code.
566 // This is controlled by the -x86-asm-syntax={att|intel}
567 def ATTAsmWriter : AsmWriter {
568 string AsmWriterClassName = "ATTInstPrinter";
571 def IntelAsmWriter : AsmWriter {
572 string AsmWriterClassName = "IntelInstPrinter";
577 // Information about the instructions...
578 let InstructionSet = X86InstrInfo;
579 let AssemblyParsers = [ATTAsmParser];
580 let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
581 let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];