1 //===- X86.td - Target definition file for the Intel X86 ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is a target description file for the Intel i386 architecture, refered to
11 // here as the "X86" architecture.
13 //===----------------------------------------------------------------------===//
15 // Get the target-independent interfaces which we are implementing...
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // X86 Subtarget features.
21 //===----------------------------------------------------------------------===//
23 def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true",
24 "Enable conditional move instructions">;
26 def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
27 "Support POPCNT instruction">;
30 def FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX",
31 "Enable MMX instructions">;
32 def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
33 "Enable SSE instructions",
34 // SSE codegen depends on cmovs, and all
35 // SSE1+ processors support them.
36 [FeatureMMX, FeatureCMOV]>;
37 def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
38 "Enable SSE2 instructions",
40 def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
41 "Enable SSE3 instructions",
43 def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
44 "Enable SSSE3 instructions",
46 def FeatureSSE41 : SubtargetFeature<"sse41", "X86SSELevel", "SSE41",
47 "Enable SSE 4.1 instructions",
49 def FeatureSSE42 : SubtargetFeature<"sse42", "X86SSELevel", "SSE42",
50 "Enable SSE 4.2 instructions",
51 [FeatureSSE41, FeaturePOPCNT]>;
52 def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
53 "Enable 3DNow! instructions">;
54 def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
55 "Enable 3DNow! Athlon instructions",
57 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
58 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
59 // without disabling 64-bit mode.
60 def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true",
61 "Support 64-bit instructions",
63 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
64 "Bit testing of memory is slow">;
65 def FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem",
66 "IsUAMemFast", "true",
67 "Fast unaligned memory access">;
68 def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true",
69 "Support SSE 4a instructions",
72 def FeatureAVX : SubtargetFeature<"avx", "HasAVX", "true",
73 "Enable AVX instructions">;
74 def FeatureCLMUL : SubtargetFeature<"clmul", "HasCLMUL", "true",
75 "Enable carry-less multiplication instructions">;
76 def FeatureFMA3 : SubtargetFeature<"fma3", "HasFMA3", "true",
77 "Enable three-operand fused multiple-add">;
78 def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true",
79 "Enable four-operand fused multiple-add">;
80 def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
81 "HasVectorUAMem", "true",
82 "Allow unaligned memory operands on vector/SIMD instructions">;
83 def FeatureAES : SubtargetFeature<"aes", "HasAES", "true",
84 "Enable AES instructions">;
86 //===----------------------------------------------------------------------===//
87 // X86 processors supported.
88 //===----------------------------------------------------------------------===//
90 class Proc<string Name, list<SubtargetFeature> Features>
91 : Processor<Name, NoItineraries, Features>;
93 def : Proc<"generic", []>;
94 def : Proc<"i386", []>;
95 def : Proc<"i486", []>;
96 def : Proc<"i586", []>;
97 def : Proc<"pentium", []>;
98 def : Proc<"pentium-mmx", [FeatureMMX]>;
99 def : Proc<"i686", []>;
100 def : Proc<"pentiumpro", [FeatureCMOV]>;
101 def : Proc<"pentium2", [FeatureMMX, FeatureCMOV]>;
102 def : Proc<"pentium3", [FeatureSSE1]>;
103 def : Proc<"pentium-m", [FeatureSSE2, FeatureSlowBTMem]>;
104 def : Proc<"pentium4", [FeatureSSE2]>;
105 def : Proc<"x86-64", [FeatureSSE2, Feature64Bit, FeatureSlowBTMem]>;
106 def : Proc<"yonah", [FeatureSSE3, FeatureSlowBTMem]>;
107 def : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>;
108 def : Proc<"nocona", [FeatureSSE3, Feature64Bit, FeatureSlowBTMem]>;
109 def : Proc<"core2", [FeatureSSSE3, Feature64Bit, FeatureSlowBTMem]>;
110 def : Proc<"penryn", [FeatureSSE41, Feature64Bit, FeatureSlowBTMem]>;
111 def : Proc<"atom", [FeatureSSE3, Feature64Bit, FeatureSlowBTMem]>;
112 // "Arrandale" along with corei3 and corei5
113 def : Proc<"corei7", [FeatureSSE42, Feature64Bit, FeatureSlowBTMem,
114 FeatureFastUAMem, FeatureAES]>;
115 def : Proc<"nehalem", [FeatureSSE42, Feature64Bit, FeatureSlowBTMem,
117 // Westmere is a similar machine to nehalem with some additional features.
118 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
119 def : Proc<"westmere", [FeatureSSE42, Feature64Bit, FeatureSlowBTMem,
120 FeatureFastUAMem, FeatureAES, FeatureCLMUL]>;
121 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
122 // rather than a superset.
123 // FIXME: Disabling AVX for now since it's not ready.
124 def : Proc<"sandybridge", [FeatureSSE42, Feature64Bit,
125 FeatureAES, FeatureCLMUL]>;
127 def : Proc<"k6", [FeatureMMX]>;
128 def : Proc<"k6-2", [FeatureMMX, Feature3DNow]>;
129 def : Proc<"k6-3", [FeatureMMX, Feature3DNow]>;
130 def : Proc<"athlon", [FeatureMMX, Feature3DNowA, FeatureSlowBTMem]>;
131 def : Proc<"athlon-tbird", [FeatureMMX, Feature3DNowA, FeatureSlowBTMem]>;
132 def : Proc<"athlon-4", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
133 def : Proc<"athlon-xp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
134 def : Proc<"athlon-mp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
135 def : Proc<"k8", [FeatureSSE2, Feature3DNowA, Feature64Bit,
137 def : Proc<"opteron", [FeatureSSE2, Feature3DNowA, Feature64Bit,
139 def : Proc<"athlon64", [FeatureSSE2, Feature3DNowA, Feature64Bit,
141 def : Proc<"athlon-fx", [FeatureSSE2, Feature3DNowA, Feature64Bit,
143 def : Proc<"k8-sse3", [FeatureSSE3, Feature3DNowA, Feature64Bit,
145 def : Proc<"opteron-sse3", [FeatureSSE3, Feature3DNowA, Feature64Bit,
147 def : Proc<"athlon64-sse3", [FeatureSSE3, Feature3DNowA, Feature64Bit,
149 def : Proc<"amdfam10", [FeatureSSE3, FeatureSSE4A,
150 Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>;
151 def : Proc<"barcelona", [FeatureSSE3, FeatureSSE4A,
152 Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>;
153 def : Proc<"istanbul", [Feature3DNowA, Feature64Bit, FeatureSSE4A,
155 def : Proc<"shanghai", [Feature3DNowA, Feature64Bit, FeatureSSE4A,
158 def : Proc<"winchip-c6", [FeatureMMX]>;
159 def : Proc<"winchip2", [FeatureMMX, Feature3DNow]>;
160 def : Proc<"c3", [FeatureMMX, Feature3DNow]>;
161 def : Proc<"c3-2", [FeatureSSE1]>;
163 //===----------------------------------------------------------------------===//
164 // Register File Description
165 //===----------------------------------------------------------------------===//
167 include "X86RegisterInfo.td"
169 //===----------------------------------------------------------------------===//
170 // Instruction Descriptions
171 //===----------------------------------------------------------------------===//
173 include "X86InstrInfo.td"
175 def X86InstrInfo : InstrInfo;
177 //===----------------------------------------------------------------------===//
178 // Calling Conventions
179 //===----------------------------------------------------------------------===//
181 include "X86CallingConv.td"
184 //===----------------------------------------------------------------------===//
186 //===----------------------------------------------------------------------===//
188 // Currently the X86 assembly parser only supports ATT syntax.
189 def ATTAsmParser : AsmParser {
190 string AsmParserClassName = "ATTAsmParser";
193 // Discard comments in assembly strings.
194 string CommentDelimiter = "#";
196 // Recognize hard coded registers.
197 string RegisterPrefix = "%";
200 //===----------------------------------------------------------------------===//
202 //===----------------------------------------------------------------------===//
204 // The X86 target supports two different syntaxes for emitting machine code.
205 // This is controlled by the -x86-asm-syntax={att|intel}
206 def ATTAsmWriter : AsmWriter {
207 string AsmWriterClassName = "ATTInstPrinter";
209 bit isMCAsmWriter = 1;
211 def IntelAsmWriter : AsmWriter {
212 string AsmWriterClassName = "IntelInstPrinter";
214 bit isMCAsmWriter = 1;
218 // Information about the instructions...
219 let InstructionSet = X86InstrInfo;
221 let AssemblyParsers = [ATTAsmParser];
223 let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];