1 //===- X86.td - Target definition file for the Intel X86 arch ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is a target description file for the Intel i386 architecture, refered to
11 // here as the "X86" architecture.
13 //===----------------------------------------------------------------------===//
15 // Get the target-independent interfaces which we are implementing...
17 include "../Target.td"
19 //===----------------------------------------------------------------------===//
20 // X86 Subtarget features.
21 //===----------------------------------------------------------------------===//
23 def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true",
24 "Support 64-bit instructions">;
25 def FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX",
26 "Enable MMX instructions">;
27 def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
28 "Enable SSE instructions",
30 def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
31 "Enable SSE2 instructions",
33 def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
34 "Enable SSE3 instructions",
36 def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
37 "Enable SSSE3 instructions",
39 def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
40 "Enable 3DNow! instructions">;
41 def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
42 "Enable 3DNow! Athlon instructions">;
44 //===----------------------------------------------------------------------===//
45 // X86 processors supported.
46 //===----------------------------------------------------------------------===//
48 class Proc<string Name, list<SubtargetFeature> Features>
49 : Processor<Name, NoItineraries, Features>;
51 def : Proc<"generic", []>;
52 def : Proc<"i386", []>;
53 def : Proc<"i486", []>;
54 def : Proc<"pentium", []>;
55 def : Proc<"pentium-mmx", [FeatureMMX]>;
56 def : Proc<"i686", []>;
57 def : Proc<"pentiumpro", []>;
58 def : Proc<"pentium2", [FeatureMMX]>;
59 def : Proc<"pentium3", [FeatureMMX, FeatureSSE1]>;
60 def : Proc<"pentium-m", [FeatureMMX, FeatureSSE1, FeatureSSE2]>;
61 def : Proc<"pentium4", [FeatureMMX, FeatureSSE1, FeatureSSE2]>;
62 def : Proc<"x86-64", [FeatureMMX, FeatureSSE1, FeatureSSE2,
64 def : Proc<"yonah", [FeatureMMX, FeatureSSE1, FeatureSSE2,
66 def : Proc<"prescott", [FeatureMMX, FeatureSSE1, FeatureSSE2,
68 def : Proc<"nocona", [FeatureMMX, FeatureSSE1, FeatureSSE2,
69 FeatureSSE3, Feature64Bit]>;
70 def : Proc<"core2", [FeatureMMX, FeatureSSE1, FeatureSSE2,
71 FeatureSSE3, FeatureSSSE3, Feature64Bit]>;
73 def : Proc<"k6", [FeatureMMX]>;
74 def : Proc<"k6-2", [FeatureMMX, Feature3DNow]>;
75 def : Proc<"k6-3", [FeatureMMX, Feature3DNow]>;
76 def : Proc<"athlon", [FeatureMMX, Feature3DNow, Feature3DNowA]>;
77 def : Proc<"athlon-tbird", [FeatureMMX, Feature3DNow, Feature3DNowA]>;
78 def : Proc<"athlon-4", [FeatureMMX, FeatureSSE1, Feature3DNow,
80 def : Proc<"athlon-xp", [FeatureMMX, FeatureSSE1, Feature3DNow,
82 def : Proc<"athlon-mp", [FeatureMMX, FeatureSSE1, Feature3DNow,
84 def : Proc<"k8", [FeatureMMX, FeatureSSE1, FeatureSSE2,
85 Feature3DNow, Feature3DNowA, Feature64Bit]>;
86 def : Proc<"opteron", [FeatureMMX, FeatureSSE1, FeatureSSE2,
87 Feature3DNow, Feature3DNowA, Feature64Bit]>;
88 def : Proc<"athlon64", [FeatureMMX, FeatureSSE1, FeatureSSE2,
89 Feature3DNow, Feature3DNowA, Feature64Bit]>;
90 def : Proc<"athlon-fx", [FeatureMMX, FeatureSSE1, FeatureSSE2,
91 Feature3DNow, Feature3DNowA, Feature64Bit]>;
93 def : Proc<"winchip-c6", [FeatureMMX]>;
94 def : Proc<"winchip2", [FeatureMMX, Feature3DNow]>;
95 def : Proc<"c3", [FeatureMMX, Feature3DNow]>;
96 def : Proc<"c3-2", [FeatureMMX, FeatureSSE1]>;
98 //===----------------------------------------------------------------------===//
99 // Register File Description
100 //===----------------------------------------------------------------------===//
102 include "X86RegisterInfo.td"
104 //===----------------------------------------------------------------------===//
105 // Instruction Descriptions
106 //===----------------------------------------------------------------------===//
108 include "X86InstrInfo.td"
110 def X86InstrInfo : InstrInfo {
112 // Define how we want to layout our TargetSpecific information field... This
113 // should be kept up-to-date with the fields in the X86InstrInfo.h file.
114 let TSFlagsFields = ["FormBits",
122 let TSFlagsShifts = [0,
132 //===----------------------------------------------------------------------===//
133 // Calling Conventions
134 //===----------------------------------------------------------------------===//
136 include "X86CallingConv.td"
139 //===----------------------------------------------------------------------===//
141 //===----------------------------------------------------------------------===//
143 // The X86 target supports two different syntaxes for emitting machine code.
144 // This is controlled by the -x86-asm-syntax={att|intel}
145 def ATTAsmWriter : AsmWriter {
146 string AsmWriterClassName = "ATTAsmPrinter";
149 def IntelAsmWriter : AsmWriter {
150 string AsmWriterClassName = "IntelAsmPrinter";
156 // Information about the instructions...
157 let InstructionSet = X86InstrInfo;
159 let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];