lib/Target/X86/X86.td

   1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is a target description file for the Intel i386 architecture, referred
  11 // to here as the "X86" architecture.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 // Get the target-independent interfaces which we are implementing...
  16 //
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // X86 Subtarget state
  21 //
  22
  23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
  24                                   "64-bit mode (x86_64)">;
  25 def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",
  26                                   "32-bit mode (80386)">;
  27 def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
  28                                   "16-bit mode (i8086)">;
  29
  30 //===----------------------------------------------------------------------===//
  31 // X86 Subtarget features
  32 //===----------------------------------------------------------------------===//
  33
  34 def FeatureCMOV    : SubtargetFeature<"cmov","HasCMov", "true",
  35                                       "Enable conditional move instructions">;
  36
  37 def FeaturePOPCNT   : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
  38                                        "Support POPCNT instruction">;
  39
  40 // The MMX subtarget feature is separate from the rest of the SSE features
  41 // because it's important (for odd compatibility reasons) to be able to
  42 // turn it off explicitly while allowing SSE+ to be on.
  43 def FeatureMMX     : SubtargetFeature<"mmx","HasMMX", "true",
  44                                       "Enable MMX instructions">;
  45
  46 def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
  47                                       "Enable SSE instructions",
  48                                       // SSE codegen depends on cmovs, and all
  49                                       // SSE1+ processors support them.
  50                                       [FeatureCMOV]>;
  51 def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
  52                                       "Enable SSE2 instructions",
  53                                       [FeatureSSE1]>;
  54 def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
  55                                       "Enable SSE3 instructions",
  56                                       [FeatureSSE2]>;
  57 def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
  58                                       "Enable SSSE3 instructions",
  59                                       [FeatureSSE3]>;
  60 def FeatureSSE41   : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
  61                                       "Enable SSE 4.1 instructions",
  62                                       [FeatureSSSE3]>;
  63 def FeatureSSE42   : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
  64                                       "Enable SSE 4.2 instructions",
  65                                       [FeatureSSE41]>;
  66 def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
  67                                       "Enable 3DNow! instructions",
  68                                       [FeatureMMX]>;
  69 def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
  70                                       "Enable 3DNow! Athlon instructions",
  71                                       [Feature3DNow]>;
  72 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
  73 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
  74 // without disabling 64-bit mode.
  75 def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
  76                                       "Support 64-bit instructions",
  77                                       [FeatureCMOV]>;
  78 def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
  79                                       "64-bit with cmpxchg16b",
  80                                       [Feature64Bit]>;
  81 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
  82                                        "Bit testing of memory is slow">;
  83 def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
  84                                        "SHLD instruction is slow">;
  85 // FIXME: This should not apply to CPUs that do not have SSE.
  86 def FeatureSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16",
  87                                 "IsUAMem16Slow", "true",
  88                                 "Slow unaligned 16-byte memory access">;
  89 def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
  90                                 "IsUAMem32Slow", "true",
  91                                 "Slow unaligned 32-byte memory access">;
  92 def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
  93                                       "Support SSE 4a instructions",
  94                                       [FeatureSSE3]>;
  95
  96 def FeatureAVX     : SubtargetFeature<"avx", "X86SSELevel", "AVX",
  97                                       "Enable AVX instructions",
  98                                       [FeatureSSE42]>;
  99 def FeatureAVX2    : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
 100                                       "Enable AVX2 instructions",
 101                                       [FeatureAVX]>;
 102 def FeatureAVX512   : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
 103                                       "Enable AVX-512 instructions",
 104                                       [FeatureAVX2]>;
 105 def FeatureERI      : SubtargetFeature<"avx512er", "HasERI", "true",
 106                       "Enable AVX-512 Exponential and Reciprocal Instructions",
 107                                       [FeatureAVX512]>;
 108 def FeatureCDI      : SubtargetFeature<"avx512cd", "HasCDI", "true",
 109                       "Enable AVX-512 Conflict Detection Instructions",
 110                                       [FeatureAVX512]>;
 111 def FeaturePFI      : SubtargetFeature<"avx512pf", "HasPFI", "true",
 112                       "Enable AVX-512 PreFetch Instructions",
 113                                       [FeatureAVX512]>;
 114 def FeatureDQI     : SubtargetFeature<"avx512dq", "HasDQI", "true",
 115                       "Enable AVX-512 Doubleword and Quadword Instructions",
 116                                       [FeatureAVX512]>;
 117 def FeatureBWI     : SubtargetFeature<"avx512bw", "HasBWI", "true",
 118                       "Enable AVX-512 Byte and Word Instructions",
 119                                       [FeatureAVX512]>;
 120 def FeatureVLX     : SubtargetFeature<"avx512vl", "HasVLX", "true",
 121                       "Enable AVX-512 Vector Length eXtensions",
 122                                       [FeatureAVX512]>;
 123 def FeaturePCLMUL  : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
 124                          "Enable packed carry-less multiplication instructions",
 125                                [FeatureSSE2]>;
 126 def FeatureFMA     : SubtargetFeature<"fma", "HasFMA", "true",
 127                                       "Enable three-operand fused multiple-add",
 128                                       [FeatureAVX]>;
 129 def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
 130                                       "Enable four-operand fused multiple-add",
 131                                       [FeatureAVX, FeatureSSE4A]>;
 132 def FeatureXOP     : SubtargetFeature<"xop", "HasXOP", "true",
 133                                       "Enable XOP instructions",
 134                                       [FeatureFMA4]>;
 135 def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem",
 136                                           "HasSSEUnalignedMem", "true",
 137                       "Allow unaligned memory operands with SSE instructions">;
 138 def FeatureAES     : SubtargetFeature<"aes", "HasAES", "true",
 139                                       "Enable AES instructions",
 140                                       [FeatureSSE2]>;
 141 def FeatureTBM     : SubtargetFeature<"tbm", "HasTBM", "true",
 142                                       "Enable TBM instructions">;
 143 def FeatureMOVBE   : SubtargetFeature<"movbe", "HasMOVBE", "true",
 144                                       "Support MOVBE instruction">;
 145 def FeatureRDRAND  : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
 146                                       "Support RDRAND instruction">;
 147 def FeatureF16C    : SubtargetFeature<"f16c", "HasF16C", "true",
 148                        "Support 16-bit floating point conversion instructions",
 149                        [FeatureAVX]>;
 150 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
 151                                        "Support FS/GS Base instructions">;
 152 def FeatureLZCNT   : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
 153                                       "Support LZCNT instruction">;
 154 def FeatureBMI     : SubtargetFeature<"bmi", "HasBMI", "true",
 155                                       "Support BMI instructions">;
 156 def FeatureBMI2    : SubtargetFeature<"bmi2", "HasBMI2", "true",
 157                                       "Support BMI2 instructions">;
 158 def FeatureRTM     : SubtargetFeature<"rtm", "HasRTM", "true",
 159                                       "Support RTM instructions">;
 160 def FeatureHLE     : SubtargetFeature<"hle", "HasHLE", "true",
 161                                       "Support HLE">;
 162 def FeatureADX     : SubtargetFeature<"adx", "HasADX", "true",
 163                                       "Support ADX instructions">;
 164 def FeatureSHA     : SubtargetFeature<"sha", "HasSHA", "true",
 165                                       "Enable SHA instructions",
 166                                       [FeatureSSE2]>;
 167 def FeaturePRFCHW  : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
 168                                       "Support PRFCHW instructions">;
 169 def FeatureRDSEED  : SubtargetFeature<"rdseed", "HasRDSEED", "true",
 170                                       "Support RDSEED instruction">;
 171 def FeatureMPX     : SubtargetFeature<"mpx", "HasMPX", "true",
 172                                       "Support MPX instructions">;
 173 def FeatureLeaForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
 174                                      "Use LEA for adjusting the stack pointer">;
 175 def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
 176                                      "HasSlowDivide32", "true",
 177                                      "Use 8-bit divide for positive values less than 256">;
 178 def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divw",
 179                                      "HasSlowDivide64", "true",
 180                                      "Use 16-bit divide for positive values less than 65536">;
 181 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
 182                                      "PadShortFunctions", "true",
 183                                      "Pad short functions">;
 184 // TODO: This feature ought to be renamed.
 185 // What it really refers to are CPUs for which certain instructions
 186 // (which ones besides the example below?) are microcoded.
 187 // The best examples of this are the memory forms of CALL and PUSH
 188 // instructions, which should be avoided in favor of a MOV + register CALL/PUSH.
 189 def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect",
 190                                      "CallRegIndirect", "true",
 191                                      "Call register indirect">;
 192 def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
 193                                    "LEA instruction needs inputs at AG stage">;
 194 def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
 195                                    "LEA instruction with certain arguments is slow">;
 196 def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
 197                                    "INC and DEC instructions are slower than ADD and SUB">;
 198 def FeatureSoftFloat
 199     : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
 200                        "Use software floating point features.">;
 201
 202 //===----------------------------------------------------------------------===//
 203 // X86 processors supported.
 204 //===----------------------------------------------------------------------===//
 205
 206 include "X86Schedule.td"
 207
 208 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
 209                     "Intel Atom processors">;
 210 def ProcIntelSLM  : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM",
 211                     "Intel Silvermont processors">;
 212
 213 class Proc<string Name, list<SubtargetFeature> Features>
 214  : ProcessorModel<Name, GenericModel, Features>;
 215
 216 def : Proc<"generic",         [FeatureSlowUAMem16]>;
 217 def : Proc<"i386",            [FeatureSlowUAMem16]>;
 218 def : Proc<"i486",            [FeatureSlowUAMem16]>;
 219 def : Proc<"i586",            [FeatureSlowUAMem16]>;
 220 def : Proc<"pentium",         [FeatureSlowUAMem16]>;
 221 def : Proc<"pentium-mmx",     [FeatureSlowUAMem16, FeatureMMX]>;
 222 def : Proc<"i686",            [FeatureSlowUAMem16]>;
 223 def : Proc<"pentiumpro",      [FeatureSlowUAMem16, FeatureCMOV]>;
 224 def : Proc<"pentium2",        [FeatureSlowUAMem16, FeatureMMX, FeatureCMOV]>;
 225 def : Proc<"pentium3",        [FeatureSlowUAMem16, FeatureMMX, FeatureSSE1]>;
 226 def : Proc<"pentium3m",       [FeatureSlowUAMem16, FeatureMMX, FeatureSSE1,
 227                                FeatureSlowBTMem]>;
 228 def : Proc<"pentium-m",       [FeatureSlowUAMem16, FeatureMMX, FeatureSSE2,
 229                                FeatureSlowBTMem]>;
 230 def : Proc<"pentium4",        [FeatureSlowUAMem16, FeatureMMX, FeatureSSE2]>;
 231 def : Proc<"pentium4m",       [FeatureSlowUAMem16, FeatureMMX, FeatureSSE2,
 232                                FeatureSlowBTMem]>;
 233
 234 // Intel Core Duo.
 235 def : ProcessorModel<
 236           "yonah", SandyBridgeModel,
 237           [ FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, FeatureSlowBTMem ]>;
 238
 239 // NetBurst.
 240 def : Proc<"prescott",
 241            [ FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, FeatureSlowBTMem ]>;
 242 def : Proc<"nocona", [
 243   FeatureSlowUAMem16,
 244   FeatureMMX,
 245   FeatureSSE3,
 246   FeatureCMPXCHG16B,
 247   FeatureSlowBTMem
 248 ]>;
 249
 250 // Intel Core 2 Solo/Duo.
 251 def : ProcessorModel<"core2", SandyBridgeModel, [
 252   FeatureSlowUAMem16,
 253   FeatureMMX,
 254   FeatureSSSE3,
 255   FeatureCMPXCHG16B,
 256   FeatureSlowBTMem
 257 ]>;
 258 def : ProcessorModel<"penryn", SandyBridgeModel, [
 259   FeatureSlowUAMem16,
 260   FeatureMMX,
 261   FeatureSSE41,
 262   FeatureCMPXCHG16B,
 263   FeatureSlowBTMem
 264 ]>;
 265
 266 // Atom CPUs.
 267 class BonnellProc<string Name> : ProcessorModel<Name, AtomModel, [
 268   ProcIntelAtom,
 269   FeatureSlowUAMem16,
 270   FeatureMMX,
 271   FeatureSSSE3,
 272   FeatureCMPXCHG16B,
 273   FeatureMOVBE,
 274   FeatureSlowBTMem,
 275   FeatureLeaForSP,
 276   FeatureSlowDivide32,
 277   FeatureSlowDivide64,
 278   FeatureCallRegIndirect,
 279   FeatureLEAUsesAG,
 280   FeaturePadShortFunctions
 281 ]>;
 282 def : BonnellProc<"bonnell">;
 283 def : BonnellProc<"atom">; // Pin the generic name to the baseline.
 284
 285 class SilvermontProc<string Name> : ProcessorModel<Name, SLMModel, [
 286   ProcIntelSLM,
 287   FeatureMMX,
 288   FeatureSSE42,
 289   FeatureCMPXCHG16B,
 290   FeatureMOVBE,
 291   FeaturePOPCNT,
 292   FeaturePCLMUL,
 293   FeatureAES,
 294   FeatureSlowDivide64,
 295   FeatureCallRegIndirect,
 296   FeaturePRFCHW,
 297   FeatureSlowLEA,
 298   FeatureSlowIncDec,
 299   FeatureSlowBTMem
 300 ]>;
 301 def : SilvermontProc<"silvermont">;
 302 def : SilvermontProc<"slm">; // Legacy alias.
 303
 304 // "Arrandale" along with corei3 and corei5
 305 class NehalemProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 306   FeatureMMX,
 307   FeatureSSE42,
 308   FeatureCMPXCHG16B,
 309   FeatureSlowBTMem,
 310   FeaturePOPCNT
 311 ]>;
 312 def : NehalemProc<"nehalem">;
 313 def : NehalemProc<"corei7">;
 314
 315 // Westmere is a similar machine to nehalem with some additional features.
 316 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
 317 class WestmereProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 318   FeatureMMX,
 319   FeatureSSE42,
 320   FeatureCMPXCHG16B,
 321   FeatureSlowBTMem,
 322   FeaturePOPCNT,
 323   FeatureAES,
 324   FeaturePCLMUL
 325 ]>;
 326 def : WestmereProc<"westmere">;
 327
 328 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
 329 // rather than a superset.
 330 class SandyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 331   FeatureMMX,
 332   FeatureAVX,
 333   FeatureCMPXCHG16B,
 334   FeatureSlowBTMem,
 335   FeatureSlowUAMem32,
 336   FeaturePOPCNT,
 337   FeatureAES,
 338   FeaturePCLMUL
 339 ]>;
 340 def : SandyBridgeProc<"sandybridge">;
 341 def : SandyBridgeProc<"corei7-avx">; // Legacy alias.
 342
 343 class IvyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 344   FeatureMMX,
 345   FeatureAVX,
 346   FeatureCMPXCHG16B,
 347   FeatureSlowBTMem,
 348   FeatureSlowUAMem32,
 349   FeaturePOPCNT,
 350   FeatureAES,
 351   FeaturePCLMUL,
 352   FeatureRDRAND,
 353   FeatureF16C,
 354   FeatureFSGSBase
 355 ]>;
 356 def : IvyBridgeProc<"ivybridge">;
 357 def : IvyBridgeProc<"core-avx-i">; // Legacy alias.
 358
 359 class HaswellProc<string Name> : ProcessorModel<Name, HaswellModel, [
 360   FeatureMMX,
 361   FeatureAVX2,
 362   FeatureCMPXCHG16B,
 363   FeatureSlowBTMem,
 364   FeaturePOPCNT,
 365   FeatureAES,
 366   FeaturePCLMUL,
 367   FeatureRDRAND,
 368   FeatureF16C,
 369   FeatureFSGSBase,
 370   FeatureMOVBE,
 371   FeatureLZCNT,
 372   FeatureBMI,
 373   FeatureBMI2,
 374   FeatureFMA,
 375   FeatureRTM,
 376   FeatureHLE,
 377   FeatureSlowIncDec
 378 ]>;
 379 def : HaswellProc<"haswell">;
 380 def : HaswellProc<"core-avx2">; // Legacy alias.
 381
 382 class BroadwellProc<string Name> : ProcessorModel<Name, HaswellModel, [
 383   FeatureMMX,
 384   FeatureAVX2,
 385   FeatureCMPXCHG16B,
 386   FeatureSlowBTMem,
 387   FeaturePOPCNT,
 388   FeatureAES,
 389   FeaturePCLMUL,
 390   FeatureRDRAND,
 391   FeatureF16C,
 392   FeatureFSGSBase,
 393   FeatureMOVBE,
 394   FeatureLZCNT,
 395   FeatureBMI,
 396   FeatureBMI2,
 397   FeatureFMA,
 398   FeatureRTM,
 399   FeatureHLE,
 400   FeatureADX,
 401   FeatureRDSEED,
 402   FeatureSlowIncDec
 403 ]>;
 404 def : BroadwellProc<"broadwell">;
 405
 406 // FIXME: define KNL model
 407 class KnightsLandingProc<string Name> : ProcessorModel<Name, HaswellModel, [
 408   FeatureMMX,
 409   FeatureAVX512,
 410   FeatureERI,
 411   FeatureCDI,
 412   FeaturePFI,
 413   FeatureCMPXCHG16B,
 414   FeaturePOPCNT,
 415   FeatureAES,
 416   FeaturePCLMUL,
 417   FeatureRDRAND,
 418   FeatureF16C,
 419   FeatureFSGSBase,
 420   FeatureMOVBE,
 421   FeatureLZCNT,
 422   FeatureBMI,
 423   FeatureBMI2,
 424   FeatureFMA,
 425   FeatureRTM,
 426   FeatureHLE,
 427   FeatureSlowIncDec,
 428   FeatureMPX
 429 ]>;
 430 def : KnightsLandingProc<"knl">;
 431
 432 // FIXME: define SKX model
 433 class SkylakeProc<string Name> : ProcessorModel<Name, HaswellModel, [
 434   FeatureMMX,
 435   FeatureAVX512,
 436   FeatureCDI,
 437   FeatureDQI,
 438   FeatureBWI,
 439   FeatureVLX,
 440   FeatureCMPXCHG16B,
 441   FeatureSlowBTMem,
 442   FeaturePOPCNT,
 443   FeatureAES,
 444   FeaturePCLMUL,
 445   FeatureRDRAND,
 446   FeatureF16C,
 447   FeatureFSGSBase,
 448   FeatureMOVBE,
 449   FeatureLZCNT,
 450   FeatureBMI,
 451   FeatureBMI2,
 452   FeatureFMA,
 453   FeatureRTM,
 454   FeatureHLE,
 455   FeatureADX,
 456   FeatureRDSEED,
 457   FeatureSlowIncDec,
 458   FeatureMPX
 459 ]>;
 460 def : SkylakeProc<"skylake">;
 461 def : SkylakeProc<"skx">; // Legacy alias.
 462
 463
 464 // AMD CPUs.
 465
 466 def : Proc<"k6",              [FeatureSlowUAMem16, FeatureMMX]>;
 467 def : Proc<"k6-2",            [FeatureSlowUAMem16, Feature3DNow]>;
 468 def : Proc<"k6-3",            [FeatureSlowUAMem16, Feature3DNow]>;
 469 def : Proc<"athlon",          [FeatureSlowUAMem16, Feature3DNowA,
 470                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 471 def : Proc<"athlon-tbird",    [FeatureSlowUAMem16, Feature3DNowA,
 472                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 473 def : Proc<"athlon-4",        [FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA,
 474                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 475 def : Proc<"athlon-xp",       [FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA,
 476                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 477 def : Proc<"athlon-mp",       [FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA,
 478                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 479 def : Proc<"k8",              [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
 480                                Feature64Bit, FeatureSlowBTMem,
 481                                FeatureSlowSHLD]>;
 482 def : Proc<"opteron",         [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
 483                                Feature64Bit, FeatureSlowBTMem,
 484                                FeatureSlowSHLD]>;
 485 def : Proc<"athlon64",        [FeatureSlowUAMem16, FeatureSSE2,   Feature3DNowA,
 486                                Feature64Bit, FeatureSlowBTMem,
 487                                FeatureSlowSHLD]>;
 488 def : Proc<"athlon-fx",       [FeatureSlowUAMem16, FeatureSSE2,   Feature3DNowA,
 489                                Feature64Bit, FeatureSlowBTMem,
 490                                FeatureSlowSHLD]>;
 491 def : Proc<"k8-sse3",         [FeatureSlowUAMem16, FeatureSSE3,   Feature3DNowA,
 492                                FeatureCMPXCHG16B, FeatureSlowBTMem,
 493                                FeatureSlowSHLD]>;
 494 def : Proc<"opteron-sse3",    [FeatureSlowUAMem16, FeatureSSE3,   Feature3DNowA,
 495                                FeatureCMPXCHG16B, FeatureSlowBTMem,
 496                                FeatureSlowSHLD]>;
 497 def : Proc<"athlon64-sse3",   [FeatureSlowUAMem16, FeatureSSE3,   Feature3DNowA,
 498                                FeatureCMPXCHG16B, FeatureSlowBTMem,
 499                                FeatureSlowSHLD]>;
 500 def : Proc<"amdfam10",        [FeatureSSE4A,
 501                                Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
 502                                FeaturePOPCNT, FeatureSlowBTMem,
 503                                FeatureSlowSHLD]>;
 504 def : Proc<"barcelona",       [FeatureSSE4A,
 505                                Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
 506                                FeaturePOPCNT, FeatureSlowBTMem,
 507                                FeatureSlowSHLD]>;
 508
 509 // Bobcat
 510 def : Proc<"btver1", [
 511   FeatureMMX,
 512   FeatureSSSE3,
 513   FeatureSSE4A,
 514   FeatureCMPXCHG16B,
 515   FeaturePRFCHW,
 516   FeatureLZCNT,
 517   FeaturePOPCNT,
 518   FeatureSlowSHLD
 519 ]>;
 520
 521 // Jaguar
 522 def : ProcessorModel<"btver2", BtVer2Model, [
 523   FeatureMMX,
 524   FeatureAVX,
 525   FeatureSSE4A,
 526   FeatureCMPXCHG16B,
 527   FeaturePRFCHW,
 528   FeatureAES,
 529   FeaturePCLMUL,
 530   FeatureBMI,
 531   FeatureF16C,
 532   FeatureMOVBE,
 533   FeatureLZCNT,
 534   FeaturePOPCNT,
 535   FeatureSlowSHLD
 536 ]>;
 537
 538 // Bulldozer
 539 def : Proc<"bdver1", [
 540   FeatureXOP,
 541   FeatureFMA4,
 542   FeatureCMPXCHG16B,
 543   FeatureAES,
 544   FeaturePRFCHW,
 545   FeaturePCLMUL,
 546   FeatureMMX,
 547   FeatureAVX,
 548   FeatureSSE4A,
 549   FeatureLZCNT,
 550   FeaturePOPCNT,
 551   FeatureSlowSHLD
 552 ]>;
 553 // Piledriver
 554 def : Proc<"bdver2", [
 555   FeatureXOP,
 556   FeatureFMA4,
 557   FeatureCMPXCHG16B,
 558   FeatureAES,
 559   FeaturePRFCHW,
 560   FeaturePCLMUL,
 561   FeatureMMX,
 562   FeatureAVX,
 563   FeatureSSE4A,
 564   FeatureF16C,
 565   FeatureLZCNT,
 566   FeaturePOPCNT,
 567   FeatureBMI,
 568   FeatureTBM,
 569   FeatureFMA,
 570   FeatureSlowSHLD
 571 ]>;
 572
 573 // Steamroller
 574 def : Proc<"bdver3", [
 575   FeatureXOP,
 576   FeatureFMA4,
 577   FeatureCMPXCHG16B,
 578   FeatureAES,
 579   FeaturePRFCHW,
 580   FeaturePCLMUL,
 581   FeatureMMX,
 582   FeatureAVX,
 583   FeatureSSE4A,
 584   FeatureF16C,
 585   FeatureLZCNT,
 586   FeaturePOPCNT,
 587   FeatureBMI,
 588   FeatureTBM,
 589   FeatureFMA,
 590   FeatureSlowSHLD,
 591   FeatureFSGSBase
 592 ]>;
 593
 594 // Excavator
 595 def : Proc<"bdver4", [
 596   FeatureMMX,
 597   FeatureAVX2,
 598   FeatureXOP,
 599   FeatureFMA4,
 600   FeatureCMPXCHG16B,
 601   FeatureAES,
 602   FeaturePRFCHW,
 603   FeaturePCLMUL,
 604   FeatureF16C,
 605   FeatureLZCNT,
 606   FeaturePOPCNT,
 607   FeatureBMI,
 608   FeatureBMI2,
 609   FeatureTBM,
 610   FeatureFMA,
 611   FeatureSSE4A,
 612   FeatureFSGSBase
 613 ]>;
 614
 615 def : Proc<"geode",           [FeatureSlowUAMem16, Feature3DNowA]>;
 616
 617 def : Proc<"winchip-c6",      [FeatureSlowUAMem16, FeatureMMX]>;
 618 def : Proc<"winchip2",        [FeatureSlowUAMem16, Feature3DNow]>;
 619 def : Proc<"c3",              [FeatureSlowUAMem16, Feature3DNow]>;
 620 def : Proc<"c3-2", [ FeatureSlowUAMem16, FeatureMMX, FeatureSSE1 ]>;
 621
 622 // We also provide a generic 64-bit specific x86 processor model which tries to
 623 // be good for modern chips without enabling instruction set encodings past the
 624 // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
 625 // modern 64-bit x86 chip, and enables features that are generally beneficial.
 626 //
 627 // We currently use the Sandy Bridge model as the default scheduling model as
 628 // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
 629 // covers a huge swath of x86 processors. If there are specific scheduling
 630 // knobs which need to be tuned differently for AMD chips, we might consider
 631 // forming a common base for them.
 632 def : ProcessorModel<
 633           "x86-64", SandyBridgeModel,
 634           [ FeatureMMX, FeatureSSE2, Feature64Bit, FeatureSlowBTMem ]>;
 635
 636 //===----------------------------------------------------------------------===//
 637 // Register File Description
 638 //===----------------------------------------------------------------------===//
 639
 640 include "X86RegisterInfo.td"
 641
 642 //===----------------------------------------------------------------------===//
 643 // Instruction Descriptions
 644 //===----------------------------------------------------------------------===//
 645
 646 include "X86InstrInfo.td"
 647
 648 def X86InstrInfo : InstrInfo;
 649
 650 //===----------------------------------------------------------------------===//
 651 // Calling Conventions
 652 //===----------------------------------------------------------------------===//
 653
 654 include "X86CallingConv.td"
 655
 656
 657 //===----------------------------------------------------------------------===//
 658 // Assembly Parser
 659 //===----------------------------------------------------------------------===//
 660
 661 def ATTAsmParser : AsmParser {
 662   string AsmParserClassName = "AsmParser";
 663 }
 664
 665 def ATTAsmParserVariant : AsmParserVariant {
 666   int Variant = 0;
 667
 668   // Variant name.
 669   string Name = "att";
 670
 671   // Discard comments in assembly strings.
 672   string CommentDelimiter = "#";
 673
 674   // Recognize hard coded registers.
 675   string RegisterPrefix = "%";
 676 }
 677
 678 def IntelAsmParserVariant : AsmParserVariant {
 679   int Variant = 1;
 680
 681   // Variant name.
 682   string Name = "intel";
 683
 684   // Discard comments in assembly strings.
 685   string CommentDelimiter = ";";
 686
 687   // Recognize hard coded registers.
 688   string RegisterPrefix = "";
 689 }
 690
 691 //===----------------------------------------------------------------------===//
 692 // Assembly Printers
 693 //===----------------------------------------------------------------------===//
 694
 695 // The X86 target supports two different syntaxes for emitting machine code.
 696 // This is controlled by the -x86-asm-syntax={att|intel}
 697 def ATTAsmWriter : AsmWriter {
 698   string AsmWriterClassName  = "ATTInstPrinter";
 699   int Variant = 0;
 700 }
 701 def IntelAsmWriter : AsmWriter {
 702   string AsmWriterClassName  = "IntelInstPrinter";
 703   int Variant = 1;
 704 }
 705
 706 def X86 : Target {
 707   // Information about the instructions...
 708   let InstructionSet = X86InstrInfo;
 709   let AssemblyParsers = [ATTAsmParser];
 710   let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
 711   let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
 712 }