1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is a target description file for the Intel i386 architecture, referred
11 // to here as the "X86" architecture.
13 //===----------------------------------------------------------------------===//
15 // Get the target-independent interfaces which we are implementing...
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // X86 Subtarget state
23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
24 "64-bit mode (x86_64)">;
26 //===----------------------------------------------------------------------===//
27 // X86 Subtarget features
28 //===----------------------------------------------------------------------===//
30 def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true",
31 "Enable conditional move instructions">;
33 def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
34 "Support POPCNT instruction">;
37 def FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX",
38 "Enable MMX instructions">;
39 def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
40 "Enable SSE instructions",
41 // SSE codegen depends on cmovs, and all
42 // SSE1+ processors support them.
43 [FeatureMMX, FeatureCMOV]>;
44 def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
45 "Enable SSE2 instructions",
47 def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
48 "Enable SSE3 instructions",
50 def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
51 "Enable SSSE3 instructions",
53 def FeatureSSE41 : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
54 "Enable SSE 4.1 instructions",
56 def FeatureSSE42 : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
57 "Enable SSE 4.2 instructions",
59 def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
60 "Enable 3DNow! instructions",
62 def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
63 "Enable 3DNow! Athlon instructions",
65 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
66 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
67 // without disabling 64-bit mode.
68 def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true",
69 "Support 64-bit instructions",
71 def FeatureCMPXCHG16B : SubtargetFeature<"cmpxchg16b", "HasCmpxchg16b", "true",
72 "64-bit with cmpxchg16b",
74 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
75 "Bit testing of memory is slow">;
76 def FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem",
77 "IsUAMemFast", "true",
78 "Fast unaligned memory access">;
79 def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true",
80 "Support SSE 4a instructions",
83 def FeatureAVX : SubtargetFeature<"avx", "X86SSELevel", "AVX",
84 "Enable AVX instructions",
86 def FeatureAVX2 : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
87 "Enable AVX2 instructions",
89 def FeatureAVX512 : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
90 "Enable AVX-512 instructions",
92 def FeatureERI : SubtargetFeature<"avx512er", "HasERI", "true",
93 "Enable AVX-512 Exponential and Reciprocal Instructions",
95 def FeatureCDI : SubtargetFeature<"avx512cd", "HasCDI", "true",
96 "Enable AVX-512 Conflict Detection Instructions",
98 def FeaturePFI : SubtargetFeature<"avx512pf", "HasPFI", "true",
99 "Enable AVX-512 PreFetch Instructions",
102 def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
103 "Enable packed carry-less multiplication instructions",
105 def FeatureFMA : SubtargetFeature<"fma", "HasFMA", "true",
106 "Enable three-operand fused multiple-add",
108 def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true",
109 "Enable four-operand fused multiple-add",
110 [FeatureAVX, FeatureSSE4A]>;
111 def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true",
112 "Enable XOP instructions",
114 def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
115 "HasVectorUAMem", "true",
116 "Allow unaligned memory operands on vector/SIMD instructions">;
117 def FeatureAES : SubtargetFeature<"aes", "HasAES", "true",
118 "Enable AES instructions",
120 def FeatureTBM : SubtargetFeature<"tbm", "HasTBM", "true",
121 "Enable TBM instructions">;
122 def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true",
123 "Support MOVBE instruction">;
124 def FeatureRDRAND : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
125 "Support RDRAND instruction">;
126 def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true",
127 "Support 16-bit floating point conversion instructions",
129 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
130 "Support FS/GS Base instructions">;
131 def FeatureLZCNT : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
132 "Support LZCNT instruction">;
133 def FeatureBMI : SubtargetFeature<"bmi", "HasBMI", "true",
134 "Support BMI instructions">;
135 def FeatureBMI2 : SubtargetFeature<"bmi2", "HasBMI2", "true",
136 "Support BMI2 instructions">;
137 def FeatureRTM : SubtargetFeature<"rtm", "HasRTM", "true",
138 "Support RTM instructions">;
139 def FeatureHLE : SubtargetFeature<"hle", "HasHLE", "true",
141 def FeatureADX : SubtargetFeature<"adx", "HasADX", "true",
142 "Support ADX instructions">;
143 def FeatureSHA : SubtargetFeature<"sha", "HasSHA", "true",
144 "Enable SHA instructions",
146 def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
147 "Support PRFCHW instructions">;
148 def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true",
149 "Support RDSEED instruction">;
150 def FeatureLeaForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
151 "Use LEA for adjusting the stack pointer">;
152 def FeatureSlowDivide : SubtargetFeature<"idiv-to-divb",
153 "HasSlowDivide", "true",
154 "Use small divide for positive values less than 256">;
155 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
156 "PadShortFunctions", "true",
157 "Pad short functions">;
158 def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect",
159 "CallRegIndirect", "true",
160 "Call register indirect">;
161 def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
162 "LEA instruction needs inputs at AG stage">;
164 //===----------------------------------------------------------------------===//
165 // X86 processors supported.
166 //===----------------------------------------------------------------------===//
168 include "X86Schedule.td"
170 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
171 "Intel Atom processors">;
172 def ProcIntelSLM : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM",
173 "Intel Silvermont processors">;
175 class Proc<string Name, list<SubtargetFeature> Features>
176 : ProcessorModel<Name, GenericModel, Features>;
178 def : Proc<"generic", []>;
179 def : Proc<"i386", []>;
180 def : Proc<"i486", []>;
181 def : Proc<"i586", []>;
182 def : Proc<"pentium", []>;
183 def : Proc<"pentium-mmx", [FeatureMMX]>;
184 def : Proc<"i686", []>;
185 def : Proc<"pentiumpro", [FeatureCMOV]>;
186 def : Proc<"pentium2", [FeatureMMX, FeatureCMOV]>;
187 def : Proc<"pentium3", [FeatureSSE1]>;
188 def : Proc<"pentium3m", [FeatureSSE1, FeatureSlowBTMem]>;
189 def : Proc<"pentium-m", [FeatureSSE2, FeatureSlowBTMem]>;
190 def : Proc<"pentium4", [FeatureSSE2]>;
191 def : Proc<"pentium4m", [FeatureSSE2, FeatureSlowBTMem]>;
192 def : Proc<"x86-64", [FeatureSSE2, Feature64Bit, FeatureSlowBTMem,
195 def : ProcessorModel<"yonah", SandyBridgeModel,
196 [FeatureSSE3, FeatureSlowBTMem]>;
199 def : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>;
200 def : Proc<"nocona", [FeatureSSE3, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
202 // Intel Core 2 Solo/Duo.
203 def : ProcessorModel<"core2", SandyBridgeModel,
204 [FeatureSSSE3, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
205 def : ProcessorModel<"penryn", SandyBridgeModel,
206 [FeatureSSE41, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
209 def : ProcessorModel<"atom", AtomModel,
210 [ProcIntelAtom, FeatureSSSE3, FeatureCMPXCHG16B,
211 FeatureMOVBE, FeatureSlowBTMem, FeatureLeaForSP,
213 FeatureCallRegIndirect,
215 FeaturePadShortFunctions]>;
218 def : ProcessorModel<"slm", SLMModel, [ProcIntelSLM,
219 FeatureSSE42, FeatureCMPXCHG16B,
220 FeatureMOVBE, FeaturePOPCNT,
221 FeaturePCLMUL, FeatureAES,
222 FeatureCallRegIndirect,
225 // "Arrandale" along with corei3 and corei5
226 def : ProcessorModel<"corei7", SandyBridgeModel,
227 [FeatureSSE42, FeatureCMPXCHG16B, FeatureSlowBTMem,
228 FeatureFastUAMem, FeaturePOPCNT, FeatureAES]>;
230 def : ProcessorModel<"nehalem", SandyBridgeModel,
231 [FeatureSSE42, FeatureCMPXCHG16B, FeatureSlowBTMem,
232 FeatureFastUAMem, FeaturePOPCNT]>;
233 // Westmere is a similar machine to nehalem with some additional features.
234 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
235 def : ProcessorModel<"westmere", SandyBridgeModel,
236 [FeatureSSE42, FeatureCMPXCHG16B, FeatureSlowBTMem,
237 FeatureFastUAMem, FeaturePOPCNT, FeatureAES,
240 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
241 // rather than a superset.
242 def : ProcessorModel<"corei7-avx", SandyBridgeModel,
243 [FeatureAVX, FeatureCMPXCHG16B, FeatureFastUAMem,
244 FeaturePOPCNT, FeatureAES, FeaturePCLMUL]>;
246 def : ProcessorModel<"core-avx-i", SandyBridgeModel,
247 [FeatureAVX, FeatureCMPXCHG16B, FeatureFastUAMem,
248 FeaturePOPCNT, FeatureAES, FeaturePCLMUL, FeatureRDRAND,
249 FeatureF16C, FeatureFSGSBase]>;
252 def : ProcessorModel<"core-avx2", HaswellModel,
253 [FeatureAVX2, FeatureCMPXCHG16B, FeatureFastUAMem,
254 FeaturePOPCNT, FeatureAES, FeaturePCLMUL, FeatureRDRAND,
255 FeatureF16C, FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT,
256 FeatureBMI, FeatureBMI2, FeatureFMA, FeatureRTM,
260 // FIXME: define KNL model
261 def : ProcessorModel<"knl", HaswellModel,
262 [FeatureAVX512, FeatureERI, FeatureCDI, FeaturePFI,
263 FeatureCMPXCHG16B, FeatureFastUAMem, FeaturePOPCNT,
264 FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C,
265 FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI,
266 FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE]>;
268 def : Proc<"k6", [FeatureMMX]>;
269 def : Proc<"k6-2", [Feature3DNow]>;
270 def : Proc<"k6-3", [Feature3DNow]>;
271 def : Proc<"athlon", [Feature3DNowA, FeatureSlowBTMem]>;
272 def : Proc<"athlon-tbird", [Feature3DNowA, FeatureSlowBTMem]>;
273 def : Proc<"athlon-4", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
274 def : Proc<"athlon-xp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
275 def : Proc<"athlon-mp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
276 def : Proc<"k8", [FeatureSSE2, Feature3DNowA, Feature64Bit,
278 def : Proc<"opteron", [FeatureSSE2, Feature3DNowA, Feature64Bit,
280 def : Proc<"athlon64", [FeatureSSE2, Feature3DNowA, Feature64Bit,
282 def : Proc<"athlon-fx", [FeatureSSE2, Feature3DNowA, Feature64Bit,
284 def : Proc<"k8-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
286 def : Proc<"opteron-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
288 def : Proc<"athlon64-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
290 def : Proc<"amdfam10", [FeatureSSE4A,
291 Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
292 FeaturePOPCNT, FeatureSlowBTMem]>;
294 def : Proc<"btver1", [FeatureSSSE3, FeatureSSE4A, FeatureCMPXCHG16B,
295 FeatureLZCNT, FeaturePOPCNT]>;
297 def : Proc<"btver2", [FeatureAVX, FeatureSSE4A, FeatureCMPXCHG16B,
298 FeatureAES, FeaturePCLMUL, FeatureBMI,
299 FeatureF16C, FeatureMOVBE, FeatureLZCNT,
302 def : Proc<"bdver1", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
303 FeatureAES, FeaturePCLMUL,
304 FeatureLZCNT, FeaturePOPCNT]>;
306 def : Proc<"bdver2", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
307 FeatureAES, FeaturePCLMUL,
308 FeatureF16C, FeatureLZCNT,
309 FeaturePOPCNT, FeatureBMI, FeatureTBM,
311 def : Proc<"geode", [Feature3DNowA]>;
313 def : Proc<"winchip-c6", [FeatureMMX]>;
314 def : Proc<"winchip2", [Feature3DNow]>;
315 def : Proc<"c3", [Feature3DNow]>;
316 def : Proc<"c3-2", [FeatureSSE1]>;
318 //===----------------------------------------------------------------------===//
319 // Register File Description
320 //===----------------------------------------------------------------------===//
322 include "X86RegisterInfo.td"
324 //===----------------------------------------------------------------------===//
325 // Instruction Descriptions
326 //===----------------------------------------------------------------------===//
328 include "X86InstrInfo.td"
330 def X86InstrInfo : InstrInfo;
332 //===----------------------------------------------------------------------===//
333 // Calling Conventions
334 //===----------------------------------------------------------------------===//
336 include "X86CallingConv.td"
339 //===----------------------------------------------------------------------===//
341 //===----------------------------------------------------------------------===//
343 def ATTAsmParser : AsmParser {
344 string AsmParserClassName = "AsmParser";
347 def ATTAsmParserVariant : AsmParserVariant {
353 // Discard comments in assembly strings.
354 string CommentDelimiter = "#";
356 // Recognize hard coded registers.
357 string RegisterPrefix = "%";
360 def IntelAsmParserVariant : AsmParserVariant {
364 string Name = "intel";
366 // Discard comments in assembly strings.
367 string CommentDelimiter = ";";
369 // Recognize hard coded registers.
370 string RegisterPrefix = "";
373 //===----------------------------------------------------------------------===//
375 //===----------------------------------------------------------------------===//
377 // The X86 target supports two different syntaxes for emitting machine code.
378 // This is controlled by the -x86-asm-syntax={att|intel}
379 def ATTAsmWriter : AsmWriter {
380 string AsmWriterClassName = "ATTInstPrinter";
382 bit isMCAsmWriter = 1;
384 def IntelAsmWriter : AsmWriter {
385 string AsmWriterClassName = "IntelInstPrinter";
387 bit isMCAsmWriter = 1;
391 // Information about the instructions...
392 let InstructionSet = X86InstrInfo;
393 let AssemblyParsers = [ATTAsmParser];
394 let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
395 let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];