lib/Target/X86/X86.td

   1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is a target description file for the Intel i386 architecture, referred
  11 // to here as the "X86" architecture.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 // Get the target-independent interfaces which we are implementing...
  16 //
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // X86 Subtarget state
  21 //
  22
  23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
  24                                   "64-bit mode (x86_64)">;
  25 def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",
  26                                   "32-bit mode (80386)">;
  27 def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
  28                                   "16-bit mode (i8086)">;
  29
  30 //===----------------------------------------------------------------------===//
  31 // X86 Subtarget features
  32 //===----------------------------------------------------------------------===//
  33
  34 def FeatureCMOV    : SubtargetFeature<"cmov","HasCMov", "true",
  35                                       "Enable conditional move instructions">;
  36
  37 def FeaturePOPCNT   : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
  38                                        "Support POPCNT instruction">;
  39
  40
  41 def FeatureMMX     : SubtargetFeature<"mmx","X86SSELevel", "MMX",
  42                                       "Enable MMX instructions">;
  43 def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
  44                                       "Enable SSE instructions",
  45                                       // SSE codegen depends on cmovs, and all
  46                                       // SSE1+ processors support them.
  47                                       [FeatureMMX, FeatureCMOV]>;
  48 def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
  49                                       "Enable SSE2 instructions",
  50                                       [FeatureSSE1]>;
  51 def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
  52                                       "Enable SSE3 instructions",
  53                                       [FeatureSSE2]>;
  54 def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
  55                                       "Enable SSSE3 instructions",
  56                                       [FeatureSSE3]>;
  57 def FeatureSSE41   : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
  58                                       "Enable SSE 4.1 instructions",
  59                                       [FeatureSSSE3]>;
  60 def FeatureSSE42   : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
  61                                       "Enable SSE 4.2 instructions",
  62                                       [FeatureSSE41]>;
  63 def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
  64                                       "Enable 3DNow! instructions",
  65                                       [FeatureMMX]>;
  66 def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
  67                                       "Enable 3DNow! Athlon instructions",
  68                                       [Feature3DNow]>;
  69 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
  70 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
  71 // without disabling 64-bit mode.
  72 def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
  73                                       "Support 64-bit instructions",
  74                                       [FeatureCMOV]>;
  75 def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
  76                                       "64-bit with cmpxchg16b",
  77                                       [Feature64Bit]>;
  78 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
  79                                        "Bit testing of memory is slow">;
  80 def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
  81                                        "SHLD instruction is slow">;
  82 def FeatureSlowUAMem : SubtargetFeature<"slow-unaligned-mem-under-32",
  83                                 "IsUAMemUnder32Slow", "true",
  84                                 "Slow unaligned 16-byte-or-less memory access">;
  85 def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
  86                                 "IsUAMem32Slow", "true",
  87                                 "Slow unaligned 32-byte memory access">;
  88 def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
  89                                       "Support SSE 4a instructions",
  90                                       [FeatureSSE3]>;
  91
  92 def FeatureAVX     : SubtargetFeature<"avx", "X86SSELevel", "AVX",
  93                                       "Enable AVX instructions",
  94                                       [FeatureSSE42]>;
  95 def FeatureAVX2    : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
  96                                       "Enable AVX2 instructions",
  97                                       [FeatureAVX]>;
  98 def FeatureAVX512   : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
  99                                       "Enable AVX-512 instructions",
 100                                       [FeatureAVX2]>;
 101 def FeatureERI      : SubtargetFeature<"avx512er", "HasERI", "true",
 102                       "Enable AVX-512 Exponential and Reciprocal Instructions",
 103                                       [FeatureAVX512]>;
 104 def FeatureCDI      : SubtargetFeature<"avx512cd", "HasCDI", "true",
 105                       "Enable AVX-512 Conflict Detection Instructions",
 106                                       [FeatureAVX512]>;
 107 def FeaturePFI      : SubtargetFeature<"avx512pf", "HasPFI", "true",
 108                       "Enable AVX-512 PreFetch Instructions",
 109                                       [FeatureAVX512]>;
 110 def FeatureDQI     : SubtargetFeature<"avx512dq", "HasDQI", "true",
 111                       "Enable AVX-512 Doubleword and Quadword Instructions",
 112                                       [FeatureAVX512]>;
 113 def FeatureBWI     : SubtargetFeature<"avx512bw", "HasBWI", "true",
 114                       "Enable AVX-512 Byte and Word Instructions",
 115                                       [FeatureAVX512]>;
 116 def FeatureVLX     : SubtargetFeature<"avx512vl", "HasVLX", "true",
 117                       "Enable AVX-512 Vector Length eXtensions",
 118                                       [FeatureAVX512]>;
 119 def FeaturePCLMUL  : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
 120                          "Enable packed carry-less multiplication instructions",
 121                                [FeatureSSE2]>;
 122 def FeatureFMA     : SubtargetFeature<"fma", "HasFMA", "true",
 123                                       "Enable three-operand fused multiple-add",
 124                                       [FeatureAVX]>;
 125 def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
 126                                       "Enable four-operand fused multiple-add",
 127                                       [FeatureAVX, FeatureSSE4A]>;
 128 def FeatureXOP     : SubtargetFeature<"xop", "HasXOP", "true",
 129                                       "Enable XOP instructions",
 130                                       [FeatureFMA4]>;
 131 def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem",
 132                                           "HasSSEUnalignedMem", "true",
 133                       "Allow unaligned memory operands with SSE instructions">;
 134 def FeatureAES     : SubtargetFeature<"aes", "HasAES", "true",
 135                                       "Enable AES instructions",
 136                                       [FeatureSSE2]>;
 137 def FeatureTBM     : SubtargetFeature<"tbm", "HasTBM", "true",
 138                                       "Enable TBM instructions">;
 139 def FeatureMOVBE   : SubtargetFeature<"movbe", "HasMOVBE", "true",
 140                                       "Support MOVBE instruction">;
 141 def FeatureRDRAND  : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
 142                                       "Support RDRAND instruction">;
 143 def FeatureF16C    : SubtargetFeature<"f16c", "HasF16C", "true",
 144                        "Support 16-bit floating point conversion instructions",
 145                        [FeatureAVX]>;
 146 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
 147                                        "Support FS/GS Base instructions">;
 148 def FeatureLZCNT   : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
 149                                       "Support LZCNT instruction">;
 150 def FeatureBMI     : SubtargetFeature<"bmi", "HasBMI", "true",
 151                                       "Support BMI instructions">;
 152 def FeatureBMI2    : SubtargetFeature<"bmi2", "HasBMI2", "true",
 153                                       "Support BMI2 instructions">;
 154 def FeatureRTM     : SubtargetFeature<"rtm", "HasRTM", "true",
 155                                       "Support RTM instructions">;
 156 def FeatureHLE     : SubtargetFeature<"hle", "HasHLE", "true",
 157                                       "Support HLE">;
 158 def FeatureADX     : SubtargetFeature<"adx", "HasADX", "true",
 159                                       "Support ADX instructions">;
 160 def FeatureSHA     : SubtargetFeature<"sha", "HasSHA", "true",
 161                                       "Enable SHA instructions",
 162                                       [FeatureSSE2]>;
 163 def FeaturePRFCHW  : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
 164                                       "Support PRFCHW instructions">;
 165 def FeatureRDSEED  : SubtargetFeature<"rdseed", "HasRDSEED", "true",
 166                                       "Support RDSEED instruction">;
 167 def FeatureMPX     : SubtargetFeature<"mpx", "HasMPX", "true",
 168                                       "Support MPX instructions">;
 169 def FeatureLeaForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
 170                                      "Use LEA for adjusting the stack pointer">;
 171 def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
 172                                      "HasSlowDivide32", "true",
 173                                      "Use 8-bit divide for positive values less than 256">;
 174 def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divw",
 175                                      "HasSlowDivide64", "true",
 176                                      "Use 16-bit divide for positive values less than 65536">;
 177 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
 178                                      "PadShortFunctions", "true",
 179                                      "Pad short functions">;
 180 // TODO: This feature ought to be renamed.
 181 // What it really refers to are CPUs for which certain instructions
 182 // (which ones besides the example below?) are microcoded.
 183 // The best examples of this are the memory forms of CALL and PUSH
 184 // instructions, which should be avoided in favor of a MOV + register CALL/PUSH.
 185 def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect",
 186                                      "CallRegIndirect", "true",
 187                                      "Call register indirect">;
 188 def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
 189                                    "LEA instruction needs inputs at AG stage">;
 190 def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
 191                                    "LEA instruction with certain arguments is slow">;
 192 def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
 193                                    "INC and DEC instructions are slower than ADD and SUB">;
 194 def FeatureSoftFloat
 195     : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
 196                        "Use software floating point features.">;
 197
 198 //===----------------------------------------------------------------------===//
 199 // X86 processors supported.
 200 //===----------------------------------------------------------------------===//
 201
 202 include "X86Schedule.td"
 203
 204 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
 205                     "Intel Atom processors">;
 206 def ProcIntelSLM  : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM",
 207                     "Intel Silvermont processors">;
 208
 209 class Proc<string Name, list<SubtargetFeature> Features>
 210  : ProcessorModel<Name, GenericModel, Features>;
 211
 212 def : Proc<"generic",         [FeatureSlowUAMem]>;
 213 def : Proc<"i386",            [FeatureSlowUAMem]>;
 214 def : Proc<"i486",            [FeatureSlowUAMem]>;
 215 def : Proc<"i586",            [FeatureSlowUAMem]>;
 216 def : Proc<"pentium",         [FeatureSlowUAMem]>;
 217 def : Proc<"pentium-mmx",     [FeatureSlowUAMem, FeatureMMX]>;
 218 def : Proc<"i686",            [FeatureSlowUAMem]>;
 219 def : Proc<"pentiumpro",      [FeatureSlowUAMem, FeatureCMOV]>;
 220 def : Proc<"pentium2",        [FeatureSlowUAMem, FeatureMMX, FeatureCMOV]>;
 221 def : Proc<"pentium3",        [FeatureSlowUAMem, FeatureSSE1]>;
 222 def : Proc<"pentium3m",       [FeatureSlowUAMem, FeatureSSE1, FeatureSlowBTMem]>;
 223 def : Proc<"pentium-m",       [FeatureSlowUAMem, FeatureSSE2, FeatureSlowBTMem]>;
 224 def : Proc<"pentium4",        [FeatureSlowUAMem, FeatureSSE2]>;
 225 def : Proc<"pentium4m",       [FeatureSlowUAMem, FeatureSSE2, FeatureSlowBTMem]>;
 226
 227 // Intel Core Duo.
 228 def : ProcessorModel<"yonah", SandyBridgeModel,
 229                      [FeatureSlowUAMem, FeatureSSE3, FeatureSlowBTMem]>;
 230
 231 // NetBurst.
 232 def : Proc<"prescott", [FeatureSlowUAMem, FeatureSSE3, FeatureSlowBTMem]>;
 233 def : Proc<"nocona",   [FeatureSlowUAMem, FeatureSSE3, FeatureCMPXCHG16B,
 234                         FeatureSlowBTMem]>;
 235
 236 // Intel Core 2 Solo/Duo.
 237 def : ProcessorModel<"core2", SandyBridgeModel,
 238                      [FeatureSlowUAMem, FeatureSSSE3, FeatureCMPXCHG16B,
 239                       FeatureSlowBTMem]>;
 240 def : ProcessorModel<"penryn", SandyBridgeModel,
 241                      [FeatureSlowUAMem, FeatureSSE41, FeatureCMPXCHG16B,
 242                       FeatureSlowBTMem]>;
 243
 244 // Atom CPUs.
 245 class BonnellProc<string Name> : ProcessorModel<Name, AtomModel, [
 246                                    ProcIntelAtom,
 247                                    FeatureSlowUAMem,
 248                                    FeatureSSSE3,
 249                                    FeatureCMPXCHG16B,
 250                                    FeatureMOVBE,
 251                                    FeatureSlowBTMem,
 252                                    FeatureLeaForSP,
 253                                    FeatureSlowDivide32,
 254                                    FeatureSlowDivide64,
 255                                    FeatureCallRegIndirect,
 256                                    FeatureLEAUsesAG,
 257                                    FeaturePadShortFunctions
 258                                  ]>;
 259 def : BonnellProc<"bonnell">;
 260 def : BonnellProc<"atom">; // Pin the generic name to the baseline.
 261
 262 class SilvermontProc<string Name> : ProcessorModel<Name, SLMModel, [
 263                                       ProcIntelSLM,
 264                                       FeatureSSE42,
 265                                       FeatureCMPXCHG16B,
 266                                       FeatureMOVBE,
 267                                       FeaturePOPCNT,
 268                                       FeaturePCLMUL,
 269                                       FeatureAES,
 270                                       FeatureSlowDivide64,
 271                                       FeatureCallRegIndirect,
 272                                       FeaturePRFCHW,
 273                                       FeatureSlowLEA,
 274                                       FeatureSlowIncDec,
 275                                       FeatureSlowBTMem
 276                                     ]>;
 277 def : SilvermontProc<"silvermont">;
 278 def : SilvermontProc<"slm">; // Legacy alias.
 279
 280 // "Arrandale" along with corei3 and corei5
 281 class NehalemProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 282                                    FeatureSSE42,
 283                                    FeatureCMPXCHG16B,
 284                                    FeatureSlowBTMem,
 285                                    FeaturePOPCNT
 286                                  ]>;
 287 def : NehalemProc<"nehalem">;
 288 def : NehalemProc<"corei7">;
 289
 290 // Westmere is a similar machine to nehalem with some additional features.
 291 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
 292 class WestmereProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 293                                     FeatureSSE42,
 294                                     FeatureCMPXCHG16B,
 295                                     FeatureSlowBTMem,
 296                                     FeaturePOPCNT,
 297                                     FeatureAES,
 298                                     FeaturePCLMUL
 299                                   ]>;
 300 def : WestmereProc<"westmere">;
 301
 302 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
 303 // rather than a superset.
 304 class SandyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 305                                        FeatureAVX,
 306                                        FeatureCMPXCHG16B,
 307                                        FeatureSlowBTMem,
 308                                        FeatureSlowUAMem32,
 309                                        FeaturePOPCNT,
 310                                        FeatureAES,
 311                                        FeaturePCLMUL
 312                                      ]>;
 313 def : SandyBridgeProc<"sandybridge">;
 314 def : SandyBridgeProc<"corei7-avx">; // Legacy alias.
 315
 316 class IvyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 317                                      FeatureAVX,
 318                                      FeatureCMPXCHG16B,
 319                                      FeatureSlowBTMem,
 320                                      FeatureSlowUAMem32,
 321                                      FeaturePOPCNT,
 322                                      FeatureAES,
 323                                      FeaturePCLMUL,
 324                                      FeatureRDRAND,
 325                                      FeatureF16C,
 326                                      FeatureFSGSBase
 327                                    ]>;
 328 def : IvyBridgeProc<"ivybridge">;
 329 def : IvyBridgeProc<"core-avx-i">; // Legacy alias.
 330
 331 class HaswellProc<string Name> : ProcessorModel<Name, HaswellModel, [
 332                                    FeatureAVX2,
 333                                    FeatureCMPXCHG16B,
 334                                    FeatureSlowBTMem,
 335                                    FeaturePOPCNT,
 336                                    FeatureAES,
 337                                    FeaturePCLMUL,
 338                                    FeatureRDRAND,
 339                                    FeatureF16C,
 340                                    FeatureFSGSBase,
 341                                    FeatureMOVBE,
 342                                    FeatureLZCNT,
 343                                    FeatureBMI,
 344                                    FeatureBMI2,
 345                                    FeatureFMA,
 346                                    FeatureRTM,
 347                                    FeatureHLE,
 348                                    FeatureSlowIncDec
 349                                  ]>;
 350 def : HaswellProc<"haswell">;
 351 def : HaswellProc<"core-avx2">; // Legacy alias.
 352
 353 class BroadwellProc<string Name> : ProcessorModel<Name, HaswellModel, [
 354                                      FeatureAVX2,
 355                                      FeatureCMPXCHG16B,
 356                                      FeatureSlowBTMem,
 357                                      FeaturePOPCNT,
 358                                      FeatureAES,
 359                                      FeaturePCLMUL,
 360                                      FeatureRDRAND,
 361                                      FeatureF16C,
 362                                      FeatureFSGSBase,
 363                                      FeatureMOVBE,
 364                                      FeatureLZCNT,
 365                                      FeatureBMI,
 366                                      FeatureBMI2,
 367                                      FeatureFMA,
 368                                      FeatureRTM,
 369                                      FeatureHLE,
 370                                      FeatureADX,
 371                                      FeatureRDSEED,
 372                                      FeatureSlowIncDec
 373                                    ]>;
 374 def : BroadwellProc<"broadwell">;
 375
 376 // FIXME: define KNL model
 377 class KnightsLandingProc<string Name> : ProcessorModel<Name, HaswellModel,
 378                      [FeatureAVX512, FeatureERI, FeatureCDI, FeaturePFI,
 379                       FeatureCMPXCHG16B, FeaturePOPCNT,
 380                       FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C,
 381                       FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI,
 382                       FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE,
 383                       FeatureSlowIncDec, FeatureMPX]>;
 384 def : KnightsLandingProc<"knl">;
 385
 386 // FIXME: define SKX model
 387 class SkylakeProc<string Name> : ProcessorModel<Name, HaswellModel,
 388                      [FeatureAVX512, FeatureCDI,
 389                       FeatureDQI, FeatureBWI, FeatureVLX,
 390                       FeatureCMPXCHG16B, FeatureSlowBTMem,
 391                       FeaturePOPCNT, FeatureAES, FeaturePCLMUL, FeatureRDRAND,
 392                       FeatureF16C, FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT,
 393                       FeatureBMI, FeatureBMI2, FeatureFMA, FeatureRTM,
 394                       FeatureHLE, FeatureADX, FeatureRDSEED, FeatureSlowIncDec,
 395                       FeatureMPX]>;
 396 def : SkylakeProc<"skylake">;
 397 def : SkylakeProc<"skx">; // Legacy alias.
 398
 399
 400 // AMD CPUs.
 401
 402 def : Proc<"k6",              [FeatureSlowUAMem, FeatureMMX]>;
 403 def : Proc<"k6-2",            [FeatureSlowUAMem, Feature3DNow]>;
 404 def : Proc<"k6-3",            [FeatureSlowUAMem, Feature3DNow]>;
 405 def : Proc<"athlon",          [FeatureSlowUAMem, Feature3DNowA,
 406                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 407 def : Proc<"athlon-tbird",    [FeatureSlowUAMem, Feature3DNowA,
 408                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 409 def : Proc<"athlon-4",        [FeatureSlowUAMem, FeatureSSE1, Feature3DNowA,
 410                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 411 def : Proc<"athlon-xp",       [FeatureSlowUAMem, FeatureSSE1, Feature3DNowA,
 412                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 413 def : Proc<"athlon-mp",       [FeatureSlowUAMem, FeatureSSE1, Feature3DNowA,
 414                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 415 def : Proc<"k8",              [FeatureSlowUAMem, FeatureSSE2, Feature3DNowA,
 416                                Feature64Bit, FeatureSlowBTMem,
 417                                FeatureSlowSHLD]>;
 418 def : Proc<"opteron",         [FeatureSlowUAMem, FeatureSSE2, Feature3DNowA,
 419                                Feature64Bit, FeatureSlowBTMem,
 420                                FeatureSlowSHLD]>;
 421 def : Proc<"athlon64",        [FeatureSlowUAMem, FeatureSSE2,   Feature3DNowA,
 422                                Feature64Bit, FeatureSlowBTMem,
 423                                FeatureSlowSHLD]>;
 424 def : Proc<"athlon-fx",       [FeatureSlowUAMem, FeatureSSE2,   Feature3DNowA,
 425                                Feature64Bit, FeatureSlowBTMem,
 426                                FeatureSlowSHLD]>;
 427 def : Proc<"k8-sse3",         [FeatureSlowUAMem, FeatureSSE3,   Feature3DNowA,
 428                                FeatureCMPXCHG16B, FeatureSlowBTMem,
 429                                FeatureSlowSHLD]>;
 430 def : Proc<"opteron-sse3",    [FeatureSlowUAMem, FeatureSSE3,   Feature3DNowA,
 431                                FeatureCMPXCHG16B, FeatureSlowBTMem,
 432                                FeatureSlowSHLD]>;
 433 def : Proc<"athlon64-sse3",   [FeatureSlowUAMem, FeatureSSE3,   Feature3DNowA,
 434                                FeatureCMPXCHG16B, FeatureSlowBTMem,
 435                                FeatureSlowSHLD]>;
 436 def : Proc<"amdfam10",        [FeatureSSE4A,
 437                                Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
 438                                FeaturePOPCNT, FeatureSlowBTMem,
 439                                FeatureSlowSHLD]>;
 440 def : Proc<"barcelona",       [FeatureSSE4A,
 441                                Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
 442                                FeaturePOPCNT, FeatureSlowBTMem,
 443                                FeatureSlowSHLD]>;
 444
 445 // Bobcat
 446 def : Proc<"btver1",          [FeatureSSSE3, FeatureSSE4A, FeatureCMPXCHG16B,
 447                                FeaturePRFCHW, FeatureLZCNT, FeaturePOPCNT,
 448                                FeatureSlowSHLD]>;
 449
 450 // Jaguar
 451 def : ProcessorModel<"btver2", BtVer2Model,
 452                      [FeatureAVX, FeatureSSE4A, FeatureCMPXCHG16B,
 453                       FeaturePRFCHW, FeatureAES, FeaturePCLMUL,
 454                       FeatureBMI, FeatureF16C, FeatureMOVBE,
 455                       FeatureLZCNT, FeaturePOPCNT,
 456                       FeatureSlowSHLD]>;
 457
 458 // Bulldozer
 459 def : Proc<"bdver1",          [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
 460                                FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
 461                                FeatureAVX, FeatureSSE4A, FeatureLZCNT,
 462                                FeaturePOPCNT, FeatureSlowSHLD]>;
 463 // Piledriver
 464 def : Proc<"bdver2",          [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
 465                                FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
 466                                FeatureAVX, FeatureSSE4A, FeatureF16C,
 467                                FeatureLZCNT, FeaturePOPCNT, FeatureBMI,
 468                                FeatureTBM, FeatureFMA, FeatureSlowSHLD]>;
 469
 470 // Steamroller
 471 def : Proc<"bdver3",          [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
 472                                FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
 473                                FeatureAVX, FeatureSSE4A, FeatureF16C,
 474                                FeatureLZCNT, FeaturePOPCNT, FeatureBMI,
 475                                FeatureTBM, FeatureFMA, FeatureSlowSHLD,
 476                                FeatureFSGSBase]>;
 477
 478 // Excavator
 479 def : Proc<"bdver4",          [FeatureAVX2, FeatureXOP, FeatureFMA4,
 480                                FeatureCMPXCHG16B, FeatureAES, FeaturePRFCHW,
 481                                FeaturePCLMUL, FeatureF16C, FeatureLZCNT,
 482                                FeaturePOPCNT, FeatureBMI, FeatureBMI2,
 483                                FeatureTBM, FeatureFMA, FeatureSSE4A,
 484                                FeatureFSGSBase]>;
 485
 486 def : Proc<"geode",           [FeatureSlowUAMem, Feature3DNowA]>;
 487
 488 def : Proc<"winchip-c6",      [FeatureSlowUAMem, FeatureMMX]>;
 489 def : Proc<"winchip2",        [FeatureSlowUAMem, Feature3DNow]>;
 490 def : Proc<"c3",              [FeatureSlowUAMem, Feature3DNow]>;
 491 def : Proc<"c3-2",            [FeatureSlowUAMem, FeatureSSE1]>;
 492
 493 // We also provide a generic 64-bit specific x86 processor model which tries to
 494 // be good for modern chips without enabling instruction set encodings past the
 495 // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
 496 // modern 64-bit x86 chip, and enables features that are generally beneficial.
 497 //
 498 // We currently use the Sandy Bridge model as the default scheduling model as
 499 // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
 500 // covers a huge swath of x86 processors. If there are specific scheduling
 501 // knobs which need to be tuned differently for AMD chips, we might consider
 502 // forming a common base for them.
 503 def : ProcessorModel<"x86-64", SandyBridgeModel,
 504                      [FeatureSSE2, Feature64Bit, FeatureSlowBTMem]>;
 505
 506 //===----------------------------------------------------------------------===//
 507 // Register File Description
 508 //===----------------------------------------------------------------------===//
 509
 510 include "X86RegisterInfo.td"
 511
 512 //===----------------------------------------------------------------------===//
 513 // Instruction Descriptions
 514 //===----------------------------------------------------------------------===//
 515
 516 include "X86InstrInfo.td"
 517
 518 def X86InstrInfo : InstrInfo;
 519
 520 //===----------------------------------------------------------------------===//
 521 // Calling Conventions
 522 //===----------------------------------------------------------------------===//
 523
 524 include "X86CallingConv.td"
 525
 526
 527 //===----------------------------------------------------------------------===//
 528 // Assembly Parser
 529 //===----------------------------------------------------------------------===//
 530
 531 def ATTAsmParser : AsmParser {
 532   string AsmParserClassName = "AsmParser";
 533 }
 534
 535 def ATTAsmParserVariant : AsmParserVariant {
 536   int Variant = 0;
 537
 538   // Variant name.
 539   string Name = "att";
 540
 541   // Discard comments in assembly strings.
 542   string CommentDelimiter = "#";
 543
 544   // Recognize hard coded registers.
 545   string RegisterPrefix = "%";
 546 }
 547
 548 def IntelAsmParserVariant : AsmParserVariant {
 549   int Variant = 1;
 550
 551   // Variant name.
 552   string Name = "intel";
 553
 554   // Discard comments in assembly strings.
 555   string CommentDelimiter = ";";
 556
 557   // Recognize hard coded registers.
 558   string RegisterPrefix = "";
 559 }
 560
 561 //===----------------------------------------------------------------------===//
 562 // Assembly Printers
 563 //===----------------------------------------------------------------------===//
 564
 565 // The X86 target supports two different syntaxes for emitting machine code.
 566 // This is controlled by the -x86-asm-syntax={att|intel}
 567 def ATTAsmWriter : AsmWriter {
 568   string AsmWriterClassName  = "ATTInstPrinter";
 569   int Variant = 0;
 570 }
 571 def IntelAsmWriter : AsmWriter {
 572   string AsmWriterClassName  = "IntelInstPrinter";
 573   int Variant = 1;
 574 }
 575
 576 def X86 : Target {
 577   // Information about the instructions...
 578   let InstructionSet = X86InstrInfo;
 579   let AssemblyParsers = [ATTAsmParser];
 580   let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
 581   let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
 582 }