1 //===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/Target/TargetAsmBackend.h"
12 #include "X86FixupKinds.h"
13 #include "llvm/ADT/Twine.h"
14 #include "llvm/MC/MCAssembler.h"
15 #include "llvm/MC/MCSectionELF.h"
16 #include "llvm/MC/MCSectionMachO.h"
17 #include "llvm/MC/MachObjectWriter.h"
18 #include "llvm/Support/ErrorHandling.h"
19 #include "llvm/Support/raw_ostream.h"
20 #include "llvm/Target/TargetRegistry.h"
21 #include "llvm/Target/TargetAsmBackend.h"
26 static unsigned getFixupKindLog2Size(unsigned Kind) {
28 default: assert(0 && "invalid fixup kind!");
29 case X86::reloc_pcrel_1byte:
30 case FK_Data_1: return 0;
31 case FK_Data_2: return 1;
32 case X86::reloc_pcrel_4byte:
33 case X86::reloc_riprel_4byte:
34 case X86::reloc_riprel_4byte_movq_load:
35 case FK_Data_4: return 2;
36 case FK_Data_8: return 3;
40 class X86AsmBackend : public TargetAsmBackend {
42 X86AsmBackend(const Target &T)
43 : TargetAsmBackend(T) {}
45 void ApplyFixup(const MCAsmFixup &Fixup, MCDataFragment &DF,
46 uint64_t Value) const {
47 unsigned Size = 1 << getFixupKindLog2Size(Fixup.Kind);
49 assert(Fixup.Offset + Size <= DF.getContents().size() &&
50 "Invalid fixup offset!");
51 for (unsigned i = 0; i != Size; ++i)
52 DF.getContents()[Fixup.Offset + i] = uint8_t(Value >> (i * 8));
55 void RelaxInstruction(const MCInstFragment *IF, MCInst &Res) const;
57 bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
60 static unsigned getRelaxedOpcode(unsigned Op) {
65 case X86::JAE_1: return X86::JAE_4;
66 case X86::JA_1: return X86::JA_4;
67 case X86::JBE_1: return X86::JBE_4;
68 case X86::JB_1: return X86::JB_4;
69 case X86::JE_1: return X86::JE_4;
70 case X86::JGE_1: return X86::JGE_4;
71 case X86::JG_1: return X86::JG_4;
72 case X86::JLE_1: return X86::JLE_4;
73 case X86::JL_1: return X86::JL_4;
74 case X86::JMP_1: return X86::JMP_4;
75 case X86::JNE_1: return X86::JNE_4;
76 case X86::JNO_1: return X86::JNO_4;
77 case X86::JNP_1: return X86::JNP_4;
78 case X86::JNS_1: return X86::JNS_4;
79 case X86::JO_1: return X86::JO_4;
80 case X86::JP_1: return X86::JP_4;
81 case X86::JS_1: return X86::JS_4;
85 // FIXME: Can tblgen help at all here to verify there aren't other instructions
87 void X86AsmBackend::RelaxInstruction(const MCInstFragment *IF,
89 // The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel.
90 unsigned RelaxedOp = getRelaxedOpcode(IF->getInst().getOpcode());
92 if (RelaxedOp == IF->getInst().getOpcode()) {
94 raw_svector_ostream OS(Tmp);
95 IF->getInst().dump_pretty(OS);
96 llvm_report_error("unexpected instruction to relax: " + OS.str());
100 Res.setOpcode(RelaxedOp);
103 /// WriteNopData - Write optimal nops to the output file for the \arg Count
104 /// bytes. This returns the number of bytes written. It may return 0 if
105 /// the \arg Count is more than the maximum optimal nops.
107 /// FIXME this is X86 32-bit specific and should move to a better place.
108 bool X86AsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
109 static const uint8_t Nops[16][16] = {
117 {0x0f, 0x1f, 0x40, 0x00},
118 // nopl 0(%[re]ax,%[re]ax,1)
119 {0x0f, 0x1f, 0x44, 0x00, 0x00},
120 // nopw 0(%[re]ax,%[re]ax,1)
121 {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
123 {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
124 // nopl 0L(%[re]ax,%[re]ax,1)
125 {0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
126 // nopw 0L(%[re]ax,%[re]ax,1)
127 {0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
128 // nopw %cs:0L(%[re]ax,%[re]ax,1)
129 {0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
130 // nopl 0(%[re]ax,%[re]ax,1)
131 // nopw 0(%[re]ax,%[re]ax,1)
132 {0x0f, 0x1f, 0x44, 0x00, 0x00,
133 0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
134 // nopw 0(%[re]ax,%[re]ax,1)
135 // nopw 0(%[re]ax,%[re]ax,1)
136 {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00,
137 0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
138 // nopw 0(%[re]ax,%[re]ax,1)
139 // nopl 0L(%[re]ax) */
140 {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00,
141 0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
144 {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00,
145 0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
147 // nopl 0L(%[re]ax,%[re]ax,1)
148 {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00,
149 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00}
152 // Write an optimal sequence for the first 15 bytes.
153 uint64_t OptimalCount = (Count < 16) ? Count : 15;
154 for (uint64_t i = 0, e = OptimalCount; i != e; i++)
155 OW->Write8(Nops[OptimalCount - 1][i]);
157 // Finish with single byte nops.
158 for (uint64_t i = OptimalCount, e = Count; i != e; ++i)
166 class ELFX86AsmBackend : public X86AsmBackend {
168 ELFX86AsmBackend(const Target &T)
170 HasAbsolutizedSet = true;
171 HasScatteredSymbols = true;
174 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
178 bool isVirtualSection(const MCSection &Section) const {
179 const MCSectionELF &SE = static_cast<const MCSectionELF&>(Section);
180 return SE.getType() == MCSectionELF::SHT_NOBITS;;
184 class DarwinX86AsmBackend : public X86AsmBackend {
186 DarwinX86AsmBackend(const Target &T)
188 HasAbsolutizedSet = true;
189 HasScatteredSymbols = true;
192 bool isVirtualSection(const MCSection &Section) const {
193 const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
194 return (SMO.getType() == MCSectionMachO::S_ZEROFILL ||
195 SMO.getType() == MCSectionMachO::S_GB_ZEROFILL);
199 class DarwinX86_32AsmBackend : public DarwinX86AsmBackend {
201 DarwinX86_32AsmBackend(const Target &T)
202 : DarwinX86AsmBackend(T) {}
204 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
205 return new MachObjectWriter(OS, /*Is64Bit=*/false);
209 class DarwinX86_64AsmBackend : public DarwinX86AsmBackend {
211 DarwinX86_64AsmBackend(const Target &T)
212 : DarwinX86AsmBackend(T) {
213 HasReliableSymbolDifference = true;
216 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
217 return new MachObjectWriter(OS, /*Is64Bit=*/true);
220 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
221 // Temporary labels in the string literals sections require symbols. The
222 // issue is that the x86_64 relocation format does not allow symbol +
223 // offset, and so the linker does not have enough information to resolve the
224 // access to the appropriate atom unless an external relocation is used. For
225 // non-cstring sections, we expect the compiler to use a non-temporary label
226 // for anything that could have an addend pointing outside the symbol.
228 // See <rdar://problem/4765733>.
229 const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
230 return SMO.getType() == MCSectionMachO::S_CSTRING_LITERALS;
236 TargetAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
237 const std::string &TT) {
238 switch (Triple(TT).getOS()) {
240 return new DarwinX86_32AsmBackend(T);
242 return new ELFX86AsmBackend(T);
246 TargetAsmBackend *llvm::createX86_64AsmBackend(const Target &T,
247 const std::string &TT) {
248 switch (Triple(TT).getOS()) {
250 return new DarwinX86_64AsmBackend(T);
252 return new ELFX86AsmBackend(T);