1 //===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/Target/TargetAsmBackend.h"
12 #include "X86FixupKinds.h"
13 #include "llvm/ADT/Twine.h"
14 #include "llvm/MC/MCAssembler.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCObjectWriter.h"
17 #include "llvm/MC/MCSectionELF.h"
18 #include "llvm/MC/MCSectionMachO.h"
19 #include "llvm/MC/MachObjectWriter.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/Support/raw_ostream.h"
22 #include "llvm/Target/TargetRegistry.h"
23 #include "llvm/Target/TargetAsmBackend.h"
28 static unsigned getFixupKindLog2Size(unsigned Kind) {
30 default: assert(0 && "invalid fixup kind!");
31 case X86::reloc_pcrel_1byte:
32 case FK_Data_1: return 0;
33 case FK_Data_2: return 1;
34 case X86::reloc_pcrel_4byte:
35 case X86::reloc_riprel_4byte:
36 case X86::reloc_riprel_4byte_movq_load:
37 case FK_Data_4: return 2;
38 case FK_Data_8: return 3;
42 class X86AsmBackend : public TargetAsmBackend {
44 X86AsmBackend(const Target &T)
45 : TargetAsmBackend(T) {}
47 void ApplyFixup(const MCAsmFixup &Fixup, MCDataFragment &DF,
48 uint64_t Value) const {
49 unsigned Size = 1 << getFixupKindLog2Size(Fixup.Kind);
51 assert(Fixup.Offset + Size <= DF.getContents().size() &&
52 "Invalid fixup offset!");
53 for (unsigned i = 0; i != Size; ++i)
54 DF.getContents()[Fixup.Offset + i] = uint8_t(Value >> (i * 8));
57 bool MayNeedRelaxation(const MCInst &Inst,
58 const SmallVectorImpl<MCAsmFixup> &Fixups) const;
60 void RelaxInstruction(const MCInstFragment *IF, MCInst &Res) const;
62 bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
65 static unsigned getRelaxedOpcode(unsigned Op) {
70 case X86::JAE_1: return X86::JAE_4;
71 case X86::JA_1: return X86::JA_4;
72 case X86::JBE_1: return X86::JBE_4;
73 case X86::JB_1: return X86::JB_4;
74 case X86::JE_1: return X86::JE_4;
75 case X86::JGE_1: return X86::JGE_4;
76 case X86::JG_1: return X86::JG_4;
77 case X86::JLE_1: return X86::JLE_4;
78 case X86::JL_1: return X86::JL_4;
79 case X86::JMP_1: return X86::JMP_4;
80 case X86::JNE_1: return X86::JNE_4;
81 case X86::JNO_1: return X86::JNO_4;
82 case X86::JNP_1: return X86::JNP_4;
83 case X86::JNS_1: return X86::JNS_4;
84 case X86::JO_1: return X86::JO_4;
85 case X86::JP_1: return X86::JP_4;
86 case X86::JS_1: return X86::JS_4;
90 bool X86AsmBackend::MayNeedRelaxation(const MCInst &Inst,
91 const SmallVectorImpl<MCAsmFixup> &Fixups) const {
92 for (unsigned i = 0, e = Fixups.size(); i != e; ++i) {
93 // We don't support relaxing anything else currently. Make sure we error out
94 // if we see a non-constant 1 or 2 byte fixup.
96 // FIXME: We should need to check this here, this is better checked in the
97 // object writer which should be verifying that any final relocations match
98 // the expected fixup. However, that code is more complicated and hasn't
99 // been written yet. See the FIXMEs in MachObjectWriter.cpp.
100 if ((Fixups[i].Kind == FK_Data_1 || Fixups[i].Kind == FK_Data_2) &&
101 !isa<MCConstantExpr>(Fixups[i].Value))
102 report_fatal_error("unexpected small fixup with a non-constant operand!");
104 // Check for a 1byte pcrel fixup, and enforce that we would know how to
105 // relax this instruction.
106 if (unsigned(Fixups[i].Kind) == X86::reloc_pcrel_1byte) {
107 assert(getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode());
115 // FIXME: Can tblgen help at all here to verify there aren't other instructions
117 void X86AsmBackend::RelaxInstruction(const MCInstFragment *IF,
119 // The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel.
120 unsigned RelaxedOp = getRelaxedOpcode(IF->getInst().getOpcode());
122 if (RelaxedOp == IF->getInst().getOpcode()) {
123 SmallString<256> Tmp;
124 raw_svector_ostream OS(Tmp);
125 IF->getInst().dump_pretty(OS);
126 report_fatal_error("unexpected instruction to relax: " + OS.str());
130 Res.setOpcode(RelaxedOp);
133 /// WriteNopData - Write optimal nops to the output file for the \arg Count
134 /// bytes. This returns the number of bytes written. It may return 0 if
135 /// the \arg Count is more than the maximum optimal nops.
137 /// FIXME this is X86 32-bit specific and should move to a better place.
138 bool X86AsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
139 static const uint8_t Nops[16][16] = {
147 {0x0f, 0x1f, 0x40, 0x00},
148 // nopl 0(%[re]ax,%[re]ax,1)
149 {0x0f, 0x1f, 0x44, 0x00, 0x00},
150 // nopw 0(%[re]ax,%[re]ax,1)
151 {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
153 {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
154 // nopl 0L(%[re]ax,%[re]ax,1)
155 {0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
156 // nopw 0L(%[re]ax,%[re]ax,1)
157 {0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
158 // nopw %cs:0L(%[re]ax,%[re]ax,1)
159 {0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
160 // nopl 0(%[re]ax,%[re]ax,1)
161 // nopw 0(%[re]ax,%[re]ax,1)
162 {0x0f, 0x1f, 0x44, 0x00, 0x00,
163 0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
164 // nopw 0(%[re]ax,%[re]ax,1)
165 // nopw 0(%[re]ax,%[re]ax,1)
166 {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00,
167 0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
168 // nopw 0(%[re]ax,%[re]ax,1)
169 // nopl 0L(%[re]ax) */
170 {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00,
171 0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
174 {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00,
175 0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
177 // nopl 0L(%[re]ax,%[re]ax,1)
178 {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00,
179 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00}
182 // Write an optimal sequence for the first 15 bytes.
183 uint64_t OptimalCount = (Count < 16) ? Count : 15;
184 for (uint64_t i = 0, e = OptimalCount; i != e; i++)
185 OW->Write8(Nops[OptimalCount - 1][i]);
187 // Finish with single byte nops.
188 for (uint64_t i = OptimalCount, e = Count; i != e; ++i)
196 class ELFX86AsmBackend : public X86AsmBackend {
198 ELFX86AsmBackend(const Target &T)
200 HasAbsolutizedSet = true;
201 HasScatteredSymbols = true;
204 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
208 bool isVirtualSection(const MCSection &Section) const {
209 const MCSectionELF &SE = static_cast<const MCSectionELF&>(Section);
210 return SE.getType() == MCSectionELF::SHT_NOBITS;;
214 class DarwinX86AsmBackend : public X86AsmBackend {
216 DarwinX86AsmBackend(const Target &T)
218 HasAbsolutizedSet = true;
219 HasScatteredSymbols = true;
222 bool isVirtualSection(const MCSection &Section) const {
223 const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
224 return (SMO.getType() == MCSectionMachO::S_ZEROFILL ||
225 SMO.getType() == MCSectionMachO::S_GB_ZEROFILL);
229 class DarwinX86_32AsmBackend : public DarwinX86AsmBackend {
231 DarwinX86_32AsmBackend(const Target &T)
232 : DarwinX86AsmBackend(T) {}
234 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
235 return new MachObjectWriter(OS, /*Is64Bit=*/false);
239 class DarwinX86_64AsmBackend : public DarwinX86AsmBackend {
241 DarwinX86_64AsmBackend(const Target &T)
242 : DarwinX86AsmBackend(T) {
243 HasReliableSymbolDifference = true;
246 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
247 return new MachObjectWriter(OS, /*Is64Bit=*/true);
250 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
251 // Temporary labels in the string literals sections require symbols. The
252 // issue is that the x86_64 relocation format does not allow symbol +
253 // offset, and so the linker does not have enough information to resolve the
254 // access to the appropriate atom unless an external relocation is used. For
255 // non-cstring sections, we expect the compiler to use a non-temporary label
256 // for anything that could have an addend pointing outside the symbol.
258 // See <rdar://problem/4765733>.
259 const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
260 return SMO.getType() == MCSectionMachO::S_CSTRING_LITERALS;
263 virtual bool isSectionAtomizable(const MCSection &Section) const {
264 const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
265 // Fixed sized data sections are uniqued, they cannot be diced into atoms.
266 switch (SMO.getType()) {
270 case MCSectionMachO::S_4BYTE_LITERALS:
271 case MCSectionMachO::S_8BYTE_LITERALS:
272 case MCSectionMachO::S_16BYTE_LITERALS:
273 case MCSectionMachO::S_LITERAL_POINTERS:
274 case MCSectionMachO::S_NON_LAZY_SYMBOL_POINTERS:
275 case MCSectionMachO::S_LAZY_SYMBOL_POINTERS:
276 case MCSectionMachO::S_MOD_INIT_FUNC_POINTERS:
277 case MCSectionMachO::S_MOD_TERM_FUNC_POINTERS:
278 case MCSectionMachO::S_INTERPOSING:
286 TargetAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
287 const std::string &TT) {
288 switch (Triple(TT).getOS()) {
290 return new DarwinX86_32AsmBackend(T);
292 return new ELFX86AsmBackend(T);
296 TargetAsmBackend *llvm::createX86_64AsmBackend(const Target &T,
297 const std::string &TT) {
298 switch (Triple(TT).getOS()) {
300 return new DarwinX86_64AsmBackend(T);
302 return new ELFX86AsmBackend(T);