1 //===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/Target/TargetAsmBackend.h"
12 #include "X86FixupKinds.h"
13 #include "llvm/ADT/Twine.h"
14 #include "llvm/MC/ELFObjectWriter.h"
15 #include "llvm/MC/MCAssembler.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCObjectWriter.h"
18 #include "llvm/MC/MCSectionCOFF.h"
19 #include "llvm/MC/MCSectionELF.h"
20 #include "llvm/MC/MCSectionMachO.h"
21 #include "llvm/MC/MachObjectWriter.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/raw_ostream.h"
24 #include "llvm/Target/TargetRegistry.h"
25 #include "llvm/Target/TargetAsmBackend.h"
29 static unsigned getFixupKindLog2Size(unsigned Kind) {
31 default: assert(0 && "invalid fixup kind!");
32 case X86::reloc_pcrel_1byte:
33 case FK_Data_1: return 0;
34 case X86::reloc_pcrel_2byte:
35 case FK_Data_2: return 1;
36 case X86::reloc_pcrel_4byte:
37 case X86::reloc_riprel_4byte:
38 case X86::reloc_riprel_4byte_movq_load:
39 case X86::reloc_signed_4byte:
40 case FK_Data_4: return 2;
41 case FK_Data_8: return 3;
46 class X86AsmBackend : public TargetAsmBackend {
48 X86AsmBackend(const Target &T)
49 : TargetAsmBackend(T) {}
51 void ApplyFixup(const MCFixup &Fixup, MCDataFragment &DF,
52 uint64_t Value) const {
53 unsigned Size = 1 << getFixupKindLog2Size(Fixup.getKind());
55 assert(Fixup.getOffset() + Size <= DF.getContents().size() &&
56 "Invalid fixup offset!");
57 for (unsigned i = 0; i != Size; ++i)
58 DF.getContents()[Fixup.getOffset() + i] = uint8_t(Value >> (i * 8));
61 bool MayNeedRelaxation(const MCInst &Inst) const;
63 void RelaxInstruction(const MCInst &Inst, MCInst &Res) const;
65 bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
67 } // end anonymous namespace
69 static unsigned getRelaxedOpcode(unsigned Op) {
74 case X86::JAE_1: return X86::JAE_4;
75 case X86::JA_1: return X86::JA_4;
76 case X86::JBE_1: return X86::JBE_4;
77 case X86::JB_1: return X86::JB_4;
78 case X86::JE_1: return X86::JE_4;
79 case X86::JGE_1: return X86::JGE_4;
80 case X86::JG_1: return X86::JG_4;
81 case X86::JLE_1: return X86::JLE_4;
82 case X86::JL_1: return X86::JL_4;
83 case X86::JMP_1: return X86::JMP_4;
84 case X86::JNE_1: return X86::JNE_4;
85 case X86::JNO_1: return X86::JNO_4;
86 case X86::JNP_1: return X86::JNP_4;
87 case X86::JNS_1: return X86::JNS_4;
88 case X86::JO_1: return X86::JO_4;
89 case X86::JP_1: return X86::JP_4;
90 case X86::JS_1: return X86::JS_4;
94 bool X86AsmBackend::MayNeedRelaxation(const MCInst &Inst) const {
95 // Check if this instruction is ever relaxable.
96 if (getRelaxedOpcode(Inst.getOpcode()) == Inst.getOpcode())
99 // If so, just assume it can be relaxed. Once we support relaxing more complex
100 // instructions we should check that the instruction actually has symbolic
101 // operands before doing this, but we need to be careful about things like
106 // FIXME: Can tblgen help at all here to verify there aren't other instructions
108 void X86AsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
109 // The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel.
110 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
112 if (RelaxedOp == Inst.getOpcode()) {
113 SmallString<256> Tmp;
114 raw_svector_ostream OS(Tmp);
115 Inst.dump_pretty(OS);
117 report_fatal_error("unexpected instruction to relax: " + OS.str());
121 Res.setOpcode(RelaxedOp);
124 /// WriteNopData - Write optimal nops to the output file for the \arg Count
125 /// bytes. This returns the number of bytes written. It may return 0 if
126 /// the \arg Count is more than the maximum optimal nops.
128 /// FIXME this is X86 32-bit specific and should move to a better place.
129 bool X86AsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
130 static const uint8_t Nops[16][16] = {
138 {0x0f, 0x1f, 0x40, 0x00},
139 // nopl 0(%[re]ax,%[re]ax,1)
140 {0x0f, 0x1f, 0x44, 0x00, 0x00},
141 // nopw 0(%[re]ax,%[re]ax,1)
142 {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
144 {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
145 // nopl 0L(%[re]ax,%[re]ax,1)
146 {0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
147 // nopw 0L(%[re]ax,%[re]ax,1)
148 {0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
149 // nopw %cs:0L(%[re]ax,%[re]ax,1)
150 {0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
151 // nopl 0(%[re]ax,%[re]ax,1)
152 // nopw 0(%[re]ax,%[re]ax,1)
153 {0x0f, 0x1f, 0x44, 0x00, 0x00,
154 0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
155 // nopw 0(%[re]ax,%[re]ax,1)
156 // nopw 0(%[re]ax,%[re]ax,1)
157 {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00,
158 0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
159 // nopw 0(%[re]ax,%[re]ax,1)
160 // nopl 0L(%[re]ax) */
161 {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00,
162 0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
165 {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00,
166 0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
168 // nopl 0L(%[re]ax,%[re]ax,1)
169 {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00,
170 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00}
173 // Write an optimal sequence for the first 15 bytes.
174 uint64_t OptimalCount = (Count < 16) ? Count : 15;
175 for (uint64_t i = 0, e = OptimalCount; i != e; i++)
176 OW->Write8(Nops[OptimalCount - 1][i]);
178 // Finish with single byte nops.
179 for (uint64_t i = OptimalCount, e = Count; i != e; ++i)
188 class ELFX86AsmBackend : public X86AsmBackend {
190 Triple::OSType OSType;
191 ELFX86AsmBackend(const Target &T, Triple::OSType _OSType)
192 : X86AsmBackend(T), OSType(_OSType) {
193 HasAbsolutizedSet = true;
194 HasScatteredSymbols = true;
195 HasReliableSymbolDifference = true;
198 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
199 const MCSectionELF &ES = static_cast<const MCSectionELF&>(Section);
200 return ES.getFlags() & MCSectionELF::SHF_MERGE;
203 bool isVirtualSection(const MCSection &Section) const {
204 const MCSectionELF &SE = static_cast<const MCSectionELF&>(Section);
205 return SE.getType() == MCSectionELF::SHT_NOBITS;
209 class ELFX86_32AsmBackend : public ELFX86AsmBackend {
211 ELFX86_32AsmBackend(const Target &T, Triple::OSType OSType)
212 : ELFX86AsmBackend(T, OSType) {}
214 unsigned getPointerSize() const {
218 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
219 return new ELFObjectWriter(OS, /*Is64Bit=*/false,
221 /*IsLittleEndian=*/true,
222 /*HasRelocationAddend=*/false);
226 class ELFX86_64AsmBackend : public ELFX86AsmBackend {
228 ELFX86_64AsmBackend(const Target &T, Triple::OSType OSType)
229 : ELFX86AsmBackend(T, OSType) {}
231 unsigned getPointerSize() const {
235 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
236 return new ELFObjectWriter(OS, /*Is64Bit=*/true,
238 /*IsLittleEndian=*/true,
239 /*HasRelocationAddend=*/true);
243 class WindowsX86AsmBackend : public X86AsmBackend {
246 WindowsX86AsmBackend(const Target &T, bool is64Bit)
249 HasScatteredSymbols = true;
252 unsigned getPointerSize() const {
259 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
260 return createWinCOFFObjectWriter(OS, Is64Bit);
263 bool isVirtualSection(const MCSection &Section) const {
264 const MCSectionCOFF &SE = static_cast<const MCSectionCOFF&>(Section);
265 return SE.getCharacteristics() & COFF::IMAGE_SCN_CNT_UNINITIALIZED_DATA;
269 class DarwinX86AsmBackend : public X86AsmBackend {
271 DarwinX86AsmBackend(const Target &T)
273 HasAbsolutizedSet = true;
274 HasScatteredSymbols = true;
277 bool isVirtualSection(const MCSection &Section) const {
278 const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
279 return (SMO.getType() == MCSectionMachO::S_ZEROFILL ||
280 SMO.getType() == MCSectionMachO::S_GB_ZEROFILL ||
281 SMO.getType() == MCSectionMachO::S_THREAD_LOCAL_ZEROFILL);
285 class DarwinX86_32AsmBackend : public DarwinX86AsmBackend {
287 DarwinX86_32AsmBackend(const Target &T)
288 : DarwinX86AsmBackend(T) {}
290 unsigned getPointerSize() const {
294 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
295 return new MachObjectWriter(OS, /*Is64Bit=*/false);
299 class DarwinX86_64AsmBackend : public DarwinX86AsmBackend {
301 DarwinX86_64AsmBackend(const Target &T)
302 : DarwinX86AsmBackend(T) {
303 HasReliableSymbolDifference = true;
306 unsigned getPointerSize() const {
310 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
311 return new MachObjectWriter(OS, /*Is64Bit=*/true);
314 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
315 // Temporary labels in the string literals sections require symbols. The
316 // issue is that the x86_64 relocation format does not allow symbol +
317 // offset, and so the linker does not have enough information to resolve the
318 // access to the appropriate atom unless an external relocation is used. For
319 // non-cstring sections, we expect the compiler to use a non-temporary label
320 // for anything that could have an addend pointing outside the symbol.
322 // See <rdar://problem/4765733>.
323 const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
324 return SMO.getType() == MCSectionMachO::S_CSTRING_LITERALS;
327 virtual bool isSectionAtomizable(const MCSection &Section) const {
328 const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
329 // Fixed sized data sections are uniqued, they cannot be diced into atoms.
330 switch (SMO.getType()) {
334 case MCSectionMachO::S_4BYTE_LITERALS:
335 case MCSectionMachO::S_8BYTE_LITERALS:
336 case MCSectionMachO::S_16BYTE_LITERALS:
337 case MCSectionMachO::S_LITERAL_POINTERS:
338 case MCSectionMachO::S_NON_LAZY_SYMBOL_POINTERS:
339 case MCSectionMachO::S_LAZY_SYMBOL_POINTERS:
340 case MCSectionMachO::S_MOD_INIT_FUNC_POINTERS:
341 case MCSectionMachO::S_MOD_TERM_FUNC_POINTERS:
342 case MCSectionMachO::S_INTERPOSING:
348 } // end anonymous namespace
350 TargetAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
351 const std::string &TT) {
352 switch (Triple(TT).getOS()) {
354 return new DarwinX86_32AsmBackend(T);
355 case Triple::MinGW32:
358 return new WindowsX86AsmBackend(T, false);
360 return new ELFX86_32AsmBackend(T, Triple(TT).getOS());
364 TargetAsmBackend *llvm::createX86_64AsmBackend(const Target &T,
365 const std::string &TT) {
366 switch (Triple(TT).getOS()) {
368 return new DarwinX86_64AsmBackend(T);
369 case Triple::MinGW64:
372 return new WindowsX86AsmBackend(T, true);
374 return new ELFX86_64AsmBackend(T, Triple(TT).getOS());