1 //===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/Target/TargetAsmBackend.h"
12 #include "X86FixupKinds.h"
13 #include "llvm/ADT/Twine.h"
14 #include "llvm/MC/MCAssembler.h"
15 #include "llvm/MC/MCELFObjectWriter.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCFixupKindInfo.h"
18 #include "llvm/MC/MCMachObjectWriter.h"
19 #include "llvm/MC/MCObjectFormat.h"
20 #include "llvm/MC/MCObjectWriter.h"
21 #include "llvm/MC/MCSectionCOFF.h"
22 #include "llvm/MC/MCSectionELF.h"
23 #include "llvm/MC/MCSectionMachO.h"
24 #include "llvm/Object/MachOFormat.h"
25 #include "llvm/Support/ELF.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/raw_ostream.h"
28 #include "llvm/Target/TargetRegistry.h"
29 #include "llvm/Target/TargetAsmBackend.h"
32 static unsigned getFixupKindLog2Size(unsigned Kind) {
34 default: assert(0 && "invalid fixup kind!");
36 case FK_Data_1: return 0;
38 case FK_Data_2: return 1;
40 case X86::reloc_riprel_4byte:
41 case X86::reloc_riprel_4byte_movq_load:
42 case X86::reloc_signed_4byte:
43 case X86::reloc_global_offset_table:
44 case FK_Data_4: return 2;
45 case FK_Data_8: return 3;
50 class X86MachObjectWriter : public MCMachObjectTargetWriter {
52 X86MachObjectWriter(bool Is64Bit, uint32_t CPUType,
54 : MCMachObjectTargetWriter(Is64Bit, CPUType, CPUSubtype,
55 /*UseAggressiveSymbolFolding=*/Is64Bit) {}
58 class X86AsmBackend : public TargetAsmBackend {
60 X86AsmBackend(const Target &T)
61 : TargetAsmBackend() {}
63 unsigned getNumFixupKinds() const {
64 return X86::NumTargetFixupKinds;
67 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
68 const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = {
69 { "reloc_riprel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
70 { "reloc_riprel_4byte_movq_load", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel},
71 { "reloc_signed_4byte", 0, 4 * 8, 0},
72 { "reloc_global_offset_table", 0, 4 * 8, 0}
75 if (Kind < FirstTargetFixupKind)
76 return TargetAsmBackend::getFixupKindInfo(Kind);
78 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
80 return Infos[Kind - FirstTargetFixupKind];
83 void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
84 uint64_t Value) const {
85 unsigned Size = 1 << getFixupKindLog2Size(Fixup.getKind());
87 assert(Fixup.getOffset() + Size <= DataSize &&
88 "Invalid fixup offset!");
89 for (unsigned i = 0; i != Size; ++i)
90 Data[Fixup.getOffset() + i] = uint8_t(Value >> (i * 8));
93 bool MayNeedRelaxation(const MCInst &Inst) const;
95 void RelaxInstruction(const MCInst &Inst, MCInst &Res) const;
97 bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
99 } // end anonymous namespace
101 static unsigned getRelaxedOpcodeBranch(unsigned Op) {
106 case X86::JAE_1: return X86::JAE_4;
107 case X86::JA_1: return X86::JA_4;
108 case X86::JBE_1: return X86::JBE_4;
109 case X86::JB_1: return X86::JB_4;
110 case X86::JE_1: return X86::JE_4;
111 case X86::JGE_1: return X86::JGE_4;
112 case X86::JG_1: return X86::JG_4;
113 case X86::JLE_1: return X86::JLE_4;
114 case X86::JL_1: return X86::JL_4;
115 case X86::JMP_1: return X86::JMP_4;
116 case X86::JNE_1: return X86::JNE_4;
117 case X86::JNO_1: return X86::JNO_4;
118 case X86::JNP_1: return X86::JNP_4;
119 case X86::JNS_1: return X86::JNS_4;
120 case X86::JO_1: return X86::JO_4;
121 case X86::JP_1: return X86::JP_4;
122 case X86::JS_1: return X86::JS_4;
126 static unsigned getRelaxedOpcodeArith(unsigned Op) {
132 case X86::IMUL16rri8: return X86::IMUL16rri;
133 case X86::IMUL16rmi8: return X86::IMUL16rmi;
134 case X86::IMUL32rri8: return X86::IMUL32rri;
135 case X86::IMUL32rmi8: return X86::IMUL32rmi;
136 case X86::IMUL64rri8: return X86::IMUL64rri32;
137 case X86::IMUL64rmi8: return X86::IMUL64rmi32;
140 case X86::AND16ri8: return X86::AND16ri;
141 case X86::AND16mi8: return X86::AND16mi;
142 case X86::AND32ri8: return X86::AND32ri;
143 case X86::AND32mi8: return X86::AND32mi;
144 case X86::AND64ri8: return X86::AND64ri32;
145 case X86::AND64mi8: return X86::AND64mi32;
148 case X86::OR16ri8: return X86::OR16ri;
149 case X86::OR16mi8: return X86::OR16mi;
150 case X86::OR32ri8: return X86::OR32ri;
151 case X86::OR32mi8: return X86::OR32mi;
152 case X86::OR64ri8: return X86::OR64ri32;
153 case X86::OR64mi8: return X86::OR64mi32;
156 case X86::XOR16ri8: return X86::XOR16ri;
157 case X86::XOR16mi8: return X86::XOR16mi;
158 case X86::XOR32ri8: return X86::XOR32ri;
159 case X86::XOR32mi8: return X86::XOR32mi;
160 case X86::XOR64ri8: return X86::XOR64ri32;
161 case X86::XOR64mi8: return X86::XOR64mi32;
164 case X86::ADD16ri8: return X86::ADD16ri;
165 case X86::ADD16mi8: return X86::ADD16mi;
166 case X86::ADD32ri8: return X86::ADD32ri;
167 case X86::ADD32mi8: return X86::ADD32mi;
168 case X86::ADD64ri8: return X86::ADD64ri32;
169 case X86::ADD64mi8: return X86::ADD64mi32;
172 case X86::SUB16ri8: return X86::SUB16ri;
173 case X86::SUB16mi8: return X86::SUB16mi;
174 case X86::SUB32ri8: return X86::SUB32ri;
175 case X86::SUB32mi8: return X86::SUB32mi;
176 case X86::SUB64ri8: return X86::SUB64ri32;
177 case X86::SUB64mi8: return X86::SUB64mi32;
180 case X86::CMP16ri8: return X86::CMP16ri;
181 case X86::CMP16mi8: return X86::CMP16mi;
182 case X86::CMP32ri8: return X86::CMP32ri;
183 case X86::CMP32mi8: return X86::CMP32mi;
184 case X86::CMP64ri8: return X86::CMP64ri32;
185 case X86::CMP64mi8: return X86::CMP64mi32;
189 static unsigned getRelaxedOpcode(unsigned Op) {
190 unsigned R = getRelaxedOpcodeArith(Op);
193 return getRelaxedOpcodeBranch(Op);
196 bool X86AsmBackend::MayNeedRelaxation(const MCInst &Inst) const {
197 // Branches can always be relaxed.
198 if (getRelaxedOpcodeBranch(Inst.getOpcode()) != Inst.getOpcode())
201 // Check if this instruction is ever relaxable.
202 if (getRelaxedOpcodeArith(Inst.getOpcode()) == Inst.getOpcode())
206 // Check if it has an expression and is not RIP relative.
209 for (unsigned i = 0; i < Inst.getNumOperands(); ++i) {
210 const MCOperand &Op = Inst.getOperand(i);
214 if (Op.isReg() && Op.getReg() == X86::RIP)
218 // FIXME: Why exactly do we need the !hasRIP? Is it just a limitation on
219 // how we do relaxations?
220 return hasExp && !hasRIP;
223 // FIXME: Can tblgen help at all here to verify there aren't other instructions
225 void X86AsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
226 // The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel.
227 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
229 if (RelaxedOp == Inst.getOpcode()) {
230 SmallString<256> Tmp;
231 raw_svector_ostream OS(Tmp);
232 Inst.dump_pretty(OS);
234 report_fatal_error("unexpected instruction to relax: " + OS.str());
238 Res.setOpcode(RelaxedOp);
241 /// WriteNopData - Write optimal nops to the output file for the \arg Count
242 /// bytes. This returns the number of bytes written. It may return 0 if
243 /// the \arg Count is more than the maximum optimal nops.
244 bool X86AsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
245 static const uint8_t Nops[10][10] = {
253 {0x0f, 0x1f, 0x40, 0x00},
254 // nopl 0(%[re]ax,%[re]ax,1)
255 {0x0f, 0x1f, 0x44, 0x00, 0x00},
256 // nopw 0(%[re]ax,%[re]ax,1)
257 {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
259 {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
260 // nopl 0L(%[re]ax,%[re]ax,1)
261 {0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
262 // nopw 0L(%[re]ax,%[re]ax,1)
263 {0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
264 // nopw %cs:0L(%[re]ax,%[re]ax,1)
265 {0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
268 // Write an optimal sequence for the first 15 bytes.
269 const uint64_t OptimalCount = (Count < 16) ? Count : 15;
270 const uint64_t Prefixes = OptimalCount <= 10 ? 0 : OptimalCount - 10;
271 for (uint64_t i = 0, e = Prefixes; i != e; i++)
273 const uint64_t Rest = OptimalCount - Prefixes;
274 for (uint64_t i = 0, e = Rest; i != e; i++)
275 OW->Write8(Nops[Rest - 1][i]);
277 // Finish with single byte nops.
278 for (uint64_t i = OptimalCount, e = Count; i != e; ++i)
287 class ELFX86AsmBackend : public X86AsmBackend {
288 MCELFObjectFormat Format;
291 Triple::OSType OSType;
292 ELFX86AsmBackend(const Target &T, Triple::OSType _OSType)
293 : X86AsmBackend(T), OSType(_OSType) {
294 HasReliableSymbolDifference = true;
297 virtual const MCObjectFormat &getObjectFormat() const {
301 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
302 const MCSectionELF &ES = static_cast<const MCSectionELF&>(Section);
303 return ES.getFlags() & MCSectionELF::SHF_MERGE;
307 class ELFX86_32AsmBackend : public ELFX86AsmBackend {
309 ELFX86_32AsmBackend(const Target &T, Triple::OSType OSType)
310 : ELFX86AsmBackend(T, OSType) {}
312 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
313 return createELFObjectWriter(OS, /*Is64Bit=*/false,
315 /*IsLittleEndian=*/true,
316 /*HasRelocationAddend=*/false);
320 class ELFX86_64AsmBackend : public ELFX86AsmBackend {
322 ELFX86_64AsmBackend(const Target &T, Triple::OSType OSType)
323 : ELFX86AsmBackend(T, OSType) {}
325 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
326 return createELFObjectWriter(OS, /*Is64Bit=*/true,
327 OSType, ELF::EM_X86_64,
328 /*IsLittleEndian=*/true,
329 /*HasRelocationAddend=*/true);
333 class WindowsX86AsmBackend : public X86AsmBackend {
335 MCCOFFObjectFormat Format;
338 WindowsX86AsmBackend(const Target &T, bool is64Bit)
343 virtual const MCObjectFormat &getObjectFormat() const {
347 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
348 return createWinCOFFObjectWriter(OS, Is64Bit);
352 class DarwinX86AsmBackend : public X86AsmBackend {
353 MCMachOObjectFormat Format;
356 DarwinX86AsmBackend(const Target &T)
357 : X86AsmBackend(T) { }
359 virtual const MCObjectFormat &getObjectFormat() const {
364 class DarwinX86_32AsmBackend : public DarwinX86AsmBackend {
366 DarwinX86_32AsmBackend(const Target &T)
367 : DarwinX86AsmBackend(T) {}
369 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
370 return createMachObjectWriter(new X86MachObjectWriter(
372 object::mach::CTM_i386,
373 object::mach::CSX86_ALL),
374 OS, /*IsLittleEndian=*/true);
378 class DarwinX86_64AsmBackend : public DarwinX86AsmBackend {
380 DarwinX86_64AsmBackend(const Target &T)
381 : DarwinX86AsmBackend(T) {
382 HasReliableSymbolDifference = true;
385 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
386 return createMachObjectWriter(new X86MachObjectWriter(
388 object::mach::CTM_x86_64,
389 object::mach::CSX86_ALL),
390 OS, /*IsLittleEndian=*/true);
393 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
394 // Temporary labels in the string literals sections require symbols. The
395 // issue is that the x86_64 relocation format does not allow symbol +
396 // offset, and so the linker does not have enough information to resolve the
397 // access to the appropriate atom unless an external relocation is used. For
398 // non-cstring sections, we expect the compiler to use a non-temporary label
399 // for anything that could have an addend pointing outside the symbol.
401 // See <rdar://problem/4765733>.
402 const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
403 return SMO.getType() == MCSectionMachO::S_CSTRING_LITERALS;
406 virtual bool isSectionAtomizable(const MCSection &Section) const {
407 const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
408 // Fixed sized data sections are uniqued, they cannot be diced into atoms.
409 switch (SMO.getType()) {
413 case MCSectionMachO::S_4BYTE_LITERALS:
414 case MCSectionMachO::S_8BYTE_LITERALS:
415 case MCSectionMachO::S_16BYTE_LITERALS:
416 case MCSectionMachO::S_LITERAL_POINTERS:
417 case MCSectionMachO::S_NON_LAZY_SYMBOL_POINTERS:
418 case MCSectionMachO::S_LAZY_SYMBOL_POINTERS:
419 case MCSectionMachO::S_MOD_INIT_FUNC_POINTERS:
420 case MCSectionMachO::S_MOD_TERM_FUNC_POINTERS:
421 case MCSectionMachO::S_INTERPOSING:
427 } // end anonymous namespace
429 TargetAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
430 const std::string &TT) {
431 switch (Triple(TT).getOS()) {
433 return new DarwinX86_32AsmBackend(T);
434 case Triple::MinGW32:
437 return new WindowsX86AsmBackend(T, false);
439 return new ELFX86_32AsmBackend(T, Triple(TT).getOS());
443 TargetAsmBackend *llvm::createX86_64AsmBackend(const Target &T,
444 const std::string &TT) {
445 switch (Triple(TT).getOS()) {
447 return new DarwinX86_64AsmBackend(T);
448 case Triple::MinGW64:
451 return new WindowsX86AsmBackend(T, true);
453 return new ELFX86_64AsmBackend(T, Triple(TT).getOS());