1 //===-- X86/Printer.cpp - Convert X86 code to human readable rep. ---------===//
3 // This file contains a printer that converts from our internal representation
4 // of LLVM code to a nice human readable form that is suitable for debuggging.
6 //===----------------------------------------------------------------------===//
9 #include "X86InstrInfo.h"
10 #include "llvm/Pass.h"
11 #include "llvm/Function.h"
12 #include "llvm/Target/TargetMachine.h"
13 #include "llvm/CodeGen/MachineFunction.h"
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "Support/Statistic.h"
18 struct Printer : public FunctionPass {
22 Printer(TargetMachine &tm, std::ostream &o) : TM(tm), O(o) {}
24 virtual const char *getPassName() const {
25 return "X86 Assembly Printer";
28 bool runOnFunction(Function &F);
32 /// createX86CodePrinterPass - Print out the specified machine code function to
33 /// the specified stream. This function should work regardless of whether or
34 /// not the function is in SSA form or not.
36 Pass *createX86CodePrinterPass(TargetMachine &TM, std::ostream &O) {
37 return new Printer(TM, O);
41 /// runOnFunction - This uses the X86InstructionInfo::print method
42 /// to print assembly for each instruction.
43 bool Printer::runOnFunction (Function & F)
45 static unsigned bbnumber = 0;
46 MachineFunction & MF = MachineFunction::get (&F);
47 const MachineInstrInfo & MII = TM.getInstrInfo ();
49 // Print out labels for the function.
50 O << "\t.globl\t" << F.getName () << "\n";
51 O << "\t.type\t" << F.getName () << ", @function\n";
52 O << F.getName () << ":\n";
54 // Print out code for the function.
55 for (MachineFunction::const_iterator bb_i = MF.begin (), bb_e = MF.end ();
58 // Print a label for the basic block.
59 O << ".BB" << bbnumber++ << ":\n";
60 for (MachineBasicBlock::const_iterator i_i = bb_i->begin (), i_e =
61 bb_i->end (); i_i != i_e; ++i_i)
63 // Print the assembly for the instruction.
65 MII.print(*i_i, O, TM);
69 // We didn't modify anything.
73 static bool isScale(const MachineOperand &MO) {
74 return MO.isImmediate() &&
75 (MO.getImmedValue() == 1 || MO.getImmedValue() == 2 ||
76 MO.getImmedValue() == 4 || MO.getImmedValue() == 8);
79 static bool isMem(const MachineInstr *MI, unsigned Op) {
80 return Op+4 <= MI->getNumOperands() &&
81 MI->getOperand(Op ).isRegister() &&isScale(MI->getOperand(Op+1)) &&
82 MI->getOperand(Op+2).isRegister() &&MI->getOperand(Op+3).isImmediate();
85 static void printOp(std::ostream &O, const MachineOperand &MO,
86 const MRegisterInfo &RI) {
87 switch (MO.getType()) {
88 case MachineOperand::MO_VirtualRegister:
89 if (Value *V = MO.getVRegValueOrNull()) {
90 O << "<" << V->getName() << ">";
93 case MachineOperand::MO_MachineRegister:
94 if (MO.getReg() < MRegisterInfo::FirstVirtualRegister)
95 O << RI.get(MO.getReg()).Name;
97 O << "%reg" << MO.getReg();
100 case MachineOperand::MO_SignExtendedImmed:
101 case MachineOperand::MO_UnextendedImmed:
102 O << (int)MO.getImmedValue();
104 case MachineOperand::MO_PCRelativeDisp:
105 O << "<" << MO.getVRegValue()->getName() << ">";
108 O << "<unknown op ty>"; return;
112 static const std::string sizePtr (const MachineInstrDescriptor &Desc) {
113 switch (Desc.TSFlags & X86II::ArgMask) {
114 case X86II::Arg8: return "BYTE PTR";
115 case X86II::Arg16: return "WORD PTR";
116 case X86II::Arg32: return "DWORD PTR";
117 case X86II::Arg64: return "QWORD PTR";
118 case X86II::Arg80: return "XWORD PTR";
119 case X86II::Arg128: return "128BIT PTR"; // dunno what the real one is
120 default: return "<SIZE?> PTR"; // crack being smoked
124 static void printMemReference(std::ostream &O, const MachineInstr *MI,
125 unsigned Op, const MRegisterInfo &RI) {
126 assert(isMem(MI, Op) && "Invalid memory reference!");
127 const MachineOperand &BaseReg = MI->getOperand(Op);
128 const MachineOperand &Scale = MI->getOperand(Op+1);
129 const MachineOperand &IndexReg = MI->getOperand(Op+2);
130 const MachineOperand &Disp = MI->getOperand(Op+3);
133 bool NeedPlus = false;
134 if (BaseReg.getReg()) {
135 printOp(O, BaseReg, RI);
139 if (IndexReg.getReg()) {
140 if (NeedPlus) O << " + ";
141 if (Scale.getImmedValue() != 1)
142 O << Scale.getImmedValue() << "*";
143 printOp(O, IndexReg, RI);
147 if (Disp.getImmedValue()) {
148 if (NeedPlus) O << " + ";
149 printOp(O, Disp, RI);
154 // print - Print out an x86 instruction in intel syntax
155 void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
156 const TargetMachine &TM) const {
157 unsigned Opcode = MI->getOpcode();
158 const MachineInstrDescriptor &Desc = get(Opcode);
160 if (Opcode == X86::PHI) {
161 printOp(O, MI->getOperand(0), RI);
163 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
164 if (i != 1) O << ", ";
166 printOp(O, MI->getOperand(i), RI);
168 printOp(O, MI->getOperand(i+1), RI);
176 switch (Desc.TSFlags & X86II::FormMask) {
178 // The accepted forms of Raw instructions are:
179 // 1. nop - No operand required
180 // 2. jmp foo - PC relative displacement operand
182 assert(MI->getNumOperands() == 0 ||
183 (MI->getNumOperands() == 1 && MI->getOperand(0).isPCRelativeDisp())&&
184 "Illegal raw instruction!");
185 O << getName(MI->getOpCode()) << " ";
187 if (MI->getNumOperands() == 1) {
188 printOp(O, MI->getOperand(0), RI);
193 case X86II::AddRegFrm: {
194 // There are currently two forms of acceptable AddRegFrm instructions.
195 // Either the instruction JUST takes a single register (like inc, dec, etc),
196 // or it takes a register and an immediate of the same size as the register
197 // (move immediate f.e.). Note that this immediate value might be stored as
198 // an LLVM value, to represent, for example, loading the address of a global
201 assert(MI->getOperand(0).isRegister() &&
202 (MI->getNumOperands() == 1 ||
203 (MI->getNumOperands() == 2 &&
204 (MI->getOperand(1).getVRegValueOrNull() ||
205 MI->getOperand(1).isImmediate()))) &&
206 "Illegal form for AddRegFrm instruction!");
208 unsigned Reg = MI->getOperand(0).getReg();
210 O << getName(MI->getOpCode()) << " ";
211 printOp(O, MI->getOperand(0), RI);
212 if (MI->getNumOperands() == 2) {
214 printOp(O, MI->getOperand(1), RI);
219 case X86II::MRMDestReg: {
220 // There are two acceptable forms of MRMDestReg instructions, those with 3
223 // 3 Operands: in this form, the first two registers (the destination, and
224 // the first operand) should be the same, post register allocation. The 3rd
225 // operand is an additional input. This should be for things like add
228 // 2 Operands: this is for things like mov that do not read a second input
230 assert(MI->getOperand(0).isRegister() &&
231 (MI->getNumOperands() == 2 ||
232 (MI->getNumOperands() == 3 && MI->getOperand(1).isRegister())) &&
233 MI->getOperand(MI->getNumOperands()-1).isRegister()
234 && "Bad format for MRMDestReg!");
235 if (MI->getNumOperands() == 3 &&
236 MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
239 O << getName(MI->getOpCode()) << " ";
240 printOp(O, MI->getOperand(0), RI);
242 printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
247 case X86II::MRMDestMem: {
248 // These instructions are the same as MRMDestReg, but instead of having a
249 // register reference for the mod/rm field, it's a memory reference.
251 assert(isMem(MI, 0) && MI->getNumOperands() == 4+1 &&
252 MI->getOperand(4).isRegister() && "Bad format for MRMDestMem!");
254 O << getName(MI->getOpCode()) << " " << sizePtr (Desc) << " ";
255 printMemReference(O, MI, 0, RI);
257 printOp(O, MI->getOperand(4), RI);
262 case X86II::MRMSrcReg: {
263 // There is a two forms that are acceptable for MRMSrcReg instructions,
264 // those with 3 and 2 operands:
266 // 3 Operands: in this form, the last register (the second input) is the
267 // ModR/M input. The first two operands should be the same, post register
268 // allocation. This is for things like: add r32, r/m32
270 // 2 Operands: this is for things like mov that do not read a second input
272 assert(MI->getOperand(0).isRegister() &&
273 MI->getOperand(1).isRegister() &&
274 (MI->getNumOperands() == 2 ||
275 (MI->getNumOperands() == 3 && MI->getOperand(2).isRegister()))
276 && "Bad format for MRMDestReg!");
277 if (MI->getNumOperands() == 3 &&
278 MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
281 O << getName(MI->getOpCode()) << " ";
282 printOp(O, MI->getOperand(0), RI);
284 printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
289 case X86II::MRMSrcMem: {
290 // These instructions are the same as MRMSrcReg, but instead of having a
291 // register reference for the mod/rm field, it's a memory reference.
293 assert(MI->getOperand(0).isRegister() &&
294 (MI->getNumOperands() == 1+4 && isMem(MI, 1)) ||
295 (MI->getNumOperands() == 2+4 && MI->getOperand(1).isRegister() &&
297 && "Bad format for MRMDestReg!");
298 if (MI->getNumOperands() == 2+4 &&
299 MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
302 O << getName(MI->getOpCode()) << " ";
303 printOp(O, MI->getOperand(0), RI);
304 O << ", " << sizePtr (Desc) << " ";
305 printMemReference(O, MI, MI->getNumOperands()-4, RI);
310 case X86II::MRMS0r: case X86II::MRMS1r:
311 case X86II::MRMS2r: case X86II::MRMS3r:
312 case X86II::MRMS4r: case X86II::MRMS5r:
313 case X86II::MRMS6r: case X86II::MRMS7r: {
314 // In this form, the following are valid formats:
316 // 2. cmp reg, immediate
317 // 2. shl rdest, rinput <implicit CL or 1>
318 // 3. sbb rdest, rinput, immediate [rdest = rinput]
320 assert(MI->getNumOperands() > 0 && MI->getNumOperands() < 4 &&
321 MI->getOperand(0).isRegister() && "Bad MRMSxR format!");
322 assert((MI->getNumOperands() != 2 ||
323 MI->getOperand(1).isRegister() || MI->getOperand(1).isImmediate())&&
324 "Bad MRMSxR format!");
325 assert((MI->getNumOperands() < 3 ||
326 (MI->getOperand(1).isRegister() && MI->getOperand(2).isImmediate())) &&
327 "Bad MRMSxR format!");
329 if (MI->getNumOperands() > 1 && MI->getOperand(1).isRegister() &&
330 MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
333 O << getName(MI->getOpCode()) << " ";
334 printOp(O, MI->getOperand(0), RI);
335 if (MI->getOperand(MI->getNumOperands()-1).isImmediate()) {
337 printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
345 O << "\t\t\t-"; MI->print(O, TM); break;