1 //===-- X86/Printer.cpp - Convert X86 code to human readable rep. ---------===//
3 // This file contains a printer that converts from our internal representation
4 // of LLVM code to a nice human readable form that is suitable for debuggging.
6 //===----------------------------------------------------------------------===//
9 #include "X86InstrInfo.h"
10 #include "llvm/Pass.h"
11 #include "llvm/Function.h"
12 #include "llvm/Target/TargetMachine.h"
13 #include "llvm/CodeGen/MachineFunction.h"
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "Support/Statistic.h"
18 struct Printer : public FunctionPass {
22 Printer(TargetMachine &tm, std::ostream &o) : TM(tm), O(o) {}
24 bool runOnFunction(Function &F);
28 /// createX86CodePrinterPass - Print out the specified machine code function to
29 /// the specified stream. This function should work regardless of whether or
30 /// not the function is in SSA form or not.
32 Pass *createX86CodePrinterPass(TargetMachine &TM, std::ostream &O) {
33 return new Printer(TM, O);
37 /// runOnFunction - This uses the X86InstructionInfo::print method
38 /// to print assembly for each instruction.
39 bool Printer::runOnFunction (Function & F)
41 static unsigned bbnumber = 0;
42 MachineFunction & MF = MachineFunction::get (&F);
43 const MachineInstrInfo & MII = TM.getInstrInfo ();
45 // Print out labels for the function.
46 O << "\t.globl\t" << F.getName () << "\n";
47 O << "\t.type\t" << F.getName () << ", @function\n";
48 O << F.getName () << ":\n";
50 // Print out code for the function.
51 for (MachineFunction::const_iterator bb_i = MF.begin (), bb_e = MF.end ();
54 // Print a label for the basic block.
55 O << ".BB" << bbnumber++ << ":\n";
56 for (MachineBasicBlock::const_iterator i_i = bb_i->begin (), i_e =
57 bb_i->end (); i_i != i_e; ++i_i)
59 // Print the assembly for the instruction.
61 MII.print(*i_i, O, TM);
65 // We didn't modify anything.
69 static bool isReg(const MachineOperand &MO) {
70 return MO.getType() == MachineOperand::MO_VirtualRegister ||
71 MO.getType() == MachineOperand::MO_MachineRegister;
74 static bool isImmediate(const MachineOperand &MO) {
75 return MO.getType() == MachineOperand::MO_SignExtendedImmed ||
76 MO.getType() == MachineOperand::MO_UnextendedImmed;
79 static bool isPCRelativeDisp(const MachineOperand &MO) {
80 return MO.getType() == MachineOperand::MO_PCRelativeDisp;
83 static bool isScale(const MachineOperand &MO) {
84 return isImmediate(MO) &&
85 (MO.getImmedValue() == 1 || MO.getImmedValue() == 2 ||
86 MO.getImmedValue() == 4 || MO.getImmedValue() == 8);
89 static bool isMem(const MachineInstr *MI, unsigned Op) {
90 return Op+4 <= MI->getNumOperands() &&
91 isReg(MI->getOperand(Op )) && isScale(MI->getOperand(Op+1)) &&
92 isReg(MI->getOperand(Op+2)) && isImmediate(MI->getOperand(Op+3));
95 static void printOp(std::ostream &O, const MachineOperand &MO,
96 const MRegisterInfo &RI) {
97 switch (MO.getType()) {
98 case MachineOperand::MO_VirtualRegister:
99 if (Value *V = MO.getVRegValueOrNull()) {
100 O << "<" << V->getName() << ">";
103 case MachineOperand::MO_MachineRegister:
104 if (MO.getReg() < MRegisterInfo::FirstVirtualRegister)
105 O << RI.get(MO.getReg()).Name;
107 O << "%reg" << MO.getReg();
110 case MachineOperand::MO_SignExtendedImmed:
111 case MachineOperand::MO_UnextendedImmed:
112 O << (int)MO.getImmedValue();
114 case MachineOperand::MO_PCRelativeDisp:
115 O << "<" << MO.getVRegValue()->getName() << ">";
118 O << "<unknown op ty>"; return;
122 static void printMemReference(std::ostream &O, const MachineInstr *MI,
123 unsigned Op, const MRegisterInfo &RI) {
124 assert(isMem(MI, Op) && "Invalid memory reference!");
125 const MachineOperand &BaseReg = MI->getOperand(Op);
126 const MachineOperand &Scale = MI->getOperand(Op+1);
127 const MachineOperand &IndexReg = MI->getOperand(Op+2);
128 const MachineOperand &Disp = MI->getOperand(Op+3);
131 bool NeedPlus = false;
132 if (BaseReg.getReg()) {
133 printOp(O, BaseReg, RI);
137 if (IndexReg.getReg()) {
138 if (NeedPlus) O << " + ";
139 if (IndexReg.getImmedValue() != 1)
140 O << IndexReg.getImmedValue() << "*";
141 printOp(O, IndexReg, RI);
145 if (Disp.getImmedValue()) {
146 if (NeedPlus) O << " + ";
147 printOp(O, Disp, RI);
152 // print - Print out an x86 instruction in intel syntax
153 void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
154 const TargetMachine &TM) const {
155 unsigned Opcode = MI->getOpcode();
156 const MachineInstrDescriptor &Desc = get(Opcode);
158 switch (Desc.TSFlags & X86II::FormMask) {
160 // The accepted forms of Raw instructions are:
161 // 1. nop - No operand required
162 // 2. jmp foo - PC relative displacement operand
164 assert(MI->getNumOperands() == 0 ||
165 (MI->getNumOperands() == 1 && isPCRelativeDisp(MI->getOperand(0))) &&
166 "Illegal raw instruction!");
167 O << getName(MI->getOpCode()) << " ";
169 if (MI->getNumOperands() == 1) {
170 printOp(O, MI->getOperand(0), RI);
175 case X86II::AddRegFrm: {
176 // There are currently two forms of acceptable AddRegFrm instructions.
177 // Either the instruction JUST takes a single register (like inc, dec, etc),
178 // or it takes a register and an immediate of the same size as the register
179 // (move immediate f.e.). Note that this immediate value might be stored as
180 // an LLVM value, to represent, for example, loading the address of a global
183 assert(isReg(MI->getOperand(0)) &&
184 (MI->getNumOperands() == 1 ||
185 (MI->getNumOperands() == 2 &&
186 (MI->getOperand(1).getVRegValueOrNull() ||
187 isImmediate(MI->getOperand(1))))) &&
188 "Illegal form for AddRegFrm instruction!");
190 unsigned Reg = MI->getOperand(0).getReg();
192 O << getName(MI->getOpCode()) << " ";
193 printOp(O, MI->getOperand(0), RI);
194 if (MI->getNumOperands() == 2) {
196 printOp(O, MI->getOperand(1), RI);
201 case X86II::MRMDestReg: {
202 // There are two acceptable forms of MRMDestReg instructions, those with 3
205 // 3 Operands: in this form, the first two registers (the destination, and
206 // the first operand) should be the same, post register allocation. The 3rd
207 // operand is an additional input. This should be for things like add
210 // 2 Operands: this is for things like mov that do not read a second input
212 assert(isReg(MI->getOperand(0)) &&
213 (MI->getNumOperands() == 2 ||
214 (MI->getNumOperands() == 3 && isReg(MI->getOperand(1)))) &&
215 isReg(MI->getOperand(MI->getNumOperands()-1))
216 && "Bad format for MRMDestReg!");
217 if (MI->getNumOperands() == 3 &&
218 MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
221 O << getName(MI->getOpCode()) << " ";
222 printOp(O, MI->getOperand(0), RI);
224 printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
229 case X86II::MRMDestMem: {
230 // These instructions are the same as MRMDestReg, but instead of having a
231 // register reference for the mod/rm field, it's a memory reference.
233 assert(isMem(MI, 0) && MI->getNumOperands() == 4+1 &&
234 isReg(MI->getOperand(4)) && "Bad format for MRMDestMem!");
236 O << getName(MI->getOpCode()) << " <SIZE> PTR ";
237 printMemReference(O, MI, 0, RI);
239 printOp(O, MI->getOperand(4), RI);
244 case X86II::MRMSrcReg: {
245 // There is a two forms that are acceptable for MRMSrcReg instructions,
246 // those with 3 and 2 operands:
248 // 3 Operands: in this form, the last register (the second input) is the
249 // ModR/M input. The first two operands should be the same, post register
250 // allocation. This is for things like: add r32, r/m32
252 // 2 Operands: this is for things like mov that do not read a second input
254 assert(isReg(MI->getOperand(0)) &&
255 isReg(MI->getOperand(1)) &&
256 (MI->getNumOperands() == 2 ||
257 (MI->getNumOperands() == 3 && isReg(MI->getOperand(2))))
258 && "Bad format for MRMDestReg!");
259 if (MI->getNumOperands() == 3 &&
260 MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
263 O << getName(MI->getOpCode()) << " ";
264 printOp(O, MI->getOperand(0), RI);
266 printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
271 case X86II::MRMSrcMem: {
272 // These instructions are the same as MRMSrcReg, but instead of having a
273 // register reference for the mod/rm field, it's a memory reference.
275 assert(isReg(MI->getOperand(0)) &&
276 (MI->getNumOperands() == 1+4 && isMem(MI, 1)) ||
277 (MI->getNumOperands() == 2+4 && isReg(MI->getOperand(1)) &&
279 && "Bad format for MRMDestReg!");
280 if (MI->getNumOperands() == 2+4 &&
281 MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
284 O << getName(MI->getOpCode()) << " ";
285 printOp(O, MI->getOperand(0), RI);
286 O << ", <SIZE> PTR ";
287 printMemReference(O, MI, MI->getNumOperands()-4, RI);
292 case X86II::MRMS0r: case X86II::MRMS1r:
293 case X86II::MRMS2r: case X86II::MRMS3r:
294 case X86II::MRMS4r: case X86II::MRMS5r:
295 case X86II::MRMS6r: case X86II::MRMS7r: {
296 // In this form, the following are valid formats:
298 // 2. cmp reg, immediate
299 // 2. shl rdest, rinput <implicit CL or 1>
300 // 3. sbb rdest, rinput, immediate [rdest = rinput]
302 assert(MI->getNumOperands() > 0 && MI->getNumOperands() < 4 &&
303 isReg(MI->getOperand(0)) && "Bad MRMSxR format!");
304 assert((MI->getNumOperands() != 2 ||
305 isReg(MI->getOperand(1)) || isImmediate(MI->getOperand(1))) &&
306 "Bad MRMSxR format!");
307 assert((MI->getNumOperands() < 3 ||
308 (isReg(MI->getOperand(1)) && isImmediate(MI->getOperand(2)))) &&
309 "Bad MRMSxR format!");
311 if (MI->getNumOperands() > 1 && isReg(MI->getOperand(1)) &&
312 MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
315 O << getName(MI->getOpCode()) << " ";
316 printOp(O, MI->getOperand(0), RI);
317 if (isImmediate(MI->getOperand(MI->getNumOperands()-1))) {
319 printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
327 O << "\t\t\t-"; MI->print(O, TM); break;