1 //===-- X86CallingConv.td - Calling Conventions X86 32/64 --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This describes the calling conventions for the X86-32 and X86-64
13 //===----------------------------------------------------------------------===//
15 /// CCIfSubtarget - Match if the current subtarget has a feature F.
16 class CCIfSubtarget<string F, CCAction A>
17 : CCIf<!strconcat("State.getTarget().getSubtarget<X86Subtarget>().", F), A>;
19 //===----------------------------------------------------------------------===//
20 // Return Value Calling Conventions
21 //===----------------------------------------------------------------------===//
23 // Return-value conventions common to all X86 CC's.
24 def RetCC_X86Common : CallingConv<[
25 // Scalar values are returned in AX first, then DX. For i8, the ABI
26 // requires the values to be in AL and AH, however this code uses AL and DL
27 // instead. This is because using AH for the second register conflicts with
28 // the way LLVM does multiple return values -- a return of {i16,i8} would end
29 // up in AX and AH, which overlap. Front-ends wishing to conform to the ABI
30 // for functions that return two i8 values are currently expected to pack the
31 // values into an i16 (which uses AX, and thus AL:AH).
33 // For code that doesn't care about the ABI, we allow returning more than two
34 // integer values in registers.
35 CCIfType<[i8] , CCAssignToReg<[AL, DL, CL]>>,
36 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>,
37 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>,
38 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX]>>,
40 // Vector types are returned in XMM0 and XMM1, when they fit. XMM2 and XMM3
41 // can only be used by ABI non-compliant code. If the target doesn't have XMM
42 // registers, it won't have vector types.
43 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
44 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,
46 // 256-bit vectors are returned in YMM0 and XMM1, when they fit. YMM2 and YMM3
47 // can only be used by ABI non-compliant code. This vector type is only
48 // supported while using the AVX target feature.
49 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
50 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>,
52 // 512-bit vectors are returned in ZMM0 and ZMM1, when they fit. ZMM2 and ZMM3
53 // can only be used by ABI non-compliant code. This vector type is only
54 // supported while using the AVX-512 target feature.
55 CCIfType<[v16i32, v8i64, v16f32, v8f64],
56 CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>,
58 // MMX vector types are always returned in MM0. If the target doesn't have
59 // MM0, it doesn't support these vector types.
60 CCIfType<[x86mmx], CCAssignToReg<[MM0]>>,
62 // Long double types are always returned in ST0 (even with SSE).
63 CCIfType<[f80], CCAssignToReg<[ST0, ST1]>>
66 // X86-32 C return-value convention.
67 def RetCC_X86_32_C : CallingConv<[
68 // The X86-32 calling convention returns FP values in ST0, unless marked
69 // with "inreg" (used here to distinguish one kind of reg from another,
70 // weirdly; this is really the sse-regparm calling convention) in which
71 // case they use XMM0, otherwise it is the same as the common X86 calling
73 CCIfInReg<CCIfSubtarget<"hasSSE2()",
74 CCIfType<[f32, f64], CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
75 CCIfType<[f32,f64], CCAssignToReg<[ST0, ST1]>>,
76 CCDelegateTo<RetCC_X86Common>
79 // X86-32 FastCC return-value convention.
80 def RetCC_X86_32_Fast : CallingConv<[
81 // The X86-32 fastcc returns 1, 2, or 3 FP values in XMM0-2 if the target has
83 // This can happen when a float, 2 x float, or 3 x float vector is split by
84 // target lowering, and is returned in 1-3 sse regs.
85 CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
86 CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
88 // For integers, ECX can be used as an extra return register
89 CCIfType<[i8], CCAssignToReg<[AL, DL, CL]>>,
90 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>,
91 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>,
93 // Otherwise, it is the same as the common X86 calling convention.
94 CCDelegateTo<RetCC_X86Common>
97 // Intel_OCL_BI return-value convention.
98 def RetCC_Intel_OCL_BI : CallingConv<[
99 // Vector types are returned in XMM0,XMM1,XMMM2 and XMM3.
100 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64],
101 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,
103 // 256-bit FP vectors
104 // No more than 4 registers
105 CCIfType<[v8f32, v4f64, v8i32, v4i64],
106 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>,
108 // 512-bit FP vectors
109 CCIfType<[v16f32, v8f64, v16i32, v8i64],
110 CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>,
112 // i32, i64 in the standard way
113 CCDelegateTo<RetCC_X86Common>
116 // X86-32 HiPE return-value convention.
117 def RetCC_X86_32_HiPE : CallingConv<[
118 // Promote all types to i32
119 CCIfType<[i8, i16], CCPromoteToType<i32>>,
121 // Return: HP, P, VAL1, VAL2
122 CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX]>>
125 // X86-64 C return-value convention.
126 def RetCC_X86_64_C : CallingConv<[
127 // The X86-64 calling convention always returns FP values in XMM0.
128 CCIfType<[f32], CCAssignToReg<[XMM0, XMM1]>>,
129 CCIfType<[f64], CCAssignToReg<[XMM0, XMM1]>>,
131 // MMX vector types are always returned in XMM0.
132 CCIfType<[x86mmx], CCAssignToReg<[XMM0, XMM1]>>,
133 CCDelegateTo<RetCC_X86Common>
136 // X86-Win64 C return-value convention.
137 def RetCC_X86_Win64_C : CallingConv<[
138 // The X86-Win64 calling convention always returns __m64 values in RAX.
139 CCIfType<[x86mmx], CCBitConvertToType<i64>>,
141 // Otherwise, everything is the same as 'normal' X86-64 C CC.
142 CCDelegateTo<RetCC_X86_64_C>
145 // X86-64 HiPE return-value convention.
146 def RetCC_X86_64_HiPE : CallingConv<[
147 // Promote all types to i64
148 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
150 // Return: HP, P, VAL1, VAL2
151 CCIfType<[i64], CCAssignToReg<[R15, RBP, RAX, RDX]>>
154 // X86-64 WebKit_JS return-value convention.
155 def RetCC_X86_64_WebKit_JS : CallingConv<[
156 // Promote all types to i64
157 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
160 CCIfType<[i64], CCAssignToReg<[RAX]>>
163 // X86-64 AnyReg return-value convention. No explicit register is specified for
164 // the return-value. The register allocator is allowed and expected to choose
165 // any free register.
167 // This calling convention is currently only supported by the stackmap and
168 // patchpoint intrinsics. All other uses will result in an assert on Debug
169 // builds. On Release builds we fallback to the X86 C calling convention.
170 def RetCC_X86_64_AnyReg : CallingConv<[
171 CCCustom<"CC_X86_AnyReg_Error">
174 // This is the root return-value convention for the X86-32 backend.
175 def RetCC_X86_32 : CallingConv<[
176 // If FastCC, use RetCC_X86_32_Fast.
177 CCIfCC<"CallingConv::Fast", CCDelegateTo<RetCC_X86_32_Fast>>,
178 // If HiPE, use RetCC_X86_32_HiPE.
179 CCIfCC<"CallingConv::HiPE", CCDelegateTo<RetCC_X86_32_HiPE>>,
181 // Otherwise, use RetCC_X86_32_C.
182 CCDelegateTo<RetCC_X86_32_C>
185 // This is the root return-value convention for the X86-64 backend.
186 def RetCC_X86_64 : CallingConv<[
187 // HiPE uses RetCC_X86_64_HiPE
188 CCIfCC<"CallingConv::HiPE", CCDelegateTo<RetCC_X86_64_HiPE>>,
190 // Handle JavaScript calls.
191 CCIfCC<"CallingConv::WebKit_JS", CCDelegateTo<RetCC_X86_64_WebKit_JS>>,
192 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<RetCC_X86_64_AnyReg>>,
194 // Handle explicit CC selection
195 CCIfCC<"CallingConv::X86_64_Win64", CCDelegateTo<RetCC_X86_Win64_C>>,
196 CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo<RetCC_X86_64_C>>,
198 // Mingw64 and native Win64 use Win64 CC
199 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<RetCC_X86_Win64_C>>,
201 // Otherwise, drop to normal X86-64 CC
202 CCDelegateTo<RetCC_X86_64_C>
205 // This is the return-value convention used for the entire X86 backend.
206 def RetCC_X86 : CallingConv<[
208 // Check if this is the Intel OpenCL built-ins calling convention
209 CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo<RetCC_Intel_OCL_BI>>,
211 CCIfSubtarget<"is64Bit()", CCDelegateTo<RetCC_X86_64>>,
212 CCDelegateTo<RetCC_X86_32>
215 //===----------------------------------------------------------------------===//
216 // X86-64 Argument Calling Conventions
217 //===----------------------------------------------------------------------===//
219 def CC_X86_64_C : CallingConv<[
220 // Handles byval parameters.
221 CCIfByVal<CCPassByVal<8, 8>>,
223 // Promote i8/i16 arguments to i32.
224 CCIfType<[i8, i16], CCPromoteToType<i32>>,
226 // The 'nest' parameter, if any, is passed in R10.
227 CCIfNest<CCAssignToReg<[R10]>>,
229 // The first 6 integer arguments are passed in integer registers.
230 CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D, R9D]>>,
231 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
233 // The first 8 MMX vector arguments are passed in XMM registers on Darwin.
235 CCIfSubtarget<"isTargetDarwin()",
236 CCIfSubtarget<"hasSSE2()",
237 CCPromoteToType<v2i64>>>>,
239 // The first 8 FP/Vector arguments are passed in XMM registers.
240 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
241 CCIfSubtarget<"hasSSE1()",
242 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>,
244 // The first 8 256-bit vector arguments are passed in YMM registers, unless
245 // this is a vararg function.
246 // FIXME: This isn't precisely correct; the x86-64 ABI document says that
247 // fixed arguments to vararg functions are supposed to be passed in
248 // registers. Actually modeling that would be a lot of work, though.
249 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
250 CCIfSubtarget<"hasFp256()",
251 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3,
252 YMM4, YMM5, YMM6, YMM7]>>>>,
254 // The first 8 512-bit vector arguments are passed in ZMM registers.
255 CCIfNotVarArg<CCIfType<[v16i32, v8i64, v16f32, v8f64],
256 CCIfSubtarget<"hasAVX512()",
257 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7]>>>>,
259 // Integer/FP values get stored in stack slots that are 8 bytes in size and
260 // 8-byte aligned if there are no more registers to hold them.
261 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
263 // Long doubles get stack slots whose size and alignment depends on the
265 CCIfType<[f80], CCAssignToStack<0, 0>>,
267 // Vectors get 16-byte stack slots that are 16-byte aligned.
268 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
270 // 256-bit vectors get 32-byte stack slots that are 32-byte aligned.
271 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
272 CCAssignToStack<32, 32>>,
274 // 512-bit vectors get 64-byte stack slots that are 64-byte aligned.
275 CCIfType<[v16i32, v8i64, v16f32, v8f64],
276 CCAssignToStack<64, 64>>
279 // Calling convention used on Win64
280 def CC_X86_Win64_C : CallingConv<[
281 // FIXME: Handle byval stuff.
282 // FIXME: Handle varargs.
284 // Promote i8/i16 arguments to i32.
285 CCIfType<[i8, i16], CCPromoteToType<i32>>,
287 // The 'nest' parameter, if any, is passed in R10.
288 CCIfNest<CCAssignToReg<[R10]>>,
290 // 128 bit vectors are passed by pointer
291 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCPassIndirect<i64>>,
294 // 256 bit vectors are passed by pointer
295 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>,
297 // 512 bit vectors are passed by pointer
298 CCIfType<[v16i32, v16f32, v8f64, v8i64], CCPassIndirect<i64>>,
300 // The first 4 MMX vector arguments are passed in GPRs.
301 CCIfType<[x86mmx], CCBitConvertToType<i64>>,
303 // The first 4 integer arguments are passed in integer registers.
304 CCIfType<[i32], CCAssignToRegWithShadow<[ECX , EDX , R8D , R9D ],
305 [XMM0, XMM1, XMM2, XMM3]>>,
307 // Do not pass the sret argument in RCX, the Win64 thiscall calling
308 // convention requires "this" to be passed in RCX.
309 CCIfCC<"CallingConv::X86_ThisCall",
310 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[RDX , R8 , R9 ],
311 [XMM1, XMM2, XMM3]>>>>,
313 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
314 [XMM0, XMM1, XMM2, XMM3]>>,
316 // The first 4 FP/Vector arguments are passed in XMM registers.
317 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
318 CCAssignToRegWithShadow<[XMM0, XMM1, XMM2, XMM3],
319 [RCX , RDX , R8 , R9 ]>>,
321 // Integer/FP values get stored in stack slots that are 8 bytes in size and
322 // 8-byte aligned if there are no more registers to hold them.
323 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
325 // Long doubles get stack slots whose size and alignment depends on the
327 CCIfType<[f80], CCAssignToStack<0, 0>>
330 def CC_X86_64_GHC : CallingConv<[
331 // Promote i8/i16/i32 arguments to i64.
332 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
334 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim
336 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
338 // Pass in STG registers: F1, F2, F3, F4, D1, D2
339 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
340 CCIfSubtarget<"hasSSE1()",
341 CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>
344 def CC_X86_64_HiPE : CallingConv<[
345 // Promote i8/i16/i32 arguments to i64.
346 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
348 // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2, ARG3
349 CCIfType<[i64], CCAssignToReg<[R15, RBP, RSI, RDX, RCX, R8]>>,
351 // Integer/FP values get stored in stack slots that are 8 bytes in size and
352 // 8-byte aligned if there are no more registers to hold them.
353 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>
356 def CC_X86_64_WebKit_JS : CallingConv<[
357 // Promote i8/i16 arguments to i32.
358 CCIfType<[i8, i16], CCPromoteToType<i32>>,
360 // Only the first integer argument is passed in register.
361 CCIfType<[i32], CCAssignToReg<[EAX]>>,
362 CCIfType<[i64], CCAssignToReg<[RAX]>>,
364 // The remaining integer arguments are passed on the stack. 32bit integer and
365 // floating-point arguments are aligned to 4 byte and stored in 4 byte slots.
366 // 64bit integer and floating-point arguments are aligned to 8 byte and stored
367 // in 8 byte stack slots.
368 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
369 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
372 // No explicit register is specified for the AnyReg calling convention. The
373 // register allocator may assign the arguments to any free register.
375 // This calling convention is currently only supported by the stackmap and
376 // patchpoint intrinsics. All other uses will result in an assert on Debug
377 // builds. On Release builds we fallback to the X86 C calling convention.
378 def CC_X86_64_AnyReg : CallingConv<[
379 CCCustom<"CC_X86_AnyReg_Error">
382 //===----------------------------------------------------------------------===//
383 // X86 C Calling Convention
384 //===----------------------------------------------------------------------===//
386 /// CC_X86_32_Common - In all X86-32 calling conventions, extra integers and FP
387 /// values are spilled on the stack, and the first 4 vector values go in XMM
389 def CC_X86_32_Common : CallingConv<[
390 // Handles byval parameters.
391 CCIfByVal<CCPassByVal<4, 4>>,
393 // The first 3 float or double arguments, if marked 'inreg' and if the call
394 // is not a vararg call and if SSE2 is available, are passed in SSE registers.
395 CCIfNotVarArg<CCIfInReg<CCIfType<[f32,f64],
396 CCIfSubtarget<"hasSSE2()",
397 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>>,
399 // The first 3 __m64 vector arguments are passed in mmx registers if the
400 // call is not a vararg call.
401 CCIfNotVarArg<CCIfType<[x86mmx],
402 CCAssignToReg<[MM0, MM1, MM2]>>>,
404 // Integer/Float values get stored in stack slots that are 4 bytes in
405 // size and 4-byte aligned.
406 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
408 // Doubles get 8-byte slots that are 4-byte aligned.
409 CCIfType<[f64], CCAssignToStack<8, 4>>,
411 // Long doubles get slots whose size depends on the subtarget.
412 CCIfType<[f80], CCAssignToStack<0, 4>>,
414 // The first 4 SSE vector arguments are passed in XMM registers.
415 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
416 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>>,
418 // The first 4 AVX 256-bit vector arguments are passed in YMM registers.
419 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
420 CCIfSubtarget<"hasFp256()",
421 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>>>,
423 // Other SSE vectors get 16-byte stack slots that are 16-byte aligned.
424 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
426 // 256-bit AVX vectors get 32-byte stack slots that are 32-byte aligned.
427 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
428 CCAssignToStack<32, 32>>,
430 // __m64 vectors get 8-byte stack slots that are 4-byte aligned. They are
431 // passed in the parameter area.
432 CCIfType<[x86mmx], CCAssignToStack<8, 4>>]>;
434 def CC_X86_32_C : CallingConv<[
435 // Promote i8/i16 arguments to i32.
436 CCIfType<[i8, i16], CCPromoteToType<i32>>,
438 // The 'nest' parameter, if any, is passed in ECX.
439 CCIfNest<CCAssignToReg<[ECX]>>,
441 // The first 3 integer arguments, if marked 'inreg' and if the call is not
442 // a vararg call, are passed in integer registers.
443 CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>>>,
445 // Otherwise, same as everything else.
446 CCDelegateTo<CC_X86_32_Common>
449 def CC_X86_32_FastCall : CallingConv<[
450 // Promote i8/i16 arguments to i32.
451 CCIfType<[i8, i16], CCPromoteToType<i32>>,
453 // The 'nest' parameter, if any, is passed in EAX.
454 CCIfNest<CCAssignToReg<[EAX]>>,
456 // The first 2 integer arguments are passed in ECX/EDX
457 CCIfInReg<CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>>,
459 // Otherwise, same as everything else.
460 CCDelegateTo<CC_X86_32_Common>
463 def CC_X86_32_ThisCall_Common : CallingConv<[
464 // The first integer argument is passed in ECX
465 CCIfType<[i32], CCAssignToReg<[ECX]>>,
467 // Otherwise, same as everything else.
468 CCDelegateTo<CC_X86_32_Common>
471 def CC_X86_32_ThisCall_Mingw : CallingConv<[
472 // Promote i8/i16 arguments to i32.
473 CCIfType<[i8, i16], CCPromoteToType<i32>>,
475 CCDelegateTo<CC_X86_32_ThisCall_Common>
478 def CC_X86_32_ThisCall_Win : CallingConv<[
479 // Promote i8/i16 arguments to i32.
480 CCIfType<[i8, i16], CCPromoteToType<i32>>,
482 // Pass sret arguments indirectly through stack.
483 CCIfSRet<CCAssignToStack<4, 4>>,
485 CCDelegateTo<CC_X86_32_ThisCall_Common>
488 def CC_X86_CDeclMethod : CallingConv<[
489 // Promote i8/i16 arguments to i32.
490 CCIfType<[i8, i16], CCPromoteToType<i32>>,
492 CCCustom<"CC_X86_CDeclMethod_SRet">,
494 CCDelegateTo<CC_X86_32_Common>
497 def CC_X86_32_ThisCall : CallingConv<[
498 CCIfSubtarget<"isTargetCygMing()", CCDelegateTo<CC_X86_32_ThisCall_Mingw>>,
499 CCDelegateTo<CC_X86_32_ThisCall_Win>
502 def CC_X86_32_FastCC : CallingConv<[
503 // Handles byval parameters. Note that we can't rely on the delegation
504 // to CC_X86_32_Common for this because that happens after code that
505 // puts arguments in registers.
506 CCIfByVal<CCPassByVal<4, 4>>,
508 // Promote i8/i16 arguments to i32.
509 CCIfType<[i8, i16], CCPromoteToType<i32>>,
511 // The 'nest' parameter, if any, is passed in EAX.
512 CCIfNest<CCAssignToReg<[EAX]>>,
514 // The first 2 integer arguments are passed in ECX/EDX
515 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>,
517 // The first 3 float or double arguments, if the call is not a vararg
518 // call and if SSE2 is available, are passed in SSE registers.
519 CCIfNotVarArg<CCIfType<[f32,f64],
520 CCIfSubtarget<"hasSSE2()",
521 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
523 // Doubles get 8-byte slots that are 8-byte aligned.
524 CCIfType<[f64], CCAssignToStack<8, 8>>,
526 // Otherwise, same as everything else.
527 CCDelegateTo<CC_X86_32_Common>
530 def CC_X86_32_GHC : CallingConv<[
531 // Promote i8/i16 arguments to i32.
532 CCIfType<[i8, i16], CCPromoteToType<i32>>,
534 // Pass in STG registers: Base, Sp, Hp, R1
535 CCIfType<[i32], CCAssignToReg<[EBX, EBP, EDI, ESI]>>
538 def CC_X86_32_HiPE : CallingConv<[
539 // Promote i8/i16 arguments to i32.
540 CCIfType<[i8, i16], CCPromoteToType<i32>>,
542 // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2
543 CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX, ECX]>>,
545 // Integer/Float values get stored in stack slots that are 4 bytes in
546 // size and 4-byte aligned.
547 CCIfType<[i32, f32], CCAssignToStack<4, 4>>
550 // X86-64 Intel OpenCL built-ins calling convention.
551 def CC_Intel_OCL_BI : CallingConv<[
553 CCIfType<[i32], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[ECX, EDX, R8D, R9D]>>>,
554 CCIfType<[i64], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[RCX, RDX, R8, R9 ]>>>,
556 CCIfType<[i32], CCIfSubtarget<"is64Bit()", CCAssignToReg<[EDI, ESI, EDX, ECX]>>>,
557 CCIfType<[i64], CCIfSubtarget<"is64Bit()", CCAssignToReg<[RDI, RSI, RDX, RCX]>>>,
559 CCIfType<[i32], CCAssignToStack<4, 4>>,
561 // The SSE vector arguments are passed in XMM registers.
562 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64],
563 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>,
565 // The 256-bit vector arguments are passed in YMM registers.
566 CCIfType<[v8f32, v4f64, v8i32, v4i64],
567 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>,
569 // The 512-bit vector arguments are passed in ZMM registers.
570 CCIfType<[v16f32, v8f64, v16i32, v8i64],
571 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3]>>,
573 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>,
574 CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64_C>>,
575 CCDelegateTo<CC_X86_32_C>
578 //===----------------------------------------------------------------------===//
579 // X86 Root Argument Calling Conventions
580 //===----------------------------------------------------------------------===//
582 // This is the root argument convention for the X86-32 backend.
583 def CC_X86_32 : CallingConv<[
584 CCIfCC<"CallingConv::X86_FastCall", CCDelegateTo<CC_X86_32_FastCall>>,
585 CCIfCC<"CallingConv::X86_ThisCall", CCDelegateTo<CC_X86_32_ThisCall>>,
586 CCIfCC<"CallingConv::X86_CDeclMethod", CCDelegateTo<CC_X86_CDeclMethod>>,
587 CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_X86_32_FastCC>>,
588 CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_32_GHC>>,
589 CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_32_HiPE>>,
591 // Otherwise, drop to normal X86-32 CC
592 CCDelegateTo<CC_X86_32_C>
595 // This is the root argument convention for the X86-64 backend.
596 def CC_X86_64 : CallingConv<[
597 CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_64_GHC>>,
598 CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_64_HiPE>>,
599 CCIfCC<"CallingConv::WebKit_JS", CCDelegateTo<CC_X86_64_WebKit_JS>>,
600 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<CC_X86_64_AnyReg>>,
601 CCIfCC<"CallingConv::X86_64_Win64", CCDelegateTo<CC_X86_Win64_C>>,
602 CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo<CC_X86_64_C>>,
604 // Mingw64 and native Win64 use Win64 CC
605 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>,
607 // Otherwise, drop to normal X86-64 CC
608 CCDelegateTo<CC_X86_64_C>
611 // This is the argument convention used for the entire X86 backend.
612 def CC_X86 : CallingConv<[
613 CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo<CC_Intel_OCL_BI>>,
614 CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64>>,
615 CCDelegateTo<CC_X86_32>
618 //===----------------------------------------------------------------------===//
619 // Callee-saved Registers.
620 //===----------------------------------------------------------------------===//
622 def CSR_NoRegs : CalleeSavedRegs<(add)>;
624 def CSR_32 : CalleeSavedRegs<(add ESI, EDI, EBX, EBP)>;
625 def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>;
627 def CSR_32EHRet : CalleeSavedRegs<(add EAX, EDX, CSR_32)>;
628 def CSR_64EHRet : CalleeSavedRegs<(add RAX, RDX, CSR_64)>;
630 def CSR_Win64 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15,
631 (sequence "XMM%u", 6, 15))>;
633 // All GPRs - except r11
634 def CSR_64_RT_MostRegs : CalleeSavedRegs<(add CSR_64, RAX, RCX, RDX, RSI, RDI,
637 // All registers - except r11
638 def CSR_64_RT_AllRegs : CalleeSavedRegs<(add CSR_64_RT_MostRegs,
639 (sequence "XMM%u", 0, 15))>;
640 def CSR_64_RT_AllRegs_AVX : CalleeSavedRegs<(add CSR_64_RT_MostRegs,
641 (sequence "YMM%u", 0, 15))>;
643 def CSR_64_MostRegs : CalleeSavedRegs<(add RBX, RCX, RDX, RSI, RDI, R8, R9, R10,
644 R11, R12, R13, R14, R15, RBP,
645 (sequence "XMM%u", 0, 15))>;
647 def CSR_64_AllRegs : CalleeSavedRegs<(add CSR_64_MostRegs, RAX, RSP,
648 (sequence "XMM%u", 16, 31))>;
649 def CSR_64_AllRegs_AVX : CalleeSavedRegs<(sub (add CSR_64_MostRegs, RAX, RSP,
650 (sequence "YMM%u", 0, 31)),
651 (sequence "XMM%u", 0, 15))>;
653 // Standard C + YMM6-15
654 def CSR_Win64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12,
656 (sequence "YMM%u", 6, 15))>;
658 def CSR_Win64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI,
660 (sequence "ZMM%u", 6, 21),
662 //Standard C + XMM 8-15
663 def CSR_64_Intel_OCL_BI : CalleeSavedRegs<(add CSR_64,
664 (sequence "XMM%u", 8, 15))>;
666 //Standard C + YMM 8-15
667 def CSR_64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add CSR_64,
668 (sequence "YMM%u", 8, 15))>;
670 def CSR_64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RDI, RSI, R14, R15,
671 (sequence "ZMM%u", 16, 31),