1 //===- X86CallingConv.td - Calling Conventions X86 32/64 ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This describes the calling conventions for the X86-32 and X86-64
13 //===----------------------------------------------------------------------===//
15 /// CCIfSubtarget - Match if the current subtarget has a feature F.
16 class CCIfSubtarget<string F, CCAction A>
17 : CCIf<!strconcat("State.getTarget().getSubtarget<X86Subtarget>().", F), A>;
19 //===----------------------------------------------------------------------===//
20 // Return Value Calling Conventions
21 //===----------------------------------------------------------------------===//
23 // Return-value conventions common to all X86 CC's.
24 def RetCC_X86Common : CallingConv<[
25 // Scalar values are returned in AX first, then DX.
26 CCIfType<[i8] , CCAssignToReg<[AL]>>,
27 CCIfType<[i16], CCAssignToReg<[AX, DX]>>,
28 CCIfType<[i32], CCAssignToReg<[EAX, EDX]>>,
29 CCIfType<[i64], CCAssignToReg<[RAX, RDX]>>,
31 // Vector types are returned in XMM0 and XMM1, when they fit. If the target
32 // doesn't have XMM registers, it won't have vector types.
33 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
34 CCAssignToReg<[XMM0,XMM1]>>,
36 // MMX vector types are always returned in MM0. If the target doesn't have
37 // MM0, it doesn't support these vector types.
38 CCIfType<[v8i8, v4i16, v2i32, v1i64, v2f32], CCAssignToReg<[MM0]>>,
40 // Long double types are always returned in ST0 (even with SSE).
41 CCIfType<[f80], CCAssignToReg<[ST0, ST1]>>
44 // X86-32 C return-value convention.
45 def RetCC_X86_32_C : CallingConv<[
46 // The X86-32 calling convention returns FP values in ST0, unless marked
47 // with "inreg" (used here to distinguish one kind of reg from another,
48 // weirdly; this is really the sse-regparm calling convention) in which
49 // case they use XMM0, otherwise it is the same as the common X86 calling
51 CCIfInReg<CCIfSubtarget<"hasSSE2()",
52 CCIfType<[f32, f64], CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
53 CCIfType<[f32,f64], CCAssignToReg<[ST0, ST1]>>,
54 CCDelegateTo<RetCC_X86Common>
57 // X86-32 FastCC return-value convention.
58 def RetCC_X86_32_Fast : CallingConv<[
59 // The X86-32 fastcc returns 1, 2, or 3 FP values in XMM0-2 if the target has
60 // SSE2, otherwise it is the the C calling conventions.
61 // This can happen when a float, 2 x float, or 3 x float vector is split by
62 // target lowering, and is returned in 1-3 sse regs.
63 CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
64 CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
65 CCDelegateTo<RetCC_X86Common>
68 // X86-32 SSEregparm return-value convention.
69 def RetCC_X86_32_SSE : CallingConv<[
70 // The X86-32 sseregparm calling convention returns FP values in XMM0 if the
71 // target has SSE2, otherwise it is the C calling convention.
72 CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0, XMM1]>>>,
73 CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0, XMM1]>>>,
74 CCDelegateTo<RetCC_X86Common>
77 // X86-64 C return-value convention.
78 def RetCC_X86_64_C : CallingConv<[
79 // The X86-64 calling convention always returns FP values in XMM0.
80 CCIfType<[f32], CCAssignToReg<[XMM0, XMM1]>>,
81 CCIfType<[f64], CCAssignToReg<[XMM0, XMM1]>>,
83 // MMX vector types are always returned in XMM0.
84 CCIfType<[v8i8, v4i16, v2i32, v1i64, v2f32], CCAssignToReg<[XMM0, XMM1]>>,
85 CCDelegateTo<RetCC_X86Common>
88 // X86-Win64 C return-value convention.
89 def RetCC_X86_Win64_C : CallingConv<[
90 // The X86-Win64 calling convention always returns __m64 values in RAX.
91 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToReg<[RAX]>>,
93 // And FP in XMM0 only.
94 CCIfType<[f32], CCAssignToReg<[XMM0]>>,
95 CCIfType<[f64], CCAssignToReg<[XMM0]>>,
97 // Otherwise, everything is the same as 'normal' X86-64 C CC.
98 CCDelegateTo<RetCC_X86_64_C>
102 // This is the root return-value convention for the X86-32 backend.
103 def RetCC_X86_32 : CallingConv<[
104 // If FastCC, use RetCC_X86_32_Fast.
105 CCIfCC<"CallingConv::Fast", CCDelegateTo<RetCC_X86_32_Fast>>,
106 // If SSECC, use RetCC_X86_32_SSE.
107 CCIfCC<"CallingConv::X86_SSECall", CCDelegateTo<RetCC_X86_32_SSE>>,
108 // Otherwise, use RetCC_X86_32_C.
109 CCDelegateTo<RetCC_X86_32_C>
112 // This is the root return-value convention for the X86-64 backend.
113 def RetCC_X86_64 : CallingConv<[
114 // Mingw64 and native Win64 use Win64 CC
115 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<RetCC_X86_Win64_C>>,
117 // Otherwise, drop to normal X86-64 CC
118 CCDelegateTo<RetCC_X86_64_C>
121 // This is the return-value convention used for the entire X86 backend.
122 def RetCC_X86 : CallingConv<[
123 CCIfSubtarget<"is64Bit()", CCDelegateTo<RetCC_X86_64>>,
124 CCDelegateTo<RetCC_X86_32>
127 //===----------------------------------------------------------------------===//
128 // X86-64 Argument Calling Conventions
129 //===----------------------------------------------------------------------===//
131 def CC_X86_64_C : CallingConv<[
132 // Handles byval parameters.
133 CCIfByVal<CCPassByVal<8, 8>>,
135 // Promote i8/i16 arguments to i32.
136 CCIfType<[i8, i16], CCPromoteToType<i32>>,
138 // The 'nest' parameter, if any, is passed in R10.
139 CCIfNest<CCAssignToReg<[R10]>>,
141 // The first 6 integer arguments are passed in integer registers.
142 CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D, R9D]>>,
143 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
145 // The first 8 FP/Vector arguments are passed in XMM registers.
146 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
147 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>,
149 // The first 8 MMX (except for v1i64) vector arguments are passed in XMM
150 // registers on Darwin.
151 CCIfType<[v8i8, v4i16, v2i32, v2f32],
152 CCIfSubtarget<"isTargetDarwin()",
153 CCIfSubtarget<"hasSSE2()",
154 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>>,
156 // The first 8 v1i64 vector arguments are passed in GPRs on Darwin.
158 CCIfSubtarget<"isTargetDarwin()",
159 CCAssignToReg<[RDI, RSI, RDX, RCX, R8]>>>,
161 // Integer/FP values get stored in stack slots that are 8 bytes in size and
162 // 8-byte aligned if there are no more registers to hold them.
163 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
165 // Long doubles get stack slots whose size and alignment depends on the
167 CCIfType<[f80], CCAssignToStack<0, 0>>,
169 // Vectors get 16-byte stack slots that are 16-byte aligned.
170 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
172 // __m64 vectors get 8-byte stack slots that are 8-byte aligned.
173 CCIfType<[v8i8, v4i16, v2i32, v1i64, v2f32], CCAssignToStack<8, 8>>
176 // Calling convention used on Win64
177 def CC_X86_Win64_C : CallingConv<[
178 // FIXME: Handle byval stuff.
179 // FIXME: Handle varargs.
181 // Promote i8/i16 arguments to i32.
182 CCIfType<[i8, i16], CCPromoteToType<i32>>,
184 // The 'nest' parameter, if any, is passed in R10.
185 CCIfNest<CCAssignToReg<[R10]>>,
187 // The first 4 integer arguments are passed in integer registers.
188 CCIfType<[i32], CCAssignToRegWithShadow<[ECX , EDX , R8D , R9D ],
189 [XMM0, XMM1, XMM2, XMM3]>>,
190 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
191 [XMM0, XMM1, XMM2, XMM3]>>,
193 // The first 4 FP/Vector arguments are passed in XMM registers.
194 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
195 CCAssignToRegWithShadow<[XMM0, XMM1, XMM2, XMM3],
196 [RCX , RDX , R8 , R9 ]>>,
198 // The first 4 MMX vector arguments are passed in GPRs.
199 CCIfType<[v8i8, v4i16, v2i32, v1i64, v2f32],
200 CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
201 [XMM0, XMM1, XMM2, XMM3]>>,
203 // Integer/FP values get stored in stack slots that are 8 bytes in size and
204 // 16-byte aligned if there are no more registers to hold them.
205 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 16>>,
207 // Long doubles get stack slots whose size and alignment depends on the
209 CCIfType<[f80], CCAssignToStack<0, 0>>,
211 // Vectors get 16-byte stack slots that are 16-byte aligned.
212 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
214 // __m64 vectors get 8-byte stack slots that are 16-byte aligned.
215 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 16>>
218 // Tail call convention (fast): One register is reserved for target address,
220 def CC_X86_64_TailCall : CallingConv<[
221 // Handles byval parameters.
222 CCIfByVal<CCPassByVal<8, 8>>,
224 // Promote i8/i16 arguments to i32.
225 CCIfType<[i8, i16], CCPromoteToType<i32>>,
227 // The 'nest' parameter, if any, is passed in R10.
228 CCIfNest<CCAssignToReg<[R10]>>,
230 // The first 6 integer arguments are passed in integer registers.
231 CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D]>>,
232 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8]>>,
234 // The first 8 FP/Vector arguments are passed in XMM registers.
235 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
236 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>,
238 // The first 8 MMX (except for v1i64) vector arguments are passed in XMM
239 // registers on Darwin.
240 CCIfType<[v8i8, v4i16, v2i32, v2f32],
241 CCIfSubtarget<"isTargetDarwin()",
242 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>,
244 // The first 8 v1i64 vector arguments are passed in GPRs on Darwin.
246 CCIfSubtarget<"isTargetDarwin()",
247 CCAssignToReg<[RDI, RSI, RDX, RCX, R8]>>>,
249 // Integer/FP values get stored in stack slots that are 8 bytes in size and
250 // 8-byte aligned if there are no more registers to hold them.
251 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
253 // Vectors get 16-byte stack slots that are 16-byte aligned.
254 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
256 // __m64 vectors get 8-byte stack slots that are 8-byte aligned.
257 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 8>>
261 //===----------------------------------------------------------------------===//
262 // X86 C Calling Convention
263 //===----------------------------------------------------------------------===//
265 /// CC_X86_32_Common - In all X86-32 calling conventions, extra integers and FP
266 /// values are spilled on the stack, and the first 4 vector values go in XMM
268 def CC_X86_32_Common : CallingConv<[
269 // Handles byval parameters.
270 CCIfByVal<CCPassByVal<4, 4>>,
272 // The first 3 float or double arguments, if marked 'inreg' and if the call
273 // is not a vararg call and if SSE2 is available, are passed in SSE registers.
274 CCIfNotVarArg<CCIfInReg<CCIfType<[f32,f64],
275 CCIfSubtarget<"hasSSE2()",
276 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>>,
278 // The first 3 __m64 (except for v1i64) vector arguments are passed in mmx
279 // registers if the call is not a vararg call.
280 CCIfNotVarArg<CCIfType<[v8i8, v4i16, v2i32, v2f32],
281 CCAssignToReg<[MM0, MM1, MM2]>>>,
283 // Integer/Float values get stored in stack slots that are 4 bytes in
284 // size and 4-byte aligned.
285 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
287 // Doubles get 8-byte slots that are 4-byte aligned.
288 CCIfType<[f64], CCAssignToStack<8, 4>>,
290 // Long doubles get slots whose size depends on the subtarget.
291 CCIfType<[f80], CCAssignToStack<0, 4>>,
293 // The first 4 SSE vector arguments are passed in XMM registers.
294 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
295 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>>,
297 // Other SSE vectors get 16-byte stack slots that are 16-byte aligned.
298 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
300 // __m64 vectors get 8-byte stack slots that are 4-byte aligned. They are
301 // passed in the parameter area.
302 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 4>>]>;
304 def CC_X86_32_C : CallingConv<[
305 // Promote i8/i16 arguments to i32.
306 CCIfType<[i8, i16], CCPromoteToType<i32>>,
308 // The 'nest' parameter, if any, is passed in ECX.
309 CCIfNest<CCAssignToReg<[ECX]>>,
311 // The first 3 integer arguments, if marked 'inreg' and if the call is not
312 // a vararg call, are passed in integer registers.
313 CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>>>,
315 // Otherwise, same as everything else.
316 CCDelegateTo<CC_X86_32_Common>
319 def CC_X86_32_FastCall : CallingConv<[
320 // Promote i8/i16 arguments to i32.
321 CCIfType<[i8, i16], CCPromoteToType<i32>>,
323 // The 'nest' parameter, if any, is passed in EAX.
324 CCIfNest<CCAssignToReg<[EAX]>>,
326 // The first 2 integer arguments are passed in ECX/EDX
327 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>,
329 // Otherwise, same as everything else.
330 CCDelegateTo<CC_X86_32_Common>
333 def CC_X86_32_FastCC : CallingConv<[
334 // Promote i8/i16 arguments to i32.
335 CCIfType<[i8, i16], CCPromoteToType<i32>>,
337 // The 'nest' parameter, if any, is passed in EAX.
338 CCIfNest<CCAssignToReg<[EAX]>>,
340 // The first 2 integer arguments are passed in ECX/EDX
341 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>,
343 // The first 3 float or double arguments, if the call is not a vararg
344 // call and if SSE2 is available, are passed in SSE registers.
345 CCIfNotVarArg<CCIfType<[f32,f64],
346 CCIfSubtarget<"hasSSE2()",
347 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
349 // Doubles get 8-byte slots that are 8-byte aligned.
350 CCIfType<[f64], CCAssignToStack<8, 8>>,
352 // Otherwise, same as everything else.
353 CCDelegateTo<CC_X86_32_Common>