1 //===- X86CallingConv.td - Calling Conventions X86 32/64 ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This describes the calling conventions for the X86-32 and X86-64
13 //===----------------------------------------------------------------------===//
15 /// CCIfSubtarget - Match if the current subtarget has a feature F.
16 class CCIfSubtarget<string F, CCAction A>
17 : CCIf<!strconcat("State.getTarget().getSubtarget<X86Subtarget>().", F), A>;
19 //===----------------------------------------------------------------------===//
20 // Return Value Calling Conventions
21 //===----------------------------------------------------------------------===//
23 // Return-value conventions common to all X86 CC's.
24 def RetCC_X86Common : CallingConv<[
25 // Scalar values are returned in AX first, then DX.
26 CCIfType<[i8] , CCAssignToReg<[AL]>>,
27 CCIfType<[i16], CCAssignToReg<[AX, DX]>>,
28 CCIfType<[i32], CCAssignToReg<[EAX, EDX]>>,
29 CCIfType<[i64], CCAssignToReg<[RAX, RDX]>>,
31 // Vector types are returned in XMM0 and XMM1, when they fit. XMMM2 and XMM3
32 // can only be used by ABI non-compliant code. If the target doesn't have XMM
33 // registers, it won't have vector types.
34 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
35 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,
37 // MMX vector types are always returned in MM0. If the target doesn't have
38 // MM0, it doesn't support these vector types.
39 CCIfType<[v8i8, v4i16, v2i32, v1i64, v2f32], CCAssignToReg<[MM0]>>,
41 // Long double types are always returned in ST0 (even with SSE).
42 CCIfType<[f80], CCAssignToReg<[ST0, ST1]>>
45 // X86-32 C return-value convention.
46 def RetCC_X86_32_C : CallingConv<[
47 // The X86-32 calling convention returns FP values in ST0, unless marked
48 // with "inreg" (used here to distinguish one kind of reg from another,
49 // weirdly; this is really the sse-regparm calling convention) in which
50 // case they use XMM0, otherwise it is the same as the common X86 calling
52 CCIfInReg<CCIfSubtarget<"hasSSE2()",
53 CCIfType<[f32, f64], CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
54 CCIfType<[f32,f64], CCAssignToReg<[ST0, ST1]>>,
55 CCDelegateTo<RetCC_X86Common>
58 // X86-32 FastCC return-value convention.
59 def RetCC_X86_32_Fast : CallingConv<[
60 // The X86-32 fastcc returns 1, 2, or 3 FP values in XMM0-2 if the target has
61 // SSE2, otherwise it is the the C calling conventions.
62 // This can happen when a float, 2 x float, or 3 x float vector is split by
63 // target lowering, and is returned in 1-3 sse regs.
64 CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
65 CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
66 CCDelegateTo<RetCC_X86Common>
69 // X86-64 C return-value convention.
70 def RetCC_X86_64_C : CallingConv<[
71 // The X86-64 calling convention always returns FP values in XMM0.
72 CCIfType<[f32], CCAssignToReg<[XMM0, XMM1]>>,
73 CCIfType<[f64], CCAssignToReg<[XMM0, XMM1]>>,
75 // MMX vector types are always returned in XMM0.
76 CCIfType<[v8i8, v4i16, v2i32, v1i64, v2f32], CCAssignToReg<[XMM0, XMM1]>>,
77 CCDelegateTo<RetCC_X86Common>
80 // X86-Win64 C return-value convention.
81 def RetCC_X86_Win64_C : CallingConv<[
82 // The X86-Win64 calling convention always returns __m64 values in RAX.
83 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToReg<[RAX]>>,
85 // And FP in XMM0 only.
86 CCIfType<[f32], CCAssignToReg<[XMM0]>>,
87 CCIfType<[f64], CCAssignToReg<[XMM0]>>,
89 // Otherwise, everything is the same as 'normal' X86-64 C CC.
90 CCDelegateTo<RetCC_X86_64_C>
94 // This is the root return-value convention for the X86-32 backend.
95 def RetCC_X86_32 : CallingConv<[
96 // If FastCC, use RetCC_X86_32_Fast.
97 CCIfCC<"CallingConv::Fast", CCDelegateTo<RetCC_X86_32_Fast>>,
98 // Otherwise, use RetCC_X86_32_C.
99 CCDelegateTo<RetCC_X86_32_C>
102 // This is the root return-value convention for the X86-64 backend.
103 def RetCC_X86_64 : CallingConv<[
104 // Mingw64 and native Win64 use Win64 CC
105 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<RetCC_X86_Win64_C>>,
107 // Otherwise, drop to normal X86-64 CC
108 CCDelegateTo<RetCC_X86_64_C>
111 // This is the return-value convention used for the entire X86 backend.
112 def RetCC_X86 : CallingConv<[
113 CCIfSubtarget<"is64Bit()", CCDelegateTo<RetCC_X86_64>>,
114 CCDelegateTo<RetCC_X86_32>
117 //===----------------------------------------------------------------------===//
118 // X86-64 Argument Calling Conventions
119 //===----------------------------------------------------------------------===//
121 def CC_X86_64_C : CallingConv<[
122 // Handles byval parameters.
123 CCIfByVal<CCPassByVal<8, 8>>,
125 // Promote i8/i16 arguments to i32.
126 CCIfType<[i8, i16], CCPromoteToType<i32>>,
128 // The 'nest' parameter, if any, is passed in R10.
129 CCIfNest<CCAssignToReg<[R10]>>,
131 // The first 6 integer arguments are passed in integer registers.
132 CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D, R9D]>>,
133 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
135 // The first 8 FP/Vector arguments are passed in XMM registers.
136 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
137 CCIfSubtarget<"hasSSE1()",
138 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>,
140 // The first 8 MMX (except for v1i64) vector arguments are passed in XMM
141 // registers on Darwin.
142 CCIfType<[v8i8, v4i16, v2i32, v2f32],
143 CCIfSubtarget<"isTargetDarwin()",
144 CCIfSubtarget<"hasSSE2()",
145 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>>,
147 // The first 8 v1i64 vector arguments are passed in GPRs on Darwin.
149 CCIfSubtarget<"isTargetDarwin()",
150 CCAssignToReg<[RDI, RSI, RDX, RCX, R8]>>>,
152 // Integer/FP values get stored in stack slots that are 8 bytes in size and
153 // 8-byte aligned if there are no more registers to hold them.
154 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
156 // Long doubles get stack slots whose size and alignment depends on the
158 CCIfType<[f80], CCAssignToStack<0, 0>>,
160 // Vectors get 16-byte stack slots that are 16-byte aligned.
161 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
163 // __m64 vectors get 8-byte stack slots that are 8-byte aligned.
164 CCIfType<[v8i8, v4i16, v2i32, v1i64, v2f32], CCAssignToStack<8, 8>>
167 // Calling convention used on Win64
168 def CC_X86_Win64_C : CallingConv<[
169 // FIXME: Handle byval stuff.
170 // FIXME: Handle varargs.
172 // Promote i8/i16 arguments to i32.
173 CCIfType<[i8, i16], CCPromoteToType<i32>>,
175 // The 'nest' parameter, if any, is passed in R10.
176 CCIfNest<CCAssignToReg<[R10]>>,
178 // The first 4 integer arguments are passed in integer registers.
179 CCIfType<[i32], CCAssignToRegWithShadow<[ECX , EDX , R8D , R9D ],
180 [XMM0, XMM1, XMM2, XMM3]>>,
181 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
182 [XMM0, XMM1, XMM2, XMM3]>>,
184 // The first 4 FP/Vector arguments are passed in XMM registers.
185 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
186 CCAssignToRegWithShadow<[XMM0, XMM1, XMM2, XMM3],
187 [RCX , RDX , R8 , R9 ]>>,
189 // The first 4 MMX vector arguments are passed in GPRs.
190 CCIfType<[v8i8, v4i16, v2i32, v1i64, v2f32],
191 CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
192 [XMM0, XMM1, XMM2, XMM3]>>,
194 // Integer/FP values get stored in stack slots that are 8 bytes in size and
195 // 16-byte aligned if there are no more registers to hold them.
196 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 16>>,
198 // Long doubles get stack slots whose size and alignment depends on the
200 CCIfType<[f80], CCAssignToStack<0, 0>>,
202 // Vectors get 16-byte stack slots that are 16-byte aligned.
203 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
205 // __m64 vectors get 8-byte stack slots that are 16-byte aligned.
206 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 16>>
209 // Tail call convention (fast): One register is reserved for target address,
211 def CC_X86_64_TailCall : CallingConv<[
212 // Handles byval parameters.
213 CCIfByVal<CCPassByVal<8, 8>>,
215 // Promote i8/i16 arguments to i32.
216 CCIfType<[i8, i16], CCPromoteToType<i32>>,
218 // The 'nest' parameter, if any, is passed in R10.
219 CCIfNest<CCAssignToReg<[R10]>>,
221 // The first 6 integer arguments are passed in integer registers.
222 CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D]>>,
223 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8]>>,
225 // The first 8 FP/Vector arguments are passed in XMM registers.
226 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
227 CCIfSubtarget<"hasSSE1()",
228 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>,
230 // The first 8 MMX (except for v1i64) vector arguments are passed in XMM
231 // registers on Darwin.
232 CCIfType<[v8i8, v4i16, v2i32, v2f32],
233 CCIfSubtarget<"isTargetDarwin()",
234 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>,
236 // The first 8 v1i64 vector arguments are passed in GPRs on Darwin.
238 CCIfSubtarget<"isTargetDarwin()",
239 CCAssignToReg<[RDI, RSI, RDX, RCX, R8]>>>,
241 // Integer/FP values get stored in stack slots that are 8 bytes in size and
242 // 8-byte aligned if there are no more registers to hold them.
243 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
245 // Vectors get 16-byte stack slots that are 16-byte aligned.
246 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
248 // __m64 vectors get 8-byte stack slots that are 8-byte aligned.
249 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 8>>
253 //===----------------------------------------------------------------------===//
254 // X86 C Calling Convention
255 //===----------------------------------------------------------------------===//
257 /// CC_X86_32_Common - In all X86-32 calling conventions, extra integers and FP
258 /// values are spilled on the stack, and the first 4 vector values go in XMM
260 def CC_X86_32_Common : CallingConv<[
261 // Handles byval parameters.
262 CCIfByVal<CCPassByVal<4, 4>>,
264 // The first 3 float or double arguments, if marked 'inreg' and if the call
265 // is not a vararg call and if SSE2 is available, are passed in SSE registers.
266 CCIfNotVarArg<CCIfInReg<CCIfType<[f32,f64],
267 CCIfSubtarget<"hasSSE2()",
268 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>>,
270 // The first 3 __m64 (except for v1i64) vector arguments are passed in mmx
271 // registers if the call is not a vararg call.
272 CCIfNotVarArg<CCIfType<[v8i8, v4i16, v2i32, v2f32],
273 CCAssignToReg<[MM0, MM1, MM2]>>>,
275 // Integer/Float values get stored in stack slots that are 4 bytes in
276 // size and 4-byte aligned.
277 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
279 // Doubles get 8-byte slots that are 4-byte aligned.
280 CCIfType<[f64], CCAssignToStack<8, 4>>,
282 // Long doubles get slots whose size depends on the subtarget.
283 CCIfType<[f80], CCAssignToStack<0, 4>>,
285 // The first 4 SSE vector arguments are passed in XMM registers.
286 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
287 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>>,
289 // Other SSE vectors get 16-byte stack slots that are 16-byte aligned.
290 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
292 // __m64 vectors get 8-byte stack slots that are 4-byte aligned. They are
293 // passed in the parameter area.
294 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 4>>]>;
296 def CC_X86_32_C : CallingConv<[
297 // Promote i8/i16 arguments to i32.
298 CCIfType<[i8, i16], CCPromoteToType<i32>>,
300 // The 'nest' parameter, if any, is passed in ECX.
301 CCIfNest<CCAssignToReg<[ECX]>>,
303 // The first 3 integer arguments, if marked 'inreg' and if the call is not
304 // a vararg call, are passed in integer registers.
305 CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>>>,
307 // Otherwise, same as everything else.
308 CCDelegateTo<CC_X86_32_Common>
311 def CC_X86_32_FastCall : CallingConv<[
312 // Promote i8/i16 arguments to i32.
313 CCIfType<[i8, i16], CCPromoteToType<i32>>,
315 // The 'nest' parameter, if any, is passed in EAX.
316 CCIfNest<CCAssignToReg<[EAX]>>,
318 // The first 2 integer arguments are passed in ECX/EDX
319 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>,
321 // Otherwise, same as everything else.
322 CCDelegateTo<CC_X86_32_Common>
325 def CC_X86_32_FastCC : CallingConv<[
326 // Handles byval parameters. Note that we can't rely on the delegation
327 // to CC_X86_32_Common for this because that happens after code that
328 // puts arguments in registers.
329 CCIfByVal<CCPassByVal<4, 4>>,
331 // Promote i8/i16 arguments to i32.
332 CCIfType<[i8, i16], CCPromoteToType<i32>>,
334 // The 'nest' parameter, if any, is passed in EAX.
335 CCIfNest<CCAssignToReg<[EAX]>>,
337 // The first 2 integer arguments are passed in ECX/EDX
338 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>,
340 // The first 3 float or double arguments, if the call is not a vararg
341 // call and if SSE2 is available, are passed in SSE registers.
342 CCIfNotVarArg<CCIfType<[f32,f64],
343 CCIfSubtarget<"hasSSE2()",
344 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
346 // Doubles get 8-byte slots that are 8-byte aligned.
347 CCIfType<[f64], CCAssignToStack<8, 8>>,
349 // Otherwise, same as everything else.
350 CCDelegateTo<CC_X86_32_Common>