1 //===-- X86CallingConv.td - Calling Conventions X86 32/64 --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This describes the calling conventions for the X86-32 and X86-64
13 //===----------------------------------------------------------------------===//
15 /// CCIfSubtarget - Match if the current subtarget has a feature F.
16 class CCIfSubtarget<string F, CCAction A>
17 : CCIf<!strconcat("static_cast<const X86Subtarget&>"
18 "(State.getMachineFunction().getSubtarget()).", F),
21 //===----------------------------------------------------------------------===//
22 // Return Value Calling Conventions
23 //===----------------------------------------------------------------------===//
25 // Return-value conventions common to all X86 CC's.
26 def RetCC_X86Common : CallingConv<[
27 // Scalar values are returned in AX first, then DX. For i8, the ABI
28 // requires the values to be in AL and AH, however this code uses AL and DL
29 // instead. This is because using AH for the second register conflicts with
30 // the way LLVM does multiple return values -- a return of {i16,i8} would end
31 // up in AX and AH, which overlap. Front-ends wishing to conform to the ABI
32 // for functions that return two i8 values are currently expected to pack the
33 // values into an i16 (which uses AX, and thus AL:AH).
35 // For code that doesn't care about the ABI, we allow returning more than two
36 // integer values in registers.
37 CCIfType<[i1], CCPromoteToType<i8>>,
38 CCIfType<[i8] , CCAssignToReg<[AL, DL, CL]>>,
39 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>,
40 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>,
41 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX]>>,
43 // Boolean vectors of AVX-512 are returned in SIMD registers.
44 // The call from AVX to AVX-512 function should work,
45 // since the boolean types in AVX/AVX2 are promoted by default.
46 CCIfType<[v2i1], CCPromoteToType<v2i64>>,
47 CCIfType<[v4i1], CCPromoteToType<v4i32>>,
48 CCIfType<[v8i1], CCPromoteToType<v8i16>>,
49 CCIfType<[v16i1], CCPromoteToType<v16i8>>,
50 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
51 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
53 // Vector types are returned in XMM0 and XMM1, when they fit. XMM2 and XMM3
54 // can only be used by ABI non-compliant code. If the target doesn't have XMM
55 // registers, it won't have vector types.
56 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
57 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,
59 // 256-bit vectors are returned in YMM0 and XMM1, when they fit. YMM2 and YMM3
60 // can only be used by ABI non-compliant code. This vector type is only
61 // supported while using the AVX target feature.
62 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
63 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>,
65 // 512-bit vectors are returned in ZMM0 and ZMM1, when they fit. ZMM2 and ZMM3
66 // can only be used by ABI non-compliant code. This vector type is only
67 // supported while using the AVX-512 target feature.
68 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
69 CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>,
71 // MMX vector types are always returned in MM0. If the target doesn't have
72 // MM0, it doesn't support these vector types.
73 CCIfType<[x86mmx], CCAssignToReg<[MM0]>>,
75 // Long double types are always returned in FP0 (even with SSE).
76 CCIfType<[f80], CCAssignToReg<[FP0, FP1]>>
79 // X86-32 C return-value convention.
80 def RetCC_X86_32_C : CallingConv<[
81 // The X86-32 calling convention returns FP values in FP0, unless marked
82 // with "inreg" (used here to distinguish one kind of reg from another,
83 // weirdly; this is really the sse-regparm calling convention) in which
84 // case they use XMM0, otherwise it is the same as the common X86 calling
86 CCIfInReg<CCIfSubtarget<"hasSSE2()",
87 CCIfType<[f32, f64], CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
88 CCIfType<[f32,f64], CCAssignToReg<[FP0, FP1]>>,
89 CCDelegateTo<RetCC_X86Common>
92 // X86-32 FastCC return-value convention.
93 def RetCC_X86_32_Fast : CallingConv<[
94 // The X86-32 fastcc returns 1, 2, or 3 FP values in XMM0-2 if the target has
96 // This can happen when a float, 2 x float, or 3 x float vector is split by
97 // target lowering, and is returned in 1-3 sse regs.
98 CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
99 CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
101 // For integers, ECX can be used as an extra return register
102 CCIfType<[i8], CCAssignToReg<[AL, DL, CL]>>,
103 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>,
104 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>,
106 // Otherwise, it is the same as the common X86 calling convention.
107 CCDelegateTo<RetCC_X86Common>
110 // Intel_OCL_BI return-value convention.
111 def RetCC_Intel_OCL_BI : CallingConv<[
112 // Vector types are returned in XMM0,XMM1,XMMM2 and XMM3.
113 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64],
114 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,
116 // 256-bit FP vectors
117 // No more than 4 registers
118 CCIfType<[v8f32, v4f64, v8i32, v4i64],
119 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>,
121 // 512-bit FP vectors
122 CCIfType<[v16f32, v8f64, v16i32, v8i64],
123 CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>,
125 // i32, i64 in the standard way
126 CCDelegateTo<RetCC_X86Common>
129 // X86-32 HiPE return-value convention.
130 def RetCC_X86_32_HiPE : CallingConv<[
131 // Promote all types to i32
132 CCIfType<[i8, i16], CCPromoteToType<i32>>,
134 // Return: HP, P, VAL1, VAL2
135 CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX]>>
138 // X86-32 HiPE return-value convention.
139 def RetCC_X86_32_VectorCall : CallingConv<[
140 // Vector types are returned in XMM0,XMM1,XMMM2 and XMM3.
141 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
142 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,
144 // 256-bit FP vectors
145 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
146 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>,
148 // 512-bit FP vectors
149 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
150 CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>,
152 // Return integers in the standard way.
153 CCDelegateTo<RetCC_X86Common>
156 // X86-64 C return-value convention.
157 def RetCC_X86_64_C : CallingConv<[
158 // The X86-64 calling convention always returns FP values in XMM0.
159 CCIfType<[f32], CCAssignToReg<[XMM0, XMM1]>>,
160 CCIfType<[f64], CCAssignToReg<[XMM0, XMM1]>>,
162 // MMX vector types are always returned in XMM0.
163 CCIfType<[x86mmx], CCAssignToReg<[XMM0, XMM1]>>,
164 CCDelegateTo<RetCC_X86Common>
167 // X86-Win64 C return-value convention.
168 def RetCC_X86_Win64_C : CallingConv<[
169 // The X86-Win64 calling convention always returns __m64 values in RAX.
170 CCIfType<[x86mmx], CCBitConvertToType<i64>>,
172 // Otherwise, everything is the same as 'normal' X86-64 C CC.
173 CCDelegateTo<RetCC_X86_64_C>
176 // X86-64 HiPE return-value convention.
177 def RetCC_X86_64_HiPE : CallingConv<[
178 // Promote all types to i64
179 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
181 // Return: HP, P, VAL1, VAL2
182 CCIfType<[i64], CCAssignToReg<[R15, RBP, RAX, RDX]>>
185 // X86-64 WebKit_JS return-value convention.
186 def RetCC_X86_64_WebKit_JS : CallingConv<[
187 // Promote all types to i64
188 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
191 CCIfType<[i64], CCAssignToReg<[RAX]>>
194 // X86-64 AnyReg return-value convention. No explicit register is specified for
195 // the return-value. The register allocator is allowed and expected to choose
196 // any free register.
198 // This calling convention is currently only supported by the stackmap and
199 // patchpoint intrinsics. All other uses will result in an assert on Debug
200 // builds. On Release builds we fallback to the X86 C calling convention.
201 def RetCC_X86_64_AnyReg : CallingConv<[
202 CCCustom<"CC_X86_AnyReg_Error">
205 // X86-64 HHVM return-value convention.
206 def RetCC_X86_64_HHVM: CallingConv<[
207 // Promote all types to i64
208 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
210 // Return: could return in any GP register save RSP and R12.
211 CCIfType<[i64], CCAssignToReg<[RBX, RBP, RDI, RSI, RDX, RCX, R8, R9,
212 RAX, R10, R11, R13, R14, R15]>>
215 // This is the root return-value convention for the X86-32 backend.
216 def RetCC_X86_32 : CallingConv<[
217 // If FastCC, use RetCC_X86_32_Fast.
218 CCIfCC<"CallingConv::Fast", CCDelegateTo<RetCC_X86_32_Fast>>,
219 // If HiPE, use RetCC_X86_32_HiPE.
220 CCIfCC<"CallingConv::HiPE", CCDelegateTo<RetCC_X86_32_HiPE>>,
221 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<RetCC_X86_32_VectorCall>>,
223 // Otherwise, use RetCC_X86_32_C.
224 CCDelegateTo<RetCC_X86_32_C>
227 // This is the root return-value convention for the X86-64 backend.
228 def RetCC_X86_64 : CallingConv<[
229 // HiPE uses RetCC_X86_64_HiPE
230 CCIfCC<"CallingConv::HiPE", CCDelegateTo<RetCC_X86_64_HiPE>>,
232 // Handle JavaScript calls.
233 CCIfCC<"CallingConv::WebKit_JS", CCDelegateTo<RetCC_X86_64_WebKit_JS>>,
234 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<RetCC_X86_64_AnyReg>>,
236 // Handle explicit CC selection
237 CCIfCC<"CallingConv::X86_64_Win64", CCDelegateTo<RetCC_X86_Win64_C>>,
238 CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo<RetCC_X86_64_C>>,
240 // Handle HHVM calls.
241 CCIfCC<"CallingConv::HHVM", CCDelegateTo<RetCC_X86_64_HHVM>>,
243 // Mingw64 and native Win64 use Win64 CC
244 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<RetCC_X86_Win64_C>>,
246 // Otherwise, drop to normal X86-64 CC
247 CCDelegateTo<RetCC_X86_64_C>
250 // This is the return-value convention used for the entire X86 backend.
251 def RetCC_X86 : CallingConv<[
253 // Check if this is the Intel OpenCL built-ins calling convention
254 CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo<RetCC_Intel_OCL_BI>>,
256 CCIfSubtarget<"is64Bit()", CCDelegateTo<RetCC_X86_64>>,
257 CCDelegateTo<RetCC_X86_32>
260 //===----------------------------------------------------------------------===//
261 // X86-64 Argument Calling Conventions
262 //===----------------------------------------------------------------------===//
264 def CC_X86_64_C : CallingConv<[
265 // Handles byval parameters.
266 CCIfByVal<CCPassByVal<8, 8>>,
268 // Promote i1/i8/i16 arguments to i32.
269 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
271 // The 'nest' parameter, if any, is passed in R10.
272 CCIfNest<CCIfSubtarget<"isTarget64BitILP32()", CCAssignToReg<[R10D]>>>,
273 CCIfNest<CCAssignToReg<[R10]>>,
275 // The first 6 integer arguments are passed in integer registers.
276 CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D, R9D]>>,
277 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
279 // The first 8 MMX vector arguments are passed in XMM registers on Darwin.
281 CCIfSubtarget<"isTargetDarwin()",
282 CCIfSubtarget<"hasSSE2()",
283 CCPromoteToType<v2i64>>>>,
285 // Boolean vectors of AVX-512 are passed in SIMD registers.
286 // The call from AVX to AVX-512 function should work,
287 // since the boolean types in AVX/AVX2 are promoted by default.
288 CCIfType<[v2i1], CCPromoteToType<v2i64>>,
289 CCIfType<[v4i1], CCPromoteToType<v4i32>>,
290 CCIfType<[v8i1], CCPromoteToType<v8i16>>,
291 CCIfType<[v16i1], CCPromoteToType<v16i8>>,
292 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
293 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
295 // The first 8 FP/Vector arguments are passed in XMM registers.
296 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
297 CCIfSubtarget<"hasSSE1()",
298 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>,
300 // The first 8 256-bit vector arguments are passed in YMM registers, unless
301 // this is a vararg function.
302 // FIXME: This isn't precisely correct; the x86-64 ABI document says that
303 // fixed arguments to vararg functions are supposed to be passed in
304 // registers. Actually modeling that would be a lot of work, though.
305 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
306 CCIfSubtarget<"hasFp256()",
307 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3,
308 YMM4, YMM5, YMM6, YMM7]>>>>,
310 // The first 8 512-bit vector arguments are passed in ZMM registers.
311 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
312 CCIfSubtarget<"hasAVX512()",
313 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7]>>>>,
315 // Integer/FP values get stored in stack slots that are 8 bytes in size and
316 // 8-byte aligned if there are no more registers to hold them.
317 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
319 // Long doubles get stack slots whose size and alignment depends on the
321 CCIfType<[f80], CCAssignToStack<0, 0>>,
323 // Vectors get 16-byte stack slots that are 16-byte aligned.
324 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
326 // 256-bit vectors get 32-byte stack slots that are 32-byte aligned.
327 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
328 CCAssignToStack<32, 32>>,
330 // 512-bit vectors get 64-byte stack slots that are 64-byte aligned.
331 CCIfType<[v16i32, v8i64, v16f32, v8f64],
332 CCAssignToStack<64, 64>>
335 // Calling convention for X86-64 HHVM.
336 def CC_X86_64_HHVM : CallingConv<[
337 // Use all/any GP registers for args, except RSP.
338 CCIfType<[i64], CCAssignToReg<[RBX, R12, RBP, R15,
339 RDI, RSI, RDX, RCX, R8, R9,
340 RAX, R10, R11, R13, R14]>>
343 // Calling convention for helper functions in HHVM.
344 def CC_X86_64_HHVM_C : CallingConv<[
345 // Pass the first argument in RBP.
346 CCIfType<[i64], CCAssignToReg<[RBP]>>,
348 // Otherwise it's the same as the regular C calling convention.
349 CCDelegateTo<CC_X86_64_C>
352 // Calling convention used on Win64
353 def CC_X86_Win64_C : CallingConv<[
354 // FIXME: Handle byval stuff.
355 // FIXME: Handle varargs.
357 // Promote i1/i8/i16 arguments to i32.
358 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
360 // The 'nest' parameter, if any, is passed in R10.
361 CCIfNest<CCAssignToReg<[R10]>>,
363 // 128 bit vectors are passed by pointer
364 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCPassIndirect<i64>>,
367 // 256 bit vectors are passed by pointer
368 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>,
370 // 512 bit vectors are passed by pointer
371 CCIfType<[v16i32, v16f32, v8f64, v8i64], CCPassIndirect<i64>>,
373 // The first 4 MMX vector arguments are passed in GPRs.
374 CCIfType<[x86mmx], CCBitConvertToType<i64>>,
376 // The first 4 integer arguments are passed in integer registers.
377 CCIfType<[i32], CCAssignToRegWithShadow<[ECX , EDX , R8D , R9D ],
378 [XMM0, XMM1, XMM2, XMM3]>>,
380 // Do not pass the sret argument in RCX, the Win64 thiscall calling
381 // convention requires "this" to be passed in RCX.
382 CCIfCC<"CallingConv::X86_ThisCall",
383 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[RDX , R8 , R9 ],
384 [XMM1, XMM2, XMM3]>>>>,
386 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
387 [XMM0, XMM1, XMM2, XMM3]>>,
389 // The first 4 FP/Vector arguments are passed in XMM registers.
390 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
391 CCAssignToRegWithShadow<[XMM0, XMM1, XMM2, XMM3],
392 [RCX , RDX , R8 , R9 ]>>,
394 // Integer/FP values get stored in stack slots that are 8 bytes in size and
395 // 8-byte aligned if there are no more registers to hold them.
396 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
398 // Long doubles get stack slots whose size and alignment depends on the
400 CCIfType<[f80], CCAssignToStack<0, 0>>
403 def CC_X86_Win64_VectorCall : CallingConv<[
404 // The first 6 floating point and vector types of 128 bits or less use
406 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
407 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5]>>,
409 // 256-bit vectors use YMM registers.
410 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
411 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3, YMM4, YMM5]>>,
413 // 512-bit vectors use ZMM registers.
414 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
415 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5]>>,
417 // Delegate to fastcall to handle integer types.
418 CCDelegateTo<CC_X86_Win64_C>
422 def CC_X86_64_GHC : CallingConv<[
423 // Promote i8/i16/i32 arguments to i64.
424 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
426 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim
428 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
430 // Pass in STG registers: F1, F2, F3, F4, D1, D2
431 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
432 CCIfSubtarget<"hasSSE1()",
433 CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>
436 def CC_X86_64_HiPE : CallingConv<[
437 // Promote i8/i16/i32 arguments to i64.
438 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
440 // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2, ARG3
441 CCIfType<[i64], CCAssignToReg<[R15, RBP, RSI, RDX, RCX, R8]>>,
443 // Integer/FP values get stored in stack slots that are 8 bytes in size and
444 // 8-byte aligned if there are no more registers to hold them.
445 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>
448 def CC_X86_64_WebKit_JS : CallingConv<[
449 // Promote i8/i16 arguments to i32.
450 CCIfType<[i8, i16], CCPromoteToType<i32>>,
452 // Only the first integer argument is passed in register.
453 CCIfType<[i32], CCAssignToReg<[EAX]>>,
454 CCIfType<[i64], CCAssignToReg<[RAX]>>,
456 // The remaining integer arguments are passed on the stack. 32bit integer and
457 // floating-point arguments are aligned to 4 byte and stored in 4 byte slots.
458 // 64bit integer and floating-point arguments are aligned to 8 byte and stored
459 // in 8 byte stack slots.
460 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
461 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
464 // No explicit register is specified for the AnyReg calling convention. The
465 // register allocator may assign the arguments to any free register.
467 // This calling convention is currently only supported by the stackmap and
468 // patchpoint intrinsics. All other uses will result in an assert on Debug
469 // builds. On Release builds we fallback to the X86 C calling convention.
470 def CC_X86_64_AnyReg : CallingConv<[
471 CCCustom<"CC_X86_AnyReg_Error">
474 //===----------------------------------------------------------------------===//
475 // X86 C Calling Convention
476 //===----------------------------------------------------------------------===//
478 /// CC_X86_32_Vector_Common - In all X86-32 calling conventions, extra vector
479 /// values are spilled on the stack.
480 def CC_X86_32_Vector_Common : CallingConv<[
481 // Other SSE vectors get 16-byte stack slots that are 16-byte aligned.
482 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
484 // 256-bit AVX vectors get 32-byte stack slots that are 32-byte aligned.
485 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
486 CCAssignToStack<32, 32>>,
488 // 512-bit AVX 512-bit vectors get 64-byte stack slots that are 64-byte aligned.
489 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
490 CCAssignToStack<64, 64>>
493 // CC_X86_32_Vector_Standard - The first 3 vector arguments are passed in
495 def CC_X86_32_Vector_Standard : CallingConv<[
496 // SSE vector arguments are passed in XMM registers.
497 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
498 CCAssignToReg<[XMM0, XMM1, XMM2]>>>,
500 // AVX 256-bit vector arguments are passed in YMM registers.
501 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
502 CCIfSubtarget<"hasFp256()",
503 CCAssignToReg<[YMM0, YMM1, YMM2]>>>>,
505 // AVX 512-bit vector arguments are passed in ZMM registers.
506 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
507 CCAssignToReg<[ZMM0, ZMM1, ZMM2]>>>,
509 CCDelegateTo<CC_X86_32_Vector_Common>
512 // CC_X86_32_Vector_Darwin - The first 4 vector arguments are passed in
514 def CC_X86_32_Vector_Darwin : CallingConv<[
515 // SSE vector arguments are passed in XMM registers.
516 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
517 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>>,
519 // AVX 256-bit vector arguments are passed in YMM registers.
520 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
521 CCIfSubtarget<"hasFp256()",
522 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>>>,
524 // AVX 512-bit vector arguments are passed in ZMM registers.
525 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
526 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3]>>>,
528 CCDelegateTo<CC_X86_32_Vector_Common>
531 /// CC_X86_32_Common - In all X86-32 calling conventions, extra integers and FP
532 /// values are spilled on the stack.
533 def CC_X86_32_Common : CallingConv<[
534 // Handles byval parameters.
535 CCIfByVal<CCPassByVal<4, 4>>,
537 // The first 3 float or double arguments, if marked 'inreg' and if the call
538 // is not a vararg call and if SSE2 is available, are passed in SSE registers.
539 CCIfNotVarArg<CCIfInReg<CCIfType<[f32,f64],
540 CCIfSubtarget<"hasSSE2()",
541 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>>,
543 // The first 3 __m64 vector arguments are passed in mmx registers if the
544 // call is not a vararg call.
545 CCIfNotVarArg<CCIfType<[x86mmx],
546 CCAssignToReg<[MM0, MM1, MM2]>>>,
548 // Integer/Float values get stored in stack slots that are 4 bytes in
549 // size and 4-byte aligned.
550 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
552 // Doubles get 8-byte slots that are 4-byte aligned.
553 CCIfType<[f64], CCAssignToStack<8, 4>>,
555 // Long doubles get slots whose size depends on the subtarget.
556 CCIfType<[f80], CCAssignToStack<0, 4>>,
558 // Boolean vectors of AVX-512 are passed in SIMD registers.
559 // The call from AVX to AVX-512 function should work,
560 // since the boolean types in AVX/AVX2 are promoted by default.
561 CCIfType<[v2i1], CCPromoteToType<v2i64>>,
562 CCIfType<[v4i1], CCPromoteToType<v4i32>>,
563 CCIfType<[v8i1], CCPromoteToType<v8i16>>,
564 CCIfType<[v16i1], CCPromoteToType<v16i8>>,
565 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
566 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
568 // __m64 vectors get 8-byte stack slots that are 4-byte aligned. They are
569 // passed in the parameter area.
570 CCIfType<[x86mmx], CCAssignToStack<8, 4>>,
572 // Darwin passes vectors in a form that differs from the i386 psABI
573 CCIfSubtarget<"isTargetDarwin()", CCDelegateTo<CC_X86_32_Vector_Darwin>>,
575 // Otherwise, drop to 'normal' X86-32 CC
576 CCDelegateTo<CC_X86_32_Vector_Standard>
579 def CC_X86_32_C : CallingConv<[
580 // Promote i1/i8/i16 arguments to i32.
581 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
583 // The 'nest' parameter, if any, is passed in ECX.
584 CCIfNest<CCAssignToReg<[ECX]>>,
586 // The first 3 integer arguments, if marked 'inreg' and if the call is not
587 // a vararg call, are passed in integer registers.
588 CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>>>,
590 // Otherwise, same as everything else.
591 CCDelegateTo<CC_X86_32_Common>
594 def CC_X86_32_FastCall : CallingConv<[
595 // Promote i1/i8/i16 arguments to i32.
596 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
598 // The 'nest' parameter, if any, is passed in EAX.
599 CCIfNest<CCAssignToReg<[EAX]>>,
601 // The first 2 integer arguments are passed in ECX/EDX
602 CCIfInReg<CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>>,
604 // Otherwise, same as everything else.
605 CCDelegateTo<CC_X86_32_Common>
608 def CC_X86_32_VectorCall : CallingConv<[
609 // The first 6 floating point and vector types of 128 bits or less use
611 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
612 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5]>>,
614 // 256-bit vectors use YMM registers.
615 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
616 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3, YMM4, YMM5]>>,
618 // 512-bit vectors use ZMM registers.
619 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
620 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5]>>,
622 // Otherwise, pass it indirectly.
623 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64,
624 v32i8, v16i16, v8i32, v4i64, v8f32, v4f64,
625 v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
626 CCCustom<"CC_X86_32_VectorCallIndirect">>,
628 // Delegate to fastcall to handle integer types.
629 CCDelegateTo<CC_X86_32_FastCall>
632 def CC_X86_32_ThisCall_Common : CallingConv<[
633 // The first integer argument is passed in ECX
634 CCIfType<[i32], CCAssignToReg<[ECX]>>,
636 // Otherwise, same as everything else.
637 CCDelegateTo<CC_X86_32_Common>
640 def CC_X86_32_ThisCall_Mingw : CallingConv<[
641 // Promote i1/i8/i16 arguments to i32.
642 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
644 CCDelegateTo<CC_X86_32_ThisCall_Common>
647 def CC_X86_32_ThisCall_Win : CallingConv<[
648 // Promote i1/i8/i16 arguments to i32.
649 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
651 // Pass sret arguments indirectly through stack.
652 CCIfSRet<CCAssignToStack<4, 4>>,
654 CCDelegateTo<CC_X86_32_ThisCall_Common>
657 def CC_X86_32_ThisCall : CallingConv<[
658 CCIfSubtarget<"isTargetCygMing()", CCDelegateTo<CC_X86_32_ThisCall_Mingw>>,
659 CCDelegateTo<CC_X86_32_ThisCall_Win>
662 def CC_X86_32_FastCC : CallingConv<[
663 // Handles byval parameters. Note that we can't rely on the delegation
664 // to CC_X86_32_Common for this because that happens after code that
665 // puts arguments in registers.
666 CCIfByVal<CCPassByVal<4, 4>>,
668 // Promote i1/i8/i16 arguments to i32.
669 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
671 // The 'nest' parameter, if any, is passed in EAX.
672 CCIfNest<CCAssignToReg<[EAX]>>,
674 // The first 2 integer arguments are passed in ECX/EDX
675 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>,
677 // The first 3 float or double arguments, if the call is not a vararg
678 // call and if SSE2 is available, are passed in SSE registers.
679 CCIfNotVarArg<CCIfType<[f32,f64],
680 CCIfSubtarget<"hasSSE2()",
681 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
683 // Doubles get 8-byte slots that are 8-byte aligned.
684 CCIfType<[f64], CCAssignToStack<8, 8>>,
686 // Otherwise, same as everything else.
687 CCDelegateTo<CC_X86_32_Common>
690 def CC_X86_32_GHC : CallingConv<[
691 // Promote i8/i16 arguments to i32.
692 CCIfType<[i8, i16], CCPromoteToType<i32>>,
694 // Pass in STG registers: Base, Sp, Hp, R1
695 CCIfType<[i32], CCAssignToReg<[EBX, EBP, EDI, ESI]>>
698 def CC_X86_32_HiPE : CallingConv<[
699 // Promote i8/i16 arguments to i32.
700 CCIfType<[i8, i16], CCPromoteToType<i32>>,
702 // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2
703 CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX, ECX]>>,
705 // Integer/Float values get stored in stack slots that are 4 bytes in
706 // size and 4-byte aligned.
707 CCIfType<[i32, f32], CCAssignToStack<4, 4>>
710 // X86-64 Intel OpenCL built-ins calling convention.
711 def CC_Intel_OCL_BI : CallingConv<[
713 CCIfType<[i32], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[ECX, EDX, R8D, R9D]>>>,
714 CCIfType<[i64], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[RCX, RDX, R8, R9 ]>>>,
716 CCIfType<[i32], CCIfSubtarget<"is64Bit()", CCAssignToReg<[EDI, ESI, EDX, ECX]>>>,
717 CCIfType<[i64], CCIfSubtarget<"is64Bit()", CCAssignToReg<[RDI, RSI, RDX, RCX]>>>,
719 CCIfType<[i32], CCAssignToStack<4, 4>>,
721 // The SSE vector arguments are passed in XMM registers.
722 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64],
723 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>,
725 // The 256-bit vector arguments are passed in YMM registers.
726 CCIfType<[v8f32, v4f64, v8i32, v4i64],
727 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>,
729 // The 512-bit vector arguments are passed in ZMM registers.
730 CCIfType<[v16f32, v8f64, v16i32, v8i64],
731 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3]>>,
733 // Pass masks in mask registers
734 CCIfType<[v16i1, v8i1], CCAssignToReg<[K1]>>,
736 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>,
737 CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64_C>>,
738 CCDelegateTo<CC_X86_32_C>
741 //===----------------------------------------------------------------------===//
742 // X86 Root Argument Calling Conventions
743 //===----------------------------------------------------------------------===//
745 // This is the root argument convention for the X86-32 backend.
746 def CC_X86_32 : CallingConv<[
747 CCIfCC<"CallingConv::X86_FastCall", CCDelegateTo<CC_X86_32_FastCall>>,
748 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<CC_X86_32_VectorCall>>,
749 CCIfCC<"CallingConv::X86_ThisCall", CCDelegateTo<CC_X86_32_ThisCall>>,
750 CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_X86_32_FastCC>>,
751 CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_32_GHC>>,
752 CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_32_HiPE>>,
754 // Otherwise, drop to normal X86-32 CC
755 CCDelegateTo<CC_X86_32_C>
758 // This is the root argument convention for the X86-64 backend.
759 def CC_X86_64 : CallingConv<[
760 CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_64_GHC>>,
761 CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_64_HiPE>>,
762 CCIfCC<"CallingConv::WebKit_JS", CCDelegateTo<CC_X86_64_WebKit_JS>>,
763 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<CC_X86_64_AnyReg>>,
764 CCIfCC<"CallingConv::X86_64_Win64", CCDelegateTo<CC_X86_Win64_C>>,
765 CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo<CC_X86_64_C>>,
766 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<CC_X86_Win64_VectorCall>>,
767 CCIfCC<"CallingConv::HHVM", CCDelegateTo<CC_X86_64_HHVM>>,
768 CCIfCC<"CallingConv::HHVM_C", CCDelegateTo<CC_X86_64_HHVM_C>>,
770 // Mingw64 and native Win64 use Win64 CC
771 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>,
773 // Otherwise, drop to normal X86-64 CC
774 CCDelegateTo<CC_X86_64_C>
777 // This is the argument convention used for the entire X86 backend.
778 def CC_X86 : CallingConv<[
779 CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo<CC_Intel_OCL_BI>>,
780 CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64>>,
781 CCDelegateTo<CC_X86_32>
784 //===----------------------------------------------------------------------===//
785 // Callee-saved Registers.
786 //===----------------------------------------------------------------------===//
788 def CSR_NoRegs : CalleeSavedRegs<(add)>;
790 def CSR_32 : CalleeSavedRegs<(add ESI, EDI, EBX, EBP)>;
791 def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>;
793 def CSR_32EHRet : CalleeSavedRegs<(add EAX, EDX, CSR_32)>;
794 def CSR_64EHRet : CalleeSavedRegs<(add RAX, RDX, CSR_64)>;
796 def CSR_Win64 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15,
797 (sequence "XMM%u", 6, 15))>;
799 // The function used by Darwin to obtain the address of a thread-local variable
800 // uses rdi to pass a single parameter and rax for the return value. All other
801 // GPRs are preserved.
802 def CSR_64_TLS_Darwin : CalleeSavedRegs<(add CSR_64, RCX, RDX, RSI,
805 // All GPRs - except r11
806 def CSR_64_RT_MostRegs : CalleeSavedRegs<(add CSR_64, RAX, RCX, RDX, RSI, RDI,
809 // All registers - except r11
810 def CSR_64_RT_AllRegs : CalleeSavedRegs<(add CSR_64_RT_MostRegs,
811 (sequence "XMM%u", 0, 15))>;
812 def CSR_64_RT_AllRegs_AVX : CalleeSavedRegs<(add CSR_64_RT_MostRegs,
813 (sequence "YMM%u", 0, 15))>;
815 def CSR_64_MostRegs : CalleeSavedRegs<(add RBX, RCX, RDX, RSI, RDI, R8, R9, R10,
816 R11, R12, R13, R14, R15, RBP,
817 (sequence "XMM%u", 0, 15))>;
819 def CSR_64_AllRegs : CalleeSavedRegs<(add CSR_64_MostRegs, RAX, RSP,
820 (sequence "XMM%u", 16, 31))>;
821 def CSR_64_AllRegs_AVX : CalleeSavedRegs<(sub (add CSR_64_MostRegs, RAX, RSP,
822 (sequence "YMM%u", 0, 31)),
823 (sequence "XMM%u", 0, 15))>;
825 // Standard C + YMM6-15
826 def CSR_Win64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12,
828 (sequence "YMM%u", 6, 15))>;
830 def CSR_Win64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI,
832 (sequence "ZMM%u", 6, 21),
834 //Standard C + XMM 8-15
835 def CSR_64_Intel_OCL_BI : CalleeSavedRegs<(add CSR_64,
836 (sequence "XMM%u", 8, 15))>;
838 //Standard C + YMM 8-15
839 def CSR_64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add CSR_64,
840 (sequence "YMM%u", 8, 15))>;
842 def CSR_64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RDI, RSI, R14, R15,
843 (sequence "ZMM%u", 16, 31),
846 // Only R12 is preserved for PHP calls in HHVM.
847 def CSR_64_HHVM : CalleeSavedRegs<(add R12)>;