1 //===- X86CallingConv.td - Calling Conventions X86 32/64 ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This describes the calling conventions for the X86-32 and X86-64
13 //===----------------------------------------------------------------------===//
15 /// CCIfSubtarget - Match if the current subtarget has a feature F.
16 class CCIfSubtarget<string F, CCAction A>
17 : CCIf<!strconcat("State.getTarget().getSubtarget<X86Subtarget>().", F), A>;
19 //===----------------------------------------------------------------------===//
20 // Return Value Calling Conventions
21 //===----------------------------------------------------------------------===//
23 // Return-value conventions common to all X86 CC's.
24 def RetCC_X86Common : CallingConv<[
25 // Scalar values are returned in AX first, then DX.
26 CCIfType<[i8] , CCAssignToReg<[AL]>>,
27 CCIfType<[i16], CCAssignToReg<[AX, DX]>>,
28 CCIfType<[i32], CCAssignToReg<[EAX, EDX]>>,
29 CCIfType<[i64], CCAssignToReg<[RAX, RDX]>>,
31 // Vector types are returned in XMM0 and XMM1, when they fit. XMMM2 and XMM3
32 // can only be used by ABI non-compliant code. If the target doesn't have XMM
33 // registers, it won't have vector types.
34 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
35 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,
37 // MMX vector types are always returned in MM0. If the target doesn't have
38 // MM0, it doesn't support these vector types.
39 CCIfType<[v8i8, v4i16, v2i32, v1i64, v2f32], CCAssignToReg<[MM0]>>,
41 // Long double types are always returned in ST0 (even with SSE).
42 CCIfType<[f80], CCAssignToReg<[ST0, ST1]>>
45 // X86-32 C return-value convention.
46 def RetCC_X86_32_C : CallingConv<[
47 // The X86-32 calling convention returns FP values in ST0, unless marked
48 // with "inreg" (used here to distinguish one kind of reg from another,
49 // weirdly; this is really the sse-regparm calling convention) in which
50 // case they use XMM0, otherwise it is the same as the common X86 calling
52 CCIfInReg<CCIfSubtarget<"hasSSE2()",
53 CCIfType<[f32, f64], CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
54 CCIfType<[f32,f64], CCAssignToReg<[ST0, ST1]>>,
55 CCDelegateTo<RetCC_X86Common>
58 // X86-32 FastCC return-value convention.
59 def RetCC_X86_32_Fast : CallingConv<[
60 // The X86-32 fastcc returns 1, 2, or 3 FP values in XMM0-2 if the target has
61 // SSE2, otherwise it is the the C calling conventions.
62 // This can happen when a float, 2 x float, or 3 x float vector is split by
63 // target lowering, and is returned in 1-3 sse regs.
64 CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
65 CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
66 CCDelegateTo<RetCC_X86Common>
69 // X86-64 C return-value convention.
70 def RetCC_X86_64_C : CallingConv<[
71 // The X86-64 calling convention always returns FP values in XMM0.
72 CCIfType<[f32], CCAssignToReg<[XMM0, XMM1]>>,
73 CCIfType<[f64], CCAssignToReg<[XMM0, XMM1]>>,
75 // MMX vector types are always returned in RAX. This seems to disagree with
76 // ABI documentation but is bug compatible with gcc.
77 CCIfType<[v8i8, v4i16, v2i32, v1i64, v2f32], CCAssignToReg<[RAX]>>,
78 CCDelegateTo<RetCC_X86Common>
81 // X86-Win64 C return-value convention.
82 def RetCC_X86_Win64_C : CallingConv<[
83 // The X86-Win64 calling convention always returns __m64 values in RAX.
84 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToReg<[RAX]>>,
86 // And FP in XMM0 only.
87 CCIfType<[f32], CCAssignToReg<[XMM0]>>,
88 CCIfType<[f64], CCAssignToReg<[XMM0]>>,
90 // Otherwise, everything is the same as 'normal' X86-64 C CC.
91 CCDelegateTo<RetCC_X86_64_C>
95 // This is the root return-value convention for the X86-32 backend.
96 def RetCC_X86_32 : CallingConv<[
97 // If FastCC, use RetCC_X86_32_Fast.
98 CCIfCC<"CallingConv::Fast", CCDelegateTo<RetCC_X86_32_Fast>>,
99 // Otherwise, use RetCC_X86_32_C.
100 CCDelegateTo<RetCC_X86_32_C>
103 // This is the root return-value convention for the X86-64 backend.
104 def RetCC_X86_64 : CallingConv<[
105 // Mingw64 and native Win64 use Win64 CC
106 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<RetCC_X86_Win64_C>>,
108 // Otherwise, drop to normal X86-64 CC
109 CCDelegateTo<RetCC_X86_64_C>
112 // This is the return-value convention used for the entire X86 backend.
113 def RetCC_X86 : CallingConv<[
114 CCIfSubtarget<"is64Bit()", CCDelegateTo<RetCC_X86_64>>,
115 CCDelegateTo<RetCC_X86_32>
118 //===----------------------------------------------------------------------===//
119 // X86-64 Argument Calling Conventions
120 //===----------------------------------------------------------------------===//
122 def CC_X86_64_C : CallingConv<[
123 // Handles byval parameters.
124 CCIfByVal<CCPassByVal<8, 8>>,
126 // Promote i8/i16 arguments to i32.
127 CCIfType<[i8, i16], CCPromoteToType<i32>>,
129 // The 'nest' parameter, if any, is passed in R10.
130 CCIfNest<CCAssignToReg<[R10]>>,
132 // The first 6 integer arguments are passed in integer registers.
133 CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D, R9D]>>,
134 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
136 // The first 8 FP/Vector arguments are passed in XMM registers.
137 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
138 CCIfSubtarget<"hasSSE1()",
139 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>,
141 // The first 8 MMX (except for v1i64) vector arguments are passed in XMM
142 // registers on Darwin.
143 CCIfType<[v8i8, v4i16, v2i32, v2f32],
144 CCIfSubtarget<"isTargetDarwin()",
145 CCIfSubtarget<"hasSSE2()",
146 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>>,
148 // The first 8 v1i64 vector arguments are passed in GPRs on Darwin.
150 CCIfSubtarget<"isTargetDarwin()",
151 CCAssignToReg<[RDI, RSI, RDX, RCX, R8]>>>,
153 // Integer/FP values get stored in stack slots that are 8 bytes in size and
154 // 8-byte aligned if there are no more registers to hold them.
155 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
157 // Long doubles get stack slots whose size and alignment depends on the
159 CCIfType<[f80], CCAssignToStack<0, 0>>,
161 // Vectors get 16-byte stack slots that are 16-byte aligned.
162 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
164 // __m64 vectors get 8-byte stack slots that are 8-byte aligned.
165 CCIfType<[v8i8, v4i16, v2i32, v1i64, v2f32], CCAssignToStack<8, 8>>
168 // Calling convention used on Win64
169 def CC_X86_Win64_C : CallingConv<[
170 // FIXME: Handle byval stuff.
171 // FIXME: Handle varargs.
173 // Promote i8/i16 arguments to i32.
174 CCIfType<[i8, i16], CCPromoteToType<i32>>,
176 // The 'nest' parameter, if any, is passed in R10.
177 CCIfNest<CCAssignToReg<[R10]>>,
179 // The first 4 integer arguments are passed in integer registers.
180 CCIfType<[i32], CCAssignToRegWithShadow<[ECX , EDX , R8D , R9D ],
181 [XMM0, XMM1, XMM2, XMM3]>>,
182 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
183 [XMM0, XMM1, XMM2, XMM3]>>,
185 // The first 4 FP/Vector arguments are passed in XMM registers.
186 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
187 CCAssignToRegWithShadow<[XMM0, XMM1, XMM2, XMM3],
188 [RCX , RDX , R8 , R9 ]>>,
190 // The first 4 MMX vector arguments are passed in GPRs.
191 CCIfType<[v8i8, v4i16, v2i32, v1i64, v2f32],
192 CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
193 [XMM0, XMM1, XMM2, XMM3]>>,
195 // Integer/FP values get stored in stack slots that are 8 bytes in size and
196 // 16-byte aligned if there are no more registers to hold them.
197 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 16>>,
199 // Long doubles get stack slots whose size and alignment depends on the
201 CCIfType<[f80], CCAssignToStack<0, 0>>,
203 // Vectors get 16-byte stack slots that are 16-byte aligned.
204 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
206 // __m64 vectors get 8-byte stack slots that are 16-byte aligned.
207 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 16>>
210 // Tail call convention (fast): One register is reserved for target address,
212 def CC_X86_64_TailCall : CallingConv<[
213 // Handles byval parameters.
214 CCIfByVal<CCPassByVal<8, 8>>,
216 // Promote i8/i16 arguments to i32.
217 CCIfType<[i8, i16], CCPromoteToType<i32>>,
219 // The 'nest' parameter, if any, is passed in R10.
220 CCIfNest<CCAssignToReg<[R10]>>,
222 // The first 6 integer arguments are passed in integer registers.
223 CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D]>>,
224 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8]>>,
226 // The first 8 FP/Vector arguments are passed in XMM registers.
227 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
228 CCIfSubtarget<"hasSSE1()",
229 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>,
231 // The first 8 MMX (except for v1i64) vector arguments are passed in XMM
232 // registers on Darwin.
233 CCIfType<[v8i8, v4i16, v2i32, v2f32],
234 CCIfSubtarget<"isTargetDarwin()",
235 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>,
237 // The first 8 v1i64 vector arguments are passed in GPRs on Darwin.
239 CCIfSubtarget<"isTargetDarwin()",
240 CCAssignToReg<[RDI, RSI, RDX, RCX, R8]>>>,
242 // Integer/FP values get stored in stack slots that are 8 bytes in size and
243 // 8-byte aligned if there are no more registers to hold them.
244 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
246 // Vectors get 16-byte stack slots that are 16-byte aligned.
247 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
249 // __m64 vectors get 8-byte stack slots that are 8-byte aligned.
250 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 8>>
254 //===----------------------------------------------------------------------===//
255 // X86 C Calling Convention
256 //===----------------------------------------------------------------------===//
258 /// CC_X86_32_Common - In all X86-32 calling conventions, extra integers and FP
259 /// values are spilled on the stack, and the first 4 vector values go in XMM
261 def CC_X86_32_Common : CallingConv<[
262 // Handles byval parameters.
263 CCIfByVal<CCPassByVal<4, 4>>,
265 // The first 3 float or double arguments, if marked 'inreg' and if the call
266 // is not a vararg call and if SSE2 is available, are passed in SSE registers.
267 CCIfNotVarArg<CCIfInReg<CCIfType<[f32,f64],
268 CCIfSubtarget<"hasSSE2()",
269 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>>,
271 // The first 3 __m64 (except for v1i64) vector arguments are passed in mmx
272 // registers if the call is not a vararg call.
273 CCIfNotVarArg<CCIfType<[v8i8, v4i16, v2i32, v2f32],
274 CCAssignToReg<[MM0, MM1, MM2]>>>,
276 // Integer/Float values get stored in stack slots that are 4 bytes in
277 // size and 4-byte aligned.
278 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
280 // Doubles get 8-byte slots that are 4-byte aligned.
281 CCIfType<[f64], CCAssignToStack<8, 4>>,
283 // Long doubles get slots whose size depends on the subtarget.
284 CCIfType<[f80], CCAssignToStack<0, 4>>,
286 // The first 4 SSE vector arguments are passed in XMM registers.
287 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
288 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>>,
290 // Other SSE vectors get 16-byte stack slots that are 16-byte aligned.
291 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
293 // __m64 vectors get 8-byte stack slots that are 4-byte aligned. They are
294 // passed in the parameter area.
295 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 4>>]>;
297 def CC_X86_32_C : CallingConv<[
298 // Promote i8/i16 arguments to i32.
299 CCIfType<[i8, i16], CCPromoteToType<i32>>,
301 // The 'nest' parameter, if any, is passed in ECX.
302 CCIfNest<CCAssignToReg<[ECX]>>,
304 // The first 3 integer arguments, if marked 'inreg' and if the call is not
305 // a vararg call, are passed in integer registers.
306 CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>>>,
308 // Otherwise, same as everything else.
309 CCDelegateTo<CC_X86_32_Common>
312 def CC_X86_32_FastCall : CallingConv<[
313 // Promote i8/i16 arguments to i32.
314 CCIfType<[i8, i16], CCPromoteToType<i32>>,
316 // The 'nest' parameter, if any, is passed in EAX.
317 CCIfNest<CCAssignToReg<[EAX]>>,
319 // The first 2 integer arguments are passed in ECX/EDX
320 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>,
322 // Otherwise, same as everything else.
323 CCDelegateTo<CC_X86_32_Common>
326 def CC_X86_32_FastCC : CallingConv<[
327 // Handles byval parameters. Note that we can't rely on the delegation
328 // to CC_X86_32_Common for this because that happens after code that
329 // puts arguments in registers.
330 CCIfByVal<CCPassByVal<4, 4>>,
332 // Promote i8/i16 arguments to i32.
333 CCIfType<[i8, i16], CCPromoteToType<i32>>,
335 // The 'nest' parameter, if any, is passed in EAX.
336 CCIfNest<CCAssignToReg<[EAX]>>,
338 // The first 2 integer arguments are passed in ECX/EDX
339 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>,
341 // The first 3 float or double arguments, if the call is not a vararg
342 // call and if SSE2 is available, are passed in SSE registers.
343 CCIfNotVarArg<CCIfType<[f32,f64],
344 CCIfSubtarget<"hasSSE2()",
345 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
347 // Doubles get 8-byte slots that are 8-byte aligned.
348 CCIfType<[f64], CCAssignToStack<8, 8>>,
350 // Otherwise, same as everything else.
351 CCDelegateTo<CC_X86_32_Common>