1 //===-- X86CallingConv.td - Calling Conventions X86 32/64 --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This describes the calling conventions for the X86-32 and X86-64
13 //===----------------------------------------------------------------------===//
15 /// CCIfSubtarget - Match if the current subtarget has a feature F.
16 class CCIfSubtarget<string F, CCAction A>
17 : CCIf<!strconcat("static_cast<const X86Subtarget&>"
18 "(State.getMachineFunction().getSubtarget()).", F),
21 //===----------------------------------------------------------------------===//
22 // Return Value Calling Conventions
23 //===----------------------------------------------------------------------===//
25 // Return-value conventions common to all X86 CC's.
26 def RetCC_X86Common : CallingConv<[
27 // Scalar values are returned in AX first, then DX. For i8, the ABI
28 // requires the values to be in AL and AH, however this code uses AL and DL
29 // instead. This is because using AH for the second register conflicts with
30 // the way LLVM does multiple return values -- a return of {i16,i8} would end
31 // up in AX and AH, which overlap. Front-ends wishing to conform to the ABI
32 // for functions that return two i8 values are currently expected to pack the
33 // values into an i16 (which uses AX, and thus AL:AH).
35 // For code that doesn't care about the ABI, we allow returning more than two
36 // integer values in registers.
37 CCIfType<[i8] , CCAssignToReg<[AL, DL, CL]>>,
38 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>,
39 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>,
40 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX]>>,
42 // Vector types are returned in XMM0 and XMM1, when they fit. XMM2 and XMM3
43 // can only be used by ABI non-compliant code. If the target doesn't have XMM
44 // registers, it won't have vector types.
45 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
46 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,
48 // 256-bit vectors are returned in YMM0 and XMM1, when they fit. YMM2 and YMM3
49 // can only be used by ABI non-compliant code. This vector type is only
50 // supported while using the AVX target feature.
51 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
52 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>,
54 // 512-bit vectors are returned in ZMM0 and ZMM1, when they fit. ZMM2 and ZMM3
55 // can only be used by ABI non-compliant code. This vector type is only
56 // supported while using the AVX-512 target feature.
57 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
58 CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>,
60 // MMX vector types are always returned in MM0. If the target doesn't have
61 // MM0, it doesn't support these vector types.
62 CCIfType<[x86mmx], CCAssignToReg<[MM0]>>,
64 // Long double types are always returned in FP0 (even with SSE).
65 CCIfType<[f80], CCAssignToReg<[FP0, FP1]>>
68 // X86-32 C return-value convention.
69 def RetCC_X86_32_C : CallingConv<[
70 // The X86-32 calling convention returns FP values in FP0, unless marked
71 // with "inreg" (used here to distinguish one kind of reg from another,
72 // weirdly; this is really the sse-regparm calling convention) in which
73 // case they use XMM0, otherwise it is the same as the common X86 calling
75 CCIfInReg<CCIfSubtarget<"hasSSE2()",
76 CCIfType<[f32, f64], CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
77 CCIfType<[f32,f64], CCAssignToReg<[FP0, FP1]>>,
78 CCDelegateTo<RetCC_X86Common>
81 // X86-32 FastCC return-value convention.
82 def RetCC_X86_32_Fast : CallingConv<[
83 // The X86-32 fastcc returns 1, 2, or 3 FP values in XMM0-2 if the target has
85 // This can happen when a float, 2 x float, or 3 x float vector is split by
86 // target lowering, and is returned in 1-3 sse regs.
87 CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
88 CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
90 // For integers, ECX can be used as an extra return register
91 CCIfType<[i8], CCAssignToReg<[AL, DL, CL]>>,
92 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>,
93 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>,
95 // Otherwise, it is the same as the common X86 calling convention.
96 CCDelegateTo<RetCC_X86Common>
99 // Intel_OCL_BI return-value convention.
100 def RetCC_Intel_OCL_BI : CallingConv<[
101 // Vector types are returned in XMM0,XMM1,XMMM2 and XMM3.
102 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64],
103 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,
105 // 256-bit FP vectors
106 // No more than 4 registers
107 CCIfType<[v8f32, v4f64, v8i32, v4i64],
108 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>,
110 // 512-bit FP vectors
111 CCIfType<[v16f32, v8f64, v16i32, v8i64],
112 CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>,
114 // i32, i64 in the standard way
115 CCDelegateTo<RetCC_X86Common>
118 // X86-32 HiPE return-value convention.
119 def RetCC_X86_32_HiPE : CallingConv<[
120 // Promote all types to i32
121 CCIfType<[i8, i16], CCPromoteToType<i32>>,
123 // Return: HP, P, VAL1, VAL2
124 CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX]>>
127 // X86-64 C return-value convention.
128 def RetCC_X86_64_C : CallingConv<[
129 // The X86-64 calling convention always returns FP values in XMM0.
130 CCIfType<[f32], CCAssignToReg<[XMM0, XMM1]>>,
131 CCIfType<[f64], CCAssignToReg<[XMM0, XMM1]>>,
133 // MMX vector types are always returned in XMM0.
134 CCIfType<[x86mmx], CCAssignToReg<[XMM0, XMM1]>>,
135 CCDelegateTo<RetCC_X86Common>
138 // X86-Win64 C return-value convention.
139 def RetCC_X86_Win64_C : CallingConv<[
140 // The X86-Win64 calling convention always returns __m64 values in RAX.
141 CCIfType<[x86mmx], CCBitConvertToType<i64>>,
143 // Otherwise, everything is the same as 'normal' X86-64 C CC.
144 CCDelegateTo<RetCC_X86_64_C>
147 // X86-64 HiPE return-value convention.
148 def RetCC_X86_64_HiPE : CallingConv<[
149 // Promote all types to i64
150 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
152 // Return: HP, P, VAL1, VAL2
153 CCIfType<[i64], CCAssignToReg<[R15, RBP, RAX, RDX]>>
156 // X86-64 WebKit_JS return-value convention.
157 def RetCC_X86_64_WebKit_JS : CallingConv<[
158 // Promote all types to i64
159 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
162 CCIfType<[i64], CCAssignToReg<[RAX]>>
165 // X86-64 AnyReg return-value convention. No explicit register is specified for
166 // the return-value. The register allocator is allowed and expected to choose
167 // any free register.
169 // This calling convention is currently only supported by the stackmap and
170 // patchpoint intrinsics. All other uses will result in an assert on Debug
171 // builds. On Release builds we fallback to the X86 C calling convention.
172 def RetCC_X86_64_AnyReg : CallingConv<[
173 CCCustom<"CC_X86_AnyReg_Error">
176 // This is the root return-value convention for the X86-32 backend.
177 def RetCC_X86_32 : CallingConv<[
178 // If FastCC, use RetCC_X86_32_Fast.
179 CCIfCC<"CallingConv::Fast", CCDelegateTo<RetCC_X86_32_Fast>>,
180 // If HiPE, use RetCC_X86_32_HiPE.
181 CCIfCC<"CallingConv::HiPE", CCDelegateTo<RetCC_X86_32_HiPE>>,
183 // Otherwise, use RetCC_X86_32_C.
184 CCDelegateTo<RetCC_X86_32_C>
187 // This is the root return-value convention for the X86-64 backend.
188 def RetCC_X86_64 : CallingConv<[
189 // HiPE uses RetCC_X86_64_HiPE
190 CCIfCC<"CallingConv::HiPE", CCDelegateTo<RetCC_X86_64_HiPE>>,
192 // Handle JavaScript calls.
193 CCIfCC<"CallingConv::WebKit_JS", CCDelegateTo<RetCC_X86_64_WebKit_JS>>,
194 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<RetCC_X86_64_AnyReg>>,
196 // Handle explicit CC selection
197 CCIfCC<"CallingConv::X86_64_Win64", CCDelegateTo<RetCC_X86_Win64_C>>,
198 CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo<RetCC_X86_64_C>>,
200 // Mingw64 and native Win64 use Win64 CC
201 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<RetCC_X86_Win64_C>>,
203 // Otherwise, drop to normal X86-64 CC
204 CCDelegateTo<RetCC_X86_64_C>
207 // This is the return-value convention used for the entire X86 backend.
208 def RetCC_X86 : CallingConv<[
210 // Check if this is the Intel OpenCL built-ins calling convention
211 CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo<RetCC_Intel_OCL_BI>>,
213 CCIfSubtarget<"is64Bit()", CCDelegateTo<RetCC_X86_64>>,
214 CCDelegateTo<RetCC_X86_32>
217 //===----------------------------------------------------------------------===//
218 // X86-64 Argument Calling Conventions
219 //===----------------------------------------------------------------------===//
221 def CC_X86_64_C : CallingConv<[
222 // Handles byval parameters.
223 CCIfByVal<CCPassByVal<8, 8>>,
225 // Promote i8/i16 arguments to i32.
226 CCIfType<[i8, i16], CCPromoteToType<i32>>,
228 // The 'nest' parameter, if any, is passed in R10.
229 CCIfNest<CCAssignToReg<[R10]>>,
231 // The first 6 integer arguments are passed in integer registers.
232 CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D, R9D]>>,
233 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
235 // The first 8 MMX vector arguments are passed in XMM registers on Darwin.
237 CCIfSubtarget<"isTargetDarwin()",
238 CCIfSubtarget<"hasSSE2()",
239 CCPromoteToType<v2i64>>>>,
241 // The first 8 FP/Vector arguments are passed in XMM registers.
242 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
243 CCIfSubtarget<"hasSSE1()",
244 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>,
246 // The first 8 256-bit vector arguments are passed in YMM registers, unless
247 // this is a vararg function.
248 // FIXME: This isn't precisely correct; the x86-64 ABI document says that
249 // fixed arguments to vararg functions are supposed to be passed in
250 // registers. Actually modeling that would be a lot of work, though.
251 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
252 CCIfSubtarget<"hasFp256()",
253 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3,
254 YMM4, YMM5, YMM6, YMM7]>>>>,
256 // The first 8 512-bit vector arguments are passed in ZMM registers.
257 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
258 CCIfSubtarget<"hasAVX512()",
259 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7]>>>>,
261 // Integer/FP values get stored in stack slots that are 8 bytes in size and
262 // 8-byte aligned if there are no more registers to hold them.
263 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
265 // Long doubles get stack slots whose size and alignment depends on the
267 CCIfType<[f80], CCAssignToStack<0, 0>>,
269 // Vectors get 16-byte stack slots that are 16-byte aligned.
270 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
272 // 256-bit vectors get 32-byte stack slots that are 32-byte aligned.
273 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
274 CCAssignToStack<32, 32>>,
276 // 512-bit vectors get 64-byte stack slots that are 64-byte aligned.
277 CCIfType<[v16i32, v8i64, v16f32, v8f64],
278 CCAssignToStack<64, 64>>
281 // Calling convention used on Win64
282 def CC_X86_Win64_C : CallingConv<[
283 // FIXME: Handle byval stuff.
284 // FIXME: Handle varargs.
286 // Promote i8/i16 arguments to i32.
287 CCIfType<[i8, i16], CCPromoteToType<i32>>,
289 // The 'nest' parameter, if any, is passed in R10.
290 CCIfNest<CCAssignToReg<[R10]>>,
292 // 128 bit vectors are passed by pointer
293 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCPassIndirect<i64>>,
296 // 256 bit vectors are passed by pointer
297 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>,
299 // 512 bit vectors are passed by pointer
300 CCIfType<[v16i32, v16f32, v8f64, v8i64], CCPassIndirect<i64>>,
302 // The first 4 MMX vector arguments are passed in GPRs.
303 CCIfType<[x86mmx], CCBitConvertToType<i64>>,
305 // The first 4 integer arguments are passed in integer registers.
306 CCIfType<[i32], CCAssignToRegWithShadow<[ECX , EDX , R8D , R9D ],
307 [XMM0, XMM1, XMM2, XMM3]>>,
309 // Do not pass the sret argument in RCX, the Win64 thiscall calling
310 // convention requires "this" to be passed in RCX.
311 CCIfCC<"CallingConv::X86_ThisCall",
312 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[RDX , R8 , R9 ],
313 [XMM1, XMM2, XMM3]>>>>,
315 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
316 [XMM0, XMM1, XMM2, XMM3]>>,
318 // The first 4 FP/Vector arguments are passed in XMM registers.
319 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
320 CCAssignToRegWithShadow<[XMM0, XMM1, XMM2, XMM3],
321 [RCX , RDX , R8 , R9 ]>>,
323 // Integer/FP values get stored in stack slots that are 8 bytes in size and
324 // 8-byte aligned if there are no more registers to hold them.
325 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
327 // Long doubles get stack slots whose size and alignment depends on the
329 CCIfType<[f80], CCAssignToStack<0, 0>>
332 def CC_X86_64_GHC : CallingConv<[
333 // Promote i8/i16/i32 arguments to i64.
334 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
336 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim
338 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
340 // Pass in STG registers: F1, F2, F3, F4, D1, D2
341 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
342 CCIfSubtarget<"hasSSE1()",
343 CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>
346 def CC_X86_64_HiPE : CallingConv<[
347 // Promote i8/i16/i32 arguments to i64.
348 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
350 // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2, ARG3
351 CCIfType<[i64], CCAssignToReg<[R15, RBP, RSI, RDX, RCX, R8]>>,
353 // Integer/FP values get stored in stack slots that are 8 bytes in size and
354 // 8-byte aligned if there are no more registers to hold them.
355 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>
358 def CC_X86_64_WebKit_JS : CallingConv<[
359 // Promote i8/i16 arguments to i32.
360 CCIfType<[i8, i16], CCPromoteToType<i32>>,
362 // Only the first integer argument is passed in register.
363 CCIfType<[i32], CCAssignToReg<[EAX]>>,
364 CCIfType<[i64], CCAssignToReg<[RAX]>>,
366 // The remaining integer arguments are passed on the stack. 32bit integer and
367 // floating-point arguments are aligned to 4 byte and stored in 4 byte slots.
368 // 64bit integer and floating-point arguments are aligned to 8 byte and stored
369 // in 8 byte stack slots.
370 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
371 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
374 // No explicit register is specified for the AnyReg calling convention. The
375 // register allocator may assign the arguments to any free register.
377 // This calling convention is currently only supported by the stackmap and
378 // patchpoint intrinsics. All other uses will result in an assert on Debug
379 // builds. On Release builds we fallback to the X86 C calling convention.
380 def CC_X86_64_AnyReg : CallingConv<[
381 CCCustom<"CC_X86_AnyReg_Error">
384 //===----------------------------------------------------------------------===//
385 // X86 C Calling Convention
386 //===----------------------------------------------------------------------===//
388 /// CC_X86_32_Common - In all X86-32 calling conventions, extra integers and FP
389 /// values are spilled on the stack, and the first 4 vector values go in XMM
391 def CC_X86_32_Common : CallingConv<[
392 // Handles byval parameters.
393 CCIfByVal<CCPassByVal<4, 4>>,
395 // The first 3 float or double arguments, if marked 'inreg' and if the call
396 // is not a vararg call and if SSE2 is available, are passed in SSE registers.
397 CCIfNotVarArg<CCIfInReg<CCIfType<[f32,f64],
398 CCIfSubtarget<"hasSSE2()",
399 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>>,
401 // The first 3 __m64 vector arguments are passed in mmx registers if the
402 // call is not a vararg call.
403 CCIfNotVarArg<CCIfType<[x86mmx],
404 CCAssignToReg<[MM0, MM1, MM2]>>>,
406 // Integer/Float values get stored in stack slots that are 4 bytes in
407 // size and 4-byte aligned.
408 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
410 // Doubles get 8-byte slots that are 4-byte aligned.
411 CCIfType<[f64], CCAssignToStack<8, 4>>,
413 // Long doubles get slots whose size depends on the subtarget.
414 CCIfType<[f80], CCAssignToStack<0, 4>>,
416 // The first 4 SSE vector arguments are passed in XMM registers.
417 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
418 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>>,
420 // The first 4 AVX 256-bit vector arguments are passed in YMM registers.
421 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
422 CCIfSubtarget<"hasFp256()",
423 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>>>,
425 // Other SSE vectors get 16-byte stack slots that are 16-byte aligned.
426 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
428 // 256-bit AVX vectors get 32-byte stack slots that are 32-byte aligned.
429 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
430 CCAssignToStack<32, 32>>,
432 // __m64 vectors get 8-byte stack slots that are 4-byte aligned. They are
433 // passed in the parameter area.
434 CCIfType<[x86mmx], CCAssignToStack<8, 4>>]>;
436 def CC_X86_32_C : CallingConv<[
437 // Promote i8/i16 arguments to i32.
438 CCIfType<[i8, i16], CCPromoteToType<i32>>,
440 // The 'nest' parameter, if any, is passed in ECX.
441 CCIfNest<CCAssignToReg<[ECX]>>,
443 // The first 3 integer arguments, if marked 'inreg' and if the call is not
444 // a vararg call, are passed in integer registers.
445 CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>>>,
447 // Otherwise, same as everything else.
448 CCDelegateTo<CC_X86_32_Common>
451 def CC_X86_32_FastCall : CallingConv<[
452 // Promote i8/i16 arguments to i32.
453 CCIfType<[i8, i16], CCPromoteToType<i32>>,
455 // The 'nest' parameter, if any, is passed in EAX.
456 CCIfNest<CCAssignToReg<[EAX]>>,
458 // The first 2 integer arguments are passed in ECX/EDX
459 CCIfInReg<CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>>,
461 // Otherwise, same as everything else.
462 CCDelegateTo<CC_X86_32_Common>
465 def CC_X86_32_ThisCall_Common : CallingConv<[
466 // The first integer argument is passed in ECX
467 CCIfType<[i32], CCAssignToReg<[ECX]>>,
469 // Otherwise, same as everything else.
470 CCDelegateTo<CC_X86_32_Common>
473 def CC_X86_32_ThisCall_Mingw : CallingConv<[
474 // Promote i8/i16 arguments to i32.
475 CCIfType<[i8, i16], CCPromoteToType<i32>>,
477 CCDelegateTo<CC_X86_32_ThisCall_Common>
480 def CC_X86_32_ThisCall_Win : CallingConv<[
481 // Promote i8/i16 arguments to i32.
482 CCIfType<[i8, i16], CCPromoteToType<i32>>,
484 // Pass sret arguments indirectly through stack.
485 CCIfSRet<CCAssignToStack<4, 4>>,
487 CCDelegateTo<CC_X86_32_ThisCall_Common>
490 def CC_X86_32_ThisCall : CallingConv<[
491 CCIfSubtarget<"isTargetCygMing()", CCDelegateTo<CC_X86_32_ThisCall_Mingw>>,
492 CCDelegateTo<CC_X86_32_ThisCall_Win>
495 def CC_X86_32_FastCC : CallingConv<[
496 // Handles byval parameters. Note that we can't rely on the delegation
497 // to CC_X86_32_Common for this because that happens after code that
498 // puts arguments in registers.
499 CCIfByVal<CCPassByVal<4, 4>>,
501 // Promote i8/i16 arguments to i32.
502 CCIfType<[i8, i16], CCPromoteToType<i32>>,
504 // The 'nest' parameter, if any, is passed in EAX.
505 CCIfNest<CCAssignToReg<[EAX]>>,
507 // The first 2 integer arguments are passed in ECX/EDX
508 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>,
510 // The first 3 float or double arguments, if the call is not a vararg
511 // call and if SSE2 is available, are passed in SSE registers.
512 CCIfNotVarArg<CCIfType<[f32,f64],
513 CCIfSubtarget<"hasSSE2()",
514 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
516 // Doubles get 8-byte slots that are 8-byte aligned.
517 CCIfType<[f64], CCAssignToStack<8, 8>>,
519 // Otherwise, same as everything else.
520 CCDelegateTo<CC_X86_32_Common>
523 def CC_X86_32_GHC : CallingConv<[
524 // Promote i8/i16 arguments to i32.
525 CCIfType<[i8, i16], CCPromoteToType<i32>>,
527 // Pass in STG registers: Base, Sp, Hp, R1
528 CCIfType<[i32], CCAssignToReg<[EBX, EBP, EDI, ESI]>>
531 def CC_X86_32_HiPE : CallingConv<[
532 // Promote i8/i16 arguments to i32.
533 CCIfType<[i8, i16], CCPromoteToType<i32>>,
535 // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2
536 CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX, ECX]>>,
538 // Integer/Float values get stored in stack slots that are 4 bytes in
539 // size and 4-byte aligned.
540 CCIfType<[i32, f32], CCAssignToStack<4, 4>>
543 // X86-64 Intel OpenCL built-ins calling convention.
544 def CC_Intel_OCL_BI : CallingConv<[
546 CCIfType<[i32], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[ECX, EDX, R8D, R9D]>>>,
547 CCIfType<[i64], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[RCX, RDX, R8, R9 ]>>>,
549 CCIfType<[i32], CCIfSubtarget<"is64Bit()", CCAssignToReg<[EDI, ESI, EDX, ECX]>>>,
550 CCIfType<[i64], CCIfSubtarget<"is64Bit()", CCAssignToReg<[RDI, RSI, RDX, RCX]>>>,
552 CCIfType<[i32], CCAssignToStack<4, 4>>,
554 // The SSE vector arguments are passed in XMM registers.
555 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64],
556 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>,
558 // The 256-bit vector arguments are passed in YMM registers.
559 CCIfType<[v8f32, v4f64, v8i32, v4i64],
560 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>,
562 // The 512-bit vector arguments are passed in ZMM registers.
563 CCIfType<[v16f32, v8f64, v16i32, v8i64],
564 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3]>>,
566 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>,
567 CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64_C>>,
568 CCDelegateTo<CC_X86_32_C>
571 //===----------------------------------------------------------------------===//
572 // X86 Root Argument Calling Conventions
573 //===----------------------------------------------------------------------===//
575 // This is the root argument convention for the X86-32 backend.
576 def CC_X86_32 : CallingConv<[
577 CCIfCC<"CallingConv::X86_FastCall", CCDelegateTo<CC_X86_32_FastCall>>,
578 CCIfCC<"CallingConv::X86_ThisCall", CCDelegateTo<CC_X86_32_ThisCall>>,
579 CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_X86_32_FastCC>>,
580 CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_32_GHC>>,
581 CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_32_HiPE>>,
583 // Otherwise, drop to normal X86-32 CC
584 CCDelegateTo<CC_X86_32_C>
587 // This is the root argument convention for the X86-64 backend.
588 def CC_X86_64 : CallingConv<[
589 CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_64_GHC>>,
590 CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_64_HiPE>>,
591 CCIfCC<"CallingConv::WebKit_JS", CCDelegateTo<CC_X86_64_WebKit_JS>>,
592 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<CC_X86_64_AnyReg>>,
593 CCIfCC<"CallingConv::X86_64_Win64", CCDelegateTo<CC_X86_Win64_C>>,
594 CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo<CC_X86_64_C>>,
596 // Mingw64 and native Win64 use Win64 CC
597 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>,
599 // Otherwise, drop to normal X86-64 CC
600 CCDelegateTo<CC_X86_64_C>
603 // This is the argument convention used for the entire X86 backend.
604 def CC_X86 : CallingConv<[
605 CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo<CC_Intel_OCL_BI>>,
606 CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64>>,
607 CCDelegateTo<CC_X86_32>
610 //===----------------------------------------------------------------------===//
611 // Callee-saved Registers.
612 //===----------------------------------------------------------------------===//
614 def CSR_NoRegs : CalleeSavedRegs<(add)>;
616 def CSR_32 : CalleeSavedRegs<(add ESI, EDI, EBX, EBP)>;
617 def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>;
619 def CSR_32EHRet : CalleeSavedRegs<(add EAX, EDX, CSR_32)>;
620 def CSR_64EHRet : CalleeSavedRegs<(add RAX, RDX, CSR_64)>;
622 def CSR_Win64 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15,
623 (sequence "XMM%u", 6, 15))>;
625 // All GPRs - except r11
626 def CSR_64_RT_MostRegs : CalleeSavedRegs<(add CSR_64, RAX, RCX, RDX, RSI, RDI,
629 // All registers - except r11
630 def CSR_64_RT_AllRegs : CalleeSavedRegs<(add CSR_64_RT_MostRegs,
631 (sequence "XMM%u", 0, 15))>;
632 def CSR_64_RT_AllRegs_AVX : CalleeSavedRegs<(add CSR_64_RT_MostRegs,
633 (sequence "YMM%u", 0, 15))>;
635 def CSR_64_MostRegs : CalleeSavedRegs<(add RBX, RCX, RDX, RSI, RDI, R8, R9, R10,
636 R11, R12, R13, R14, R15, RBP,
637 (sequence "XMM%u", 0, 15))>;
639 def CSR_64_AllRegs : CalleeSavedRegs<(add CSR_64_MostRegs, RAX, RSP,
640 (sequence "XMM%u", 16, 31))>;
641 def CSR_64_AllRegs_AVX : CalleeSavedRegs<(sub (add CSR_64_MostRegs, RAX, RSP,
642 (sequence "YMM%u", 0, 31)),
643 (sequence "XMM%u", 0, 15))>;
645 // Standard C + YMM6-15
646 def CSR_Win64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12,
648 (sequence "YMM%u", 6, 15))>;
650 def CSR_Win64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI,
652 (sequence "ZMM%u", 6, 21),
654 //Standard C + XMM 8-15
655 def CSR_64_Intel_OCL_BI : CalleeSavedRegs<(add CSR_64,
656 (sequence "XMM%u", 8, 15))>;
658 //Standard C + YMM 8-15
659 def CSR_64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add CSR_64,
660 (sequence "YMM%u", 8, 15))>;
662 def CSR_64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RDI, RSI, R14, R15,
663 (sequence "ZMM%u", 16, 31),