1 //===-- X86CallingConv.td - Calling Conventions X86 32/64 --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This describes the calling conventions for the X86-32 and X86-64
13 //===----------------------------------------------------------------------===//
15 /// CCIfSubtarget - Match if the current subtarget has a feature F.
16 class CCIfSubtarget<string F, CCAction A>
17 : CCIf<!strconcat("static_cast<const X86Subtarget&>"
18 "(State.getMachineFunction().getSubtarget()).", F),
21 //===----------------------------------------------------------------------===//
22 // Return Value Calling Conventions
23 //===----------------------------------------------------------------------===//
25 // Return-value conventions common to all X86 CC's.
26 def RetCC_X86Common : CallingConv<[
27 // Scalar values are returned in AX first, then DX. For i8, the ABI
28 // requires the values to be in AL and AH, however this code uses AL and DL
29 // instead. This is because using AH for the second register conflicts with
30 // the way LLVM does multiple return values -- a return of {i16,i8} would end
31 // up in AX and AH, which overlap. Front-ends wishing to conform to the ABI
32 // for functions that return two i8 values are currently expected to pack the
33 // values into an i16 (which uses AX, and thus AL:AH).
35 // For code that doesn't care about the ABI, we allow returning more than two
36 // integer values in registers.
37 CCIfType<[i1], CCPromoteToType<i8>>,
38 CCIfType<[i8] , CCAssignToReg<[AL, DL, CL]>>,
39 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>,
40 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>,
41 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX]>>,
43 // Boolean vectors of AVX-512 are returned in SIMD registers.
44 // The call from AVX to AVX-512 function should work,
45 // since the boolean types in AVX/AVX2 are promoted by default.
46 CCIfType<[v2i1], CCPromoteToType<v2i64>>,
47 CCIfType<[v4i1], CCPromoteToType<v4i32>>,
48 CCIfType<[v8i1], CCPromoteToType<v8i16>>,
49 CCIfType<[v16i1], CCPromoteToType<v16i8>>,
50 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
51 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
53 // Vector types are returned in XMM0 and XMM1, when they fit. XMM2 and XMM3
54 // can only be used by ABI non-compliant code. If the target doesn't have XMM
55 // registers, it won't have vector types.
56 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
57 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,
59 // 256-bit vectors are returned in YMM0 and XMM1, when they fit. YMM2 and YMM3
60 // can only be used by ABI non-compliant code. This vector type is only
61 // supported while using the AVX target feature.
62 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
63 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>,
65 // 512-bit vectors are returned in ZMM0 and ZMM1, when they fit. ZMM2 and ZMM3
66 // can only be used by ABI non-compliant code. This vector type is only
67 // supported while using the AVX-512 target feature.
68 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
69 CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>,
71 // MMX vector types are always returned in MM0. If the target doesn't have
72 // MM0, it doesn't support these vector types.
73 CCIfType<[x86mmx], CCAssignToReg<[MM0]>>,
75 // Long double types are always returned in FP0 (even with SSE).
76 CCIfType<[f80], CCAssignToReg<[FP0, FP1]>>
79 // X86-32 C return-value convention.
80 def RetCC_X86_32_C : CallingConv<[
81 // The X86-32 calling convention returns FP values in FP0, unless marked
82 // with "inreg" (used here to distinguish one kind of reg from another,
83 // weirdly; this is really the sse-regparm calling convention) in which
84 // case they use XMM0, otherwise it is the same as the common X86 calling
86 CCIfInReg<CCIfSubtarget<"hasSSE2()",
87 CCIfType<[f32, f64], CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
88 CCIfType<[f32,f64], CCAssignToReg<[FP0, FP1]>>,
89 CCDelegateTo<RetCC_X86Common>
92 // X86-32 FastCC return-value convention.
93 def RetCC_X86_32_Fast : CallingConv<[
94 // The X86-32 fastcc returns 1, 2, or 3 FP values in XMM0-2 if the target has
96 // This can happen when a float, 2 x float, or 3 x float vector is split by
97 // target lowering, and is returned in 1-3 sse regs.
98 CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
99 CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
101 // For integers, ECX can be used as an extra return register
102 CCIfType<[i8], CCAssignToReg<[AL, DL, CL]>>,
103 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>,
104 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>,
106 // Otherwise, it is the same as the common X86 calling convention.
107 CCDelegateTo<RetCC_X86Common>
110 // Intel_OCL_BI return-value convention.
111 def RetCC_Intel_OCL_BI : CallingConv<[
112 // Vector types are returned in XMM0,XMM1,XMMM2 and XMM3.
113 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64],
114 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,
116 // 256-bit FP vectors
117 // No more than 4 registers
118 CCIfType<[v8f32, v4f64, v8i32, v4i64],
119 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>,
121 // 512-bit FP vectors
122 CCIfType<[v16f32, v8f64, v16i32, v8i64],
123 CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>,
125 // i32, i64 in the standard way
126 CCDelegateTo<RetCC_X86Common>
129 // X86-32 HiPE return-value convention.
130 def RetCC_X86_32_HiPE : CallingConv<[
131 // Promote all types to i32
132 CCIfType<[i8, i16], CCPromoteToType<i32>>,
134 // Return: HP, P, VAL1, VAL2
135 CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX]>>
138 // X86-32 HiPE return-value convention.
139 def RetCC_X86_32_VectorCall : CallingConv<[
140 // Vector types are returned in XMM0,XMM1,XMMM2 and XMM3.
141 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
142 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,
144 // 256-bit FP vectors
145 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
146 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>,
148 // 512-bit FP vectors
149 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
150 CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>,
152 // Return integers in the standard way.
153 CCDelegateTo<RetCC_X86Common>
156 // X86-64 C return-value convention.
157 def RetCC_X86_64_C : CallingConv<[
158 // The X86-64 calling convention always returns FP values in XMM0.
159 CCIfType<[f32], CCAssignToReg<[XMM0, XMM1]>>,
160 CCIfType<[f64], CCAssignToReg<[XMM0, XMM1]>>,
162 // MMX vector types are always returned in XMM0.
163 CCIfType<[x86mmx], CCAssignToReg<[XMM0, XMM1]>>,
164 CCDelegateTo<RetCC_X86Common>
167 // X86-Win64 C return-value convention.
168 def RetCC_X86_Win64_C : CallingConv<[
169 // The X86-Win64 calling convention always returns __m64 values in RAX.
170 CCIfType<[x86mmx], CCBitConvertToType<i64>>,
172 // Otherwise, everything is the same as 'normal' X86-64 C CC.
173 CCDelegateTo<RetCC_X86_64_C>
176 // X86-64 HiPE return-value convention.
177 def RetCC_X86_64_HiPE : CallingConv<[
178 // Promote all types to i64
179 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
181 // Return: HP, P, VAL1, VAL2
182 CCIfType<[i64], CCAssignToReg<[R15, RBP, RAX, RDX]>>
185 // X86-64 WebKit_JS return-value convention.
186 def RetCC_X86_64_WebKit_JS : CallingConv<[
187 // Promote all types to i64
188 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
191 CCIfType<[i64], CCAssignToReg<[RAX]>>
194 // X86-64 AnyReg return-value convention. No explicit register is specified for
195 // the return-value. The register allocator is allowed and expected to choose
196 // any free register.
198 // This calling convention is currently only supported by the stackmap and
199 // patchpoint intrinsics. All other uses will result in an assert on Debug
200 // builds. On Release builds we fallback to the X86 C calling convention.
201 def RetCC_X86_64_AnyReg : CallingConv<[
202 CCCustom<"CC_X86_AnyReg_Error">
205 // This is the root return-value convention for the X86-32 backend.
206 def RetCC_X86_32 : CallingConv<[
207 // If FastCC, use RetCC_X86_32_Fast.
208 CCIfCC<"CallingConv::Fast", CCDelegateTo<RetCC_X86_32_Fast>>,
209 // If HiPE, use RetCC_X86_32_HiPE.
210 CCIfCC<"CallingConv::HiPE", CCDelegateTo<RetCC_X86_32_HiPE>>,
211 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<RetCC_X86_32_VectorCall>>,
213 // Otherwise, use RetCC_X86_32_C.
214 CCDelegateTo<RetCC_X86_32_C>
217 // This is the root return-value convention for the X86-64 backend.
218 def RetCC_X86_64 : CallingConv<[
219 // HiPE uses RetCC_X86_64_HiPE
220 CCIfCC<"CallingConv::HiPE", CCDelegateTo<RetCC_X86_64_HiPE>>,
222 // Handle JavaScript calls.
223 CCIfCC<"CallingConv::WebKit_JS", CCDelegateTo<RetCC_X86_64_WebKit_JS>>,
224 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<RetCC_X86_64_AnyReg>>,
226 // Handle explicit CC selection
227 CCIfCC<"CallingConv::X86_64_Win64", CCDelegateTo<RetCC_X86_Win64_C>>,
228 CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo<RetCC_X86_64_C>>,
230 // Mingw64 and native Win64 use Win64 CC
231 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<RetCC_X86_Win64_C>>,
233 // Otherwise, drop to normal X86-64 CC
234 CCDelegateTo<RetCC_X86_64_C>
237 // This is the return-value convention used for the entire X86 backend.
238 def RetCC_X86 : CallingConv<[
240 // Check if this is the Intel OpenCL built-ins calling convention
241 CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo<RetCC_Intel_OCL_BI>>,
243 CCIfSubtarget<"is64Bit()", CCDelegateTo<RetCC_X86_64>>,
244 CCDelegateTo<RetCC_X86_32>
247 //===----------------------------------------------------------------------===//
248 // X86-64 Argument Calling Conventions
249 //===----------------------------------------------------------------------===//
251 def CC_X86_64_C : CallingConv<[
252 // Handles byval parameters.
253 CCIfByVal<CCPassByVal<8, 8>>,
255 // Promote i1/i8/i16 arguments to i32.
256 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
258 // The 'nest' parameter, if any, is passed in R10.
259 CCIfNest<CCIfSubtarget<"isTarget64BitILP32()", CCAssignToReg<[R10D]>>>,
260 CCIfNest<CCAssignToReg<[R10]>>,
262 // The first 6 integer arguments are passed in integer registers.
263 CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D, R9D]>>,
264 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
266 // The first 8 MMX vector arguments are passed in XMM registers on Darwin.
268 CCIfSubtarget<"isTargetDarwin()",
269 CCIfSubtarget<"hasSSE2()",
270 CCPromoteToType<v2i64>>>>,
272 // Boolean vectors of AVX-512 are passed in SIMD registers.
273 // The call from AVX to AVX-512 function should work,
274 // since the boolean types in AVX/AVX2 are promoted by default.
275 CCIfType<[v2i1], CCPromoteToType<v2i64>>,
276 CCIfType<[v4i1], CCPromoteToType<v4i32>>,
277 CCIfType<[v8i1], CCPromoteToType<v8i16>>,
278 CCIfType<[v16i1], CCPromoteToType<v16i8>>,
279 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
280 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
282 // The first 8 FP/Vector arguments are passed in XMM registers.
283 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
284 CCIfSubtarget<"hasSSE1()",
285 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>,
287 // The first 8 256-bit vector arguments are passed in YMM registers, unless
288 // this is a vararg function.
289 // FIXME: This isn't precisely correct; the x86-64 ABI document says that
290 // fixed arguments to vararg functions are supposed to be passed in
291 // registers. Actually modeling that would be a lot of work, though.
292 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
293 CCIfSubtarget<"hasFp256()",
294 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3,
295 YMM4, YMM5, YMM6, YMM7]>>>>,
297 // The first 8 512-bit vector arguments are passed in ZMM registers.
298 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
299 CCIfSubtarget<"hasAVX512()",
300 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7]>>>>,
302 // Integer/FP values get stored in stack slots that are 8 bytes in size and
303 // 8-byte aligned if there are no more registers to hold them.
304 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
306 // Long doubles get stack slots whose size and alignment depends on the
308 CCIfType<[f80], CCAssignToStack<0, 0>>,
310 // Vectors get 16-byte stack slots that are 16-byte aligned.
311 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
313 // 256-bit vectors get 32-byte stack slots that are 32-byte aligned.
314 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
315 CCAssignToStack<32, 32>>,
317 // 512-bit vectors get 64-byte stack slots that are 64-byte aligned.
318 CCIfType<[v16i32, v8i64, v16f32, v8f64],
319 CCAssignToStack<64, 64>>
322 // Calling convention used on Win64
323 def CC_X86_Win64_C : CallingConv<[
324 // FIXME: Handle byval stuff.
325 // FIXME: Handle varargs.
327 // Promote i1/i8/i16 arguments to i32.
328 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
330 // The 'nest' parameter, if any, is passed in R10.
331 CCIfNest<CCAssignToReg<[R10]>>,
333 // 128 bit vectors are passed by pointer
334 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCPassIndirect<i64>>,
337 // 256 bit vectors are passed by pointer
338 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>,
340 // 512 bit vectors are passed by pointer
341 CCIfType<[v16i32, v16f32, v8f64, v8i64], CCPassIndirect<i64>>,
343 // The first 4 MMX vector arguments are passed in GPRs.
344 CCIfType<[x86mmx], CCBitConvertToType<i64>>,
346 // The first 4 integer arguments are passed in integer registers.
347 CCIfType<[i32], CCAssignToRegWithShadow<[ECX , EDX , R8D , R9D ],
348 [XMM0, XMM1, XMM2, XMM3]>>,
350 // Do not pass the sret argument in RCX, the Win64 thiscall calling
351 // convention requires "this" to be passed in RCX.
352 CCIfCC<"CallingConv::X86_ThisCall",
353 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[RDX , R8 , R9 ],
354 [XMM1, XMM2, XMM3]>>>>,
356 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
357 [XMM0, XMM1, XMM2, XMM3]>>,
359 // The first 4 FP/Vector arguments are passed in XMM registers.
360 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
361 CCAssignToRegWithShadow<[XMM0, XMM1, XMM2, XMM3],
362 [RCX , RDX , R8 , R9 ]>>,
364 // Integer/FP values get stored in stack slots that are 8 bytes in size and
365 // 8-byte aligned if there are no more registers to hold them.
366 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
368 // Long doubles get stack slots whose size and alignment depends on the
370 CCIfType<[f80], CCAssignToStack<0, 0>>
373 def CC_X86_Win64_VectorCall : CallingConv<[
374 // The first 6 floating point and vector types of 128 bits or less use
376 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
377 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5]>>,
379 // 256-bit vectors use YMM registers.
380 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
381 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3, YMM4, YMM5]>>,
383 // 512-bit vectors use ZMM registers.
384 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
385 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5]>>,
387 // Delegate to fastcall to handle integer types.
388 CCDelegateTo<CC_X86_Win64_C>
392 def CC_X86_64_GHC : CallingConv<[
393 // Promote i8/i16/i32 arguments to i64.
394 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
396 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim
398 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
400 // Pass in STG registers: F1, F2, F3, F4, D1, D2
401 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
402 CCIfSubtarget<"hasSSE1()",
403 CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>
406 def CC_X86_64_HiPE : CallingConv<[
407 // Promote i8/i16/i32 arguments to i64.
408 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
410 // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2, ARG3
411 CCIfType<[i64], CCAssignToReg<[R15, RBP, RSI, RDX, RCX, R8]>>,
413 // Integer/FP values get stored in stack slots that are 8 bytes in size and
414 // 8-byte aligned if there are no more registers to hold them.
415 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>
418 def CC_X86_64_WebKit_JS : CallingConv<[
419 // Promote i8/i16 arguments to i32.
420 CCIfType<[i8, i16], CCPromoteToType<i32>>,
422 // Only the first integer argument is passed in register.
423 CCIfType<[i32], CCAssignToReg<[EAX]>>,
424 CCIfType<[i64], CCAssignToReg<[RAX]>>,
426 // The remaining integer arguments are passed on the stack. 32bit integer and
427 // floating-point arguments are aligned to 4 byte and stored in 4 byte slots.
428 // 64bit integer and floating-point arguments are aligned to 8 byte and stored
429 // in 8 byte stack slots.
430 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
431 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
434 // No explicit register is specified for the AnyReg calling convention. The
435 // register allocator may assign the arguments to any free register.
437 // This calling convention is currently only supported by the stackmap and
438 // patchpoint intrinsics. All other uses will result in an assert on Debug
439 // builds. On Release builds we fallback to the X86 C calling convention.
440 def CC_X86_64_AnyReg : CallingConv<[
441 CCCustom<"CC_X86_AnyReg_Error">
444 //===----------------------------------------------------------------------===//
445 // X86 C Calling Convention
446 //===----------------------------------------------------------------------===//
448 /// CC_X86_32_Vector_Common - In all X86-32 calling conventions, extra vector
449 /// values are spilled on the stack.
450 def CC_X86_32_Vector_Common : CallingConv<[
451 // Other SSE vectors get 16-byte stack slots that are 16-byte aligned.
452 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
454 // 256-bit AVX vectors get 32-byte stack slots that are 32-byte aligned.
455 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
456 CCAssignToStack<32, 32>>,
458 // 512-bit AVX 512-bit vectors get 64-byte stack slots that are 64-byte aligned.
459 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
460 CCAssignToStack<64, 64>>
463 // CC_X86_32_Vector_Standard - The first 3 vector arguments are passed in
465 def CC_X86_32_Vector_Standard : CallingConv<[
466 // SSE vector arguments are passed in XMM registers.
467 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
468 CCAssignToReg<[XMM0, XMM1, XMM2]>>>,
470 // AVX 256-bit vector arguments are passed in YMM registers.
471 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
472 CCIfSubtarget<"hasFp256()",
473 CCAssignToReg<[YMM0, YMM1, YMM2]>>>>,
475 // AVX 512-bit vector arguments are passed in ZMM registers.
476 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
477 CCAssignToReg<[ZMM0, ZMM1, ZMM2]>>>,
479 CCDelegateTo<CC_X86_32_Vector_Common>
482 // CC_X86_32_Vector_Darwin - The first 4 vector arguments are passed in
484 def CC_X86_32_Vector_Darwin : CallingConv<[
485 // SSE vector arguments are passed in XMM registers.
486 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
487 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>>,
489 // AVX 256-bit vector arguments are passed in YMM registers.
490 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
491 CCIfSubtarget<"hasFp256()",
492 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>>>,
494 // AVX 512-bit vector arguments are passed in ZMM registers.
495 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
496 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3]>>>,
498 CCDelegateTo<CC_X86_32_Vector_Common>
501 /// CC_X86_32_Common - In all X86-32 calling conventions, extra integers and FP
502 /// values are spilled on the stack.
503 def CC_X86_32_Common : CallingConv<[
504 // Handles byval parameters.
505 CCIfByVal<CCPassByVal<4, 4>>,
507 // The first 3 float or double arguments, if marked 'inreg' and if the call
508 // is not a vararg call and if SSE2 is available, are passed in SSE registers.
509 CCIfNotVarArg<CCIfInReg<CCIfType<[f32,f64],
510 CCIfSubtarget<"hasSSE2()",
511 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>>,
513 // The first 3 __m64 vector arguments are passed in mmx registers if the
514 // call is not a vararg call.
515 CCIfNotVarArg<CCIfType<[x86mmx],
516 CCAssignToReg<[MM0, MM1, MM2]>>>,
518 // Integer/Float values get stored in stack slots that are 4 bytes in
519 // size and 4-byte aligned.
520 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
522 // Doubles get 8-byte slots that are 4-byte aligned.
523 CCIfType<[f64], CCAssignToStack<8, 4>>,
525 // Long doubles get slots whose size depends on the subtarget.
526 CCIfType<[f80], CCAssignToStack<0, 4>>,
528 // Boolean vectors of AVX-512 are passed in SIMD registers.
529 // The call from AVX to AVX-512 function should work,
530 // since the boolean types in AVX/AVX2 are promoted by default.
531 CCIfType<[v2i1], CCPromoteToType<v2i64>>,
532 CCIfType<[v4i1], CCPromoteToType<v4i32>>,
533 CCIfType<[v8i1], CCPromoteToType<v8i16>>,
534 CCIfType<[v16i1], CCPromoteToType<v16i8>>,
535 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
536 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
538 // __m64 vectors get 8-byte stack slots that are 4-byte aligned. They are
539 // passed in the parameter area.
540 CCIfType<[x86mmx], CCAssignToStack<8, 4>>,
542 // Darwin passes vectors in a form that differs from the i386 psABI
543 CCIfSubtarget<"isTargetDarwin()", CCDelegateTo<CC_X86_32_Vector_Darwin>>,
545 // Otherwise, drop to 'normal' X86-32 CC
546 CCDelegateTo<CC_X86_32_Vector_Standard>
549 def CC_X86_32_C : CallingConv<[
550 // Promote i1/i8/i16 arguments to i32.
551 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
553 // The 'nest' parameter, if any, is passed in ECX.
554 CCIfNest<CCAssignToReg<[ECX]>>,
556 // The first 3 integer arguments, if marked 'inreg' and if the call is not
557 // a vararg call, are passed in integer registers.
558 CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>>>,
560 // Otherwise, same as everything else.
561 CCDelegateTo<CC_X86_32_Common>
564 def CC_X86_32_FastCall : CallingConv<[
565 // Promote i1/i8/i16 arguments to i32.
566 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
568 // The 'nest' parameter, if any, is passed in EAX.
569 CCIfNest<CCAssignToReg<[EAX]>>,
571 // The first 2 integer arguments are passed in ECX/EDX
572 CCIfInReg<CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>>,
574 // Otherwise, same as everything else.
575 CCDelegateTo<CC_X86_32_Common>
578 def CC_X86_32_VectorCall : CallingConv<[
579 // The first 6 floating point and vector types of 128 bits or less use
581 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
582 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5]>>,
584 // 256-bit vectors use YMM registers.
585 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
586 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3, YMM4, YMM5]>>,
588 // 512-bit vectors use ZMM registers.
589 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
590 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5]>>,
592 // Otherwise, pass it indirectly.
593 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64,
594 v32i8, v16i16, v8i32, v4i64, v8f32, v4f64,
595 v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
596 CCCustom<"CC_X86_32_VectorCallIndirect">>,
598 // Delegate to fastcall to handle integer types.
599 CCDelegateTo<CC_X86_32_FastCall>
602 def CC_X86_32_ThisCall_Common : CallingConv<[
603 // The first integer argument is passed in ECX
604 CCIfType<[i32], CCAssignToReg<[ECX]>>,
606 // Otherwise, same as everything else.
607 CCDelegateTo<CC_X86_32_Common>
610 def CC_X86_32_ThisCall_Mingw : CallingConv<[
611 // Promote i1/i8/i16 arguments to i32.
612 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
614 CCDelegateTo<CC_X86_32_ThisCall_Common>
617 def CC_X86_32_ThisCall_Win : CallingConv<[
618 // Promote i1/i8/i16 arguments to i32.
619 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
621 // Pass sret arguments indirectly through stack.
622 CCIfSRet<CCAssignToStack<4, 4>>,
624 CCDelegateTo<CC_X86_32_ThisCall_Common>
627 def CC_X86_32_ThisCall : CallingConv<[
628 CCIfSubtarget<"isTargetCygMing()", CCDelegateTo<CC_X86_32_ThisCall_Mingw>>,
629 CCDelegateTo<CC_X86_32_ThisCall_Win>
632 def CC_X86_32_FastCC : CallingConv<[
633 // Handles byval parameters. Note that we can't rely on the delegation
634 // to CC_X86_32_Common for this because that happens after code that
635 // puts arguments in registers.
636 CCIfByVal<CCPassByVal<4, 4>>,
638 // Promote i1/i8/i16 arguments to i32.
639 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
641 // The 'nest' parameter, if any, is passed in EAX.
642 CCIfNest<CCAssignToReg<[EAX]>>,
644 // The first 2 integer arguments are passed in ECX/EDX
645 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>,
647 // The first 3 float or double arguments, if the call is not a vararg
648 // call and if SSE2 is available, are passed in SSE registers.
649 CCIfNotVarArg<CCIfType<[f32,f64],
650 CCIfSubtarget<"hasSSE2()",
651 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
653 // Doubles get 8-byte slots that are 8-byte aligned.
654 CCIfType<[f64], CCAssignToStack<8, 8>>,
656 // Otherwise, same as everything else.
657 CCDelegateTo<CC_X86_32_Common>
660 def CC_X86_32_GHC : CallingConv<[
661 // Promote i8/i16 arguments to i32.
662 CCIfType<[i8, i16], CCPromoteToType<i32>>,
664 // Pass in STG registers: Base, Sp, Hp, R1
665 CCIfType<[i32], CCAssignToReg<[EBX, EBP, EDI, ESI]>>
668 def CC_X86_32_HiPE : CallingConv<[
669 // Promote i8/i16 arguments to i32.
670 CCIfType<[i8, i16], CCPromoteToType<i32>>,
672 // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2
673 CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX, ECX]>>,
675 // Integer/Float values get stored in stack slots that are 4 bytes in
676 // size and 4-byte aligned.
677 CCIfType<[i32, f32], CCAssignToStack<4, 4>>
680 // X86-64 Intel OpenCL built-ins calling convention.
681 def CC_Intel_OCL_BI : CallingConv<[
683 CCIfType<[i32], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[ECX, EDX, R8D, R9D]>>>,
684 CCIfType<[i64], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[RCX, RDX, R8, R9 ]>>>,
686 CCIfType<[i32], CCIfSubtarget<"is64Bit()", CCAssignToReg<[EDI, ESI, EDX, ECX]>>>,
687 CCIfType<[i64], CCIfSubtarget<"is64Bit()", CCAssignToReg<[RDI, RSI, RDX, RCX]>>>,
689 CCIfType<[i32], CCAssignToStack<4, 4>>,
691 // The SSE vector arguments are passed in XMM registers.
692 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64],
693 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>,
695 // The 256-bit vector arguments are passed in YMM registers.
696 CCIfType<[v8f32, v4f64, v8i32, v4i64],
697 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>,
699 // The 512-bit vector arguments are passed in ZMM registers.
700 CCIfType<[v16f32, v8f64, v16i32, v8i64],
701 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3]>>,
703 // Pass masks in mask registers
704 CCIfType<[v16i1, v8i1], CCAssignToReg<[K1]>>,
706 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>,
707 CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64_C>>,
708 CCDelegateTo<CC_X86_32_C>
711 //===----------------------------------------------------------------------===//
712 // X86 Root Argument Calling Conventions
713 //===----------------------------------------------------------------------===//
715 // This is the root argument convention for the X86-32 backend.
716 def CC_X86_32 : CallingConv<[
717 CCIfCC<"CallingConv::X86_FastCall", CCDelegateTo<CC_X86_32_FastCall>>,
718 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<CC_X86_32_VectorCall>>,
719 CCIfCC<"CallingConv::X86_ThisCall", CCDelegateTo<CC_X86_32_ThisCall>>,
720 CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_X86_32_FastCC>>,
721 CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_32_GHC>>,
722 CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_32_HiPE>>,
724 // Otherwise, drop to normal X86-32 CC
725 CCDelegateTo<CC_X86_32_C>
728 // This is the root argument convention for the X86-64 backend.
729 def CC_X86_64 : CallingConv<[
730 CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_64_GHC>>,
731 CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_64_HiPE>>,
732 CCIfCC<"CallingConv::WebKit_JS", CCDelegateTo<CC_X86_64_WebKit_JS>>,
733 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<CC_X86_64_AnyReg>>,
734 CCIfCC<"CallingConv::X86_64_Win64", CCDelegateTo<CC_X86_Win64_C>>,
735 CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo<CC_X86_64_C>>,
736 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<CC_X86_Win64_VectorCall>>,
738 // Mingw64 and native Win64 use Win64 CC
739 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>,
741 // Otherwise, drop to normal X86-64 CC
742 CCDelegateTo<CC_X86_64_C>
745 // This is the argument convention used for the entire X86 backend.
746 def CC_X86 : CallingConv<[
747 CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo<CC_Intel_OCL_BI>>,
748 CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64>>,
749 CCDelegateTo<CC_X86_32>
752 //===----------------------------------------------------------------------===//
753 // Callee-saved Registers.
754 //===----------------------------------------------------------------------===//
756 def CSR_NoRegs : CalleeSavedRegs<(add)>;
758 def CSR_32 : CalleeSavedRegs<(add ESI, EDI, EBX, EBP)>;
759 def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>;
761 def CSR_32EHRet : CalleeSavedRegs<(add EAX, EDX, CSR_32)>;
762 def CSR_64EHRet : CalleeSavedRegs<(add RAX, RDX, CSR_64)>;
764 def CSR_Win64 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15,
765 (sequence "XMM%u", 6, 15))>;
767 // All GPRs - except r11
768 def CSR_64_RT_MostRegs : CalleeSavedRegs<(add CSR_64, RAX, RCX, RDX, RSI, RDI,
771 // All registers - except r11
772 def CSR_64_RT_AllRegs : CalleeSavedRegs<(add CSR_64_RT_MostRegs,
773 (sequence "XMM%u", 0, 15))>;
774 def CSR_64_RT_AllRegs_AVX : CalleeSavedRegs<(add CSR_64_RT_MostRegs,
775 (sequence "YMM%u", 0, 15))>;
777 def CSR_64_MostRegs : CalleeSavedRegs<(add RBX, RCX, RDX, RSI, RDI, R8, R9, R10,
778 R11, R12, R13, R14, R15, RBP,
779 (sequence "XMM%u", 0, 15))>;
781 def CSR_64_AllRegs : CalleeSavedRegs<(add CSR_64_MostRegs, RAX, RSP,
782 (sequence "XMM%u", 16, 31))>;
783 def CSR_64_AllRegs_AVX : CalleeSavedRegs<(sub (add CSR_64_MostRegs, RAX, RSP,
784 (sequence "YMM%u", 0, 31)),
785 (sequence "XMM%u", 0, 15))>;
787 // Standard C + YMM6-15
788 def CSR_Win64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12,
790 (sequence "YMM%u", 6, 15))>;
792 def CSR_Win64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI,
794 (sequence "ZMM%u", 6, 21),
796 //Standard C + XMM 8-15
797 def CSR_64_Intel_OCL_BI : CalleeSavedRegs<(add CSR_64,
798 (sequence "XMM%u", 8, 15))>;
800 //Standard C + YMM 8-15
801 def CSR_64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add CSR_64,
802 (sequence "YMM%u", 8, 15))>;
804 def CSR_64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RDI, RSI, R14, R15,
805 (sequence "ZMM%u", 16, 31),