1 //===- X86CallingConv.td - Calling Conventions X86 32/64 ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This describes the calling conventions for the X86-32 and X86-64
13 //===----------------------------------------------------------------------===//
15 /// CCIfSubtarget - Match if the current subtarget has a feature F.
16 class CCIfSubtarget<string F, CCAction A>
17 : CCIf<!strconcat("State.getTarget().getSubtarget<X86Subtarget>().", F), A>;
19 //===----------------------------------------------------------------------===//
20 // Return Value Calling Conventions
21 //===----------------------------------------------------------------------===//
23 // Return-value conventions common to all X86 CC's.
24 def RetCC_X86Common : CallingConv<[
25 // Scalar values are returned in AX first, then DX.
26 CCIfType<[i8] , CCAssignToReg<[AL]>>,
27 CCIfType<[i16], CCAssignToReg<[AX, DX]>>,
28 CCIfType<[i32], CCAssignToReg<[EAX, EDX]>>,
29 CCIfType<[i64], CCAssignToReg<[RAX, RDX]>>,
31 // Vector types are returned in XMM0 and XMM1, when they fit. If the target
32 // doesn't have XMM registers, it won't have vector types.
33 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
34 CCAssignToReg<[XMM0,XMM1]>>,
36 // MMX vector types are always returned in MM0. If the target doesn't have
37 // MM0, it doesn't support these vector types.
38 CCIfType<[v8i8, v4i16, v2i32, v1i64, v2f32], CCAssignToReg<[MM0]>>,
40 // Long double types are always returned in ST0 (even with SSE).
41 CCIfType<[f80], CCAssignToReg<[ST0, ST1]>>
44 // X86-32 C return-value convention.
45 def RetCC_X86_32_C : CallingConv<[
46 // The X86-32 calling convention returns FP values in ST0, unless marked
47 // with "inreg" (used here to distinguish one kind of reg from another,
48 // weirdly; this is really the sse-regparm calling convention) in which
49 // case they use XMM0, otherwise it is the same as the common X86 calling
51 CCIfInReg<CCIfSubtarget<"hasSSE2()",
52 CCIfType<[f32, f64], CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
53 CCIfType<[f32,f64], CCAssignToReg<[ST0, ST1]>>,
54 CCDelegateTo<RetCC_X86Common>
57 // X86-32 FastCC return-value convention.
58 def RetCC_X86_32_Fast : CallingConv<[
59 // The X86-32 fastcc returns 1, 2, or 3 FP values in XMM0-2 if the target has
60 // SSE2, otherwise it is the the C calling conventions.
61 // This can happen when a float, 2 x float, or 3 x float vector is split by
62 // target lowering, and is returned in 1-3 sse regs.
63 CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
64 CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
65 CCDelegateTo<RetCC_X86Common>
68 // X86-64 C return-value convention.
69 def RetCC_X86_64_C : CallingConv<[
70 // The X86-64 calling convention always returns FP values in XMM0.
71 CCIfType<[f32], CCAssignToReg<[XMM0, XMM1]>>,
72 CCIfType<[f64], CCAssignToReg<[XMM0, XMM1]>>,
74 // MMX vector types are always returned in XMM0.
75 CCIfType<[v8i8, v4i16, v2i32, v1i64, v2f32], CCAssignToReg<[XMM0, XMM1]>>,
76 CCDelegateTo<RetCC_X86Common>
79 // X86-Win64 C return-value convention.
80 def RetCC_X86_Win64_C : CallingConv<[
81 // The X86-Win64 calling convention always returns __m64 values in RAX.
82 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToReg<[RAX]>>,
84 // And FP in XMM0 only.
85 CCIfType<[f32], CCAssignToReg<[XMM0]>>,
86 CCIfType<[f64], CCAssignToReg<[XMM0]>>,
88 // Otherwise, everything is the same as 'normal' X86-64 C CC.
89 CCDelegateTo<RetCC_X86_64_C>
93 // This is the root return-value convention for the X86-32 backend.
94 def RetCC_X86_32 : CallingConv<[
95 // If FastCC, use RetCC_X86_32_Fast.
96 CCIfCC<"CallingConv::Fast", CCDelegateTo<RetCC_X86_32_Fast>>,
97 // Otherwise, use RetCC_X86_32_C.
98 CCDelegateTo<RetCC_X86_32_C>
101 // This is the root return-value convention for the X86-64 backend.
102 def RetCC_X86_64 : CallingConv<[
103 // Mingw64 and native Win64 use Win64 CC
104 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<RetCC_X86_Win64_C>>,
106 // Otherwise, drop to normal X86-64 CC
107 CCDelegateTo<RetCC_X86_64_C>
110 // This is the return-value convention used for the entire X86 backend.
111 def RetCC_X86 : CallingConv<[
112 CCIfSubtarget<"is64Bit()", CCDelegateTo<RetCC_X86_64>>,
113 CCDelegateTo<RetCC_X86_32>
116 //===----------------------------------------------------------------------===//
117 // X86-64 Argument Calling Conventions
118 //===----------------------------------------------------------------------===//
120 def CC_X86_64_C : CallingConv<[
121 // Handles byval parameters.
122 CCIfByVal<CCPassByVal<8, 8>>,
124 // Promote i8/i16 arguments to i32.
125 CCIfType<[i8, i16], CCPromoteToType<i32>>,
127 // The 'nest' parameter, if any, is passed in R10.
128 CCIfNest<CCAssignToReg<[R10]>>,
130 // The first 6 integer arguments are passed in integer registers.
131 CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D, R9D]>>,
132 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
134 // The first 8 FP/Vector arguments are passed in XMM registers.
135 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
136 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>,
138 // The first 8 MMX (except for v1i64) vector arguments are passed in XMM
139 // registers on Darwin.
140 CCIfType<[v8i8, v4i16, v2i32, v2f32],
141 CCIfSubtarget<"isTargetDarwin()",
142 CCIfSubtarget<"hasSSE2()",
143 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>>,
145 // The first 8 v1i64 vector arguments are passed in GPRs on Darwin.
147 CCIfSubtarget<"isTargetDarwin()",
148 CCAssignToReg<[RDI, RSI, RDX, RCX, R8]>>>,
150 // Integer/FP values get stored in stack slots that are 8 bytes in size and
151 // 8-byte aligned if there are no more registers to hold them.
152 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
154 // Long doubles get stack slots whose size and alignment depends on the
156 CCIfType<[f80], CCAssignToStack<0, 0>>,
158 // Vectors get 16-byte stack slots that are 16-byte aligned.
159 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
161 // __m64 vectors get 8-byte stack slots that are 8-byte aligned.
162 CCIfType<[v8i8, v4i16, v2i32, v1i64, v2f32], CCAssignToStack<8, 8>>
165 // Calling convention used on Win64
166 def CC_X86_Win64_C : CallingConv<[
167 // FIXME: Handle byval stuff.
168 // FIXME: Handle varargs.
170 // Promote i8/i16 arguments to i32.
171 CCIfType<[i8, i16], CCPromoteToType<i32>>,
173 // The 'nest' parameter, if any, is passed in R10.
174 CCIfNest<CCAssignToReg<[R10]>>,
176 // The first 4 integer arguments are passed in integer registers.
177 CCIfType<[i32], CCAssignToRegWithShadow<[ECX , EDX , R8D , R9D ],
178 [XMM0, XMM1, XMM2, XMM3]>>,
179 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
180 [XMM0, XMM1, XMM2, XMM3]>>,
182 // The first 4 FP/Vector arguments are passed in XMM registers.
183 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
184 CCAssignToRegWithShadow<[XMM0, XMM1, XMM2, XMM3],
185 [RCX , RDX , R8 , R9 ]>>,
187 // The first 4 MMX vector arguments are passed in GPRs.
188 CCIfType<[v8i8, v4i16, v2i32, v1i64, v2f32],
189 CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
190 [XMM0, XMM1, XMM2, XMM3]>>,
192 // Integer/FP values get stored in stack slots that are 8 bytes in size and
193 // 16-byte aligned if there are no more registers to hold them.
194 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 16>>,
196 // Long doubles get stack slots whose size and alignment depends on the
198 CCIfType<[f80], CCAssignToStack<0, 0>>,
200 // Vectors get 16-byte stack slots that are 16-byte aligned.
201 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
203 // __m64 vectors get 8-byte stack slots that are 16-byte aligned.
204 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 16>>
207 // Tail call convention (fast): One register is reserved for target address,
209 def CC_X86_64_TailCall : CallingConv<[
210 // Handles byval parameters.
211 CCIfByVal<CCPassByVal<8, 8>>,
213 // Promote i8/i16 arguments to i32.
214 CCIfType<[i8, i16], CCPromoteToType<i32>>,
216 // The 'nest' parameter, if any, is passed in R10.
217 CCIfNest<CCAssignToReg<[R10]>>,
219 // The first 6 integer arguments are passed in integer registers.
220 CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D]>>,
221 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8]>>,
223 // The first 8 FP/Vector arguments are passed in XMM registers.
224 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
225 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>,
227 // The first 8 MMX (except for v1i64) vector arguments are passed in XMM
228 // registers on Darwin.
229 CCIfType<[v8i8, v4i16, v2i32, v2f32],
230 CCIfSubtarget<"isTargetDarwin()",
231 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>,
233 // The first 8 v1i64 vector arguments are passed in GPRs on Darwin.
235 CCIfSubtarget<"isTargetDarwin()",
236 CCAssignToReg<[RDI, RSI, RDX, RCX, R8]>>>,
238 // Integer/FP values get stored in stack slots that are 8 bytes in size and
239 // 8-byte aligned if there are no more registers to hold them.
240 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
242 // Vectors get 16-byte stack slots that are 16-byte aligned.
243 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
245 // __m64 vectors get 8-byte stack slots that are 8-byte aligned.
246 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 8>>
250 //===----------------------------------------------------------------------===//
251 // X86 C Calling Convention
252 //===----------------------------------------------------------------------===//
254 /// CC_X86_32_Common - In all X86-32 calling conventions, extra integers and FP
255 /// values are spilled on the stack, and the first 4 vector values go in XMM
257 def CC_X86_32_Common : CallingConv<[
258 // Handles byval parameters.
259 CCIfByVal<CCPassByVal<4, 4>>,
261 // The first 3 float or double arguments, if marked 'inreg' and if the call
262 // is not a vararg call and if SSE2 is available, are passed in SSE registers.
263 CCIfNotVarArg<CCIfInReg<CCIfType<[f32,f64],
264 CCIfSubtarget<"hasSSE2()",
265 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>>,
267 // The first 3 __m64 (except for v1i64) vector arguments are passed in mmx
268 // registers if the call is not a vararg call.
269 CCIfNotVarArg<CCIfType<[v8i8, v4i16, v2i32, v2f32],
270 CCAssignToReg<[MM0, MM1, MM2]>>>,
272 // Integer/Float values get stored in stack slots that are 4 bytes in
273 // size and 4-byte aligned.
274 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
276 // Doubles get 8-byte slots that are 4-byte aligned.
277 CCIfType<[f64], CCAssignToStack<8, 4>>,
279 // Long doubles get slots whose size depends on the subtarget.
280 CCIfType<[f80], CCAssignToStack<0, 4>>,
282 // The first 4 SSE vector arguments are passed in XMM registers.
283 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
284 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>>,
286 // Other SSE vectors get 16-byte stack slots that are 16-byte aligned.
287 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
289 // __m64 vectors get 8-byte stack slots that are 4-byte aligned. They are
290 // passed in the parameter area.
291 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 4>>]>;
293 def CC_X86_32_C : CallingConv<[
294 // Promote i8/i16 arguments to i32.
295 CCIfType<[i8, i16], CCPromoteToType<i32>>,
297 // The 'nest' parameter, if any, is passed in ECX.
298 CCIfNest<CCAssignToReg<[ECX]>>,
300 // The first 3 integer arguments, if marked 'inreg' and if the call is not
301 // a vararg call, are passed in integer registers.
302 CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>>>,
304 // Otherwise, same as everything else.
305 CCDelegateTo<CC_X86_32_Common>
308 def CC_X86_32_FastCall : CallingConv<[
309 // Promote i8/i16 arguments to i32.
310 CCIfType<[i8, i16], CCPromoteToType<i32>>,
312 // The 'nest' parameter, if any, is passed in EAX.
313 CCIfNest<CCAssignToReg<[EAX]>>,
315 // The first 2 integer arguments are passed in ECX/EDX
316 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>,
318 // Otherwise, same as everything else.
319 CCDelegateTo<CC_X86_32_Common>
322 def CC_X86_32_FastCC : CallingConv<[
323 // Promote i8/i16 arguments to i32.
324 CCIfType<[i8, i16], CCPromoteToType<i32>>,
326 // The 'nest' parameter, if any, is passed in EAX.
327 CCIfNest<CCAssignToReg<[EAX]>>,
329 // The first 2 integer arguments are passed in ECX/EDX
330 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>,
332 // The first 3 float or double arguments, if the call is not a vararg
333 // call and if SSE2 is available, are passed in SSE registers.
334 CCIfNotVarArg<CCIfType<[f32,f64],
335 CCIfSubtarget<"hasSSE2()",
336 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
338 // Doubles get 8-byte slots that are 8-byte aligned.
339 CCIfType<[f64], CCAssignToStack<8, 8>>,
341 // Otherwise, same as everything else.
342 CCDelegateTo<CC_X86_32_Common>