1 //===- X86CallingConv.td - Calling Conventions X86 32/64 ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This describes the calling conventions for the X86-32 and X86-64
13 //===----------------------------------------------------------------------===//
15 /// CCIfSubtarget - Match if the current subtarget has a feature F.
16 class CCIfSubtarget<string F, CCAction A>
17 : CCIf<!strconcat("State.getTarget().getSubtarget<X86Subtarget>().", F), A>;
19 //===----------------------------------------------------------------------===//
20 // Return Value Calling Conventions
21 //===----------------------------------------------------------------------===//
23 // Return-value conventions common to all X86 CC's.
24 def RetCC_X86Common : CallingConv<[
25 // Scalar values are returned in AX first, then DX.
26 CCIfType<[i8] , CCAssignToReg<[AL]>>,
27 CCIfType<[i16], CCAssignToReg<[AX, DX]>>,
28 CCIfType<[i32], CCAssignToReg<[EAX, EDX]>>,
29 CCIfType<[i64], CCAssignToReg<[RAX, RDX]>>,
31 // Vector types are returned in XMM0 and XMM1, when they fit. XMMM2 and XMM3
32 // can only be used by ABI non-compliant code. If the target doesn't have XMM
33 // registers, it won't have vector types.
34 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
35 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,
37 // MMX vector types are always returned in MM0. If the target doesn't have
38 // MM0, it doesn't support these vector types.
39 CCIfType<[v8i8, v4i16, v2i32, v1i64, v2f32], CCAssignToReg<[MM0]>>,
41 // Long double types are always returned in ST0 (even with SSE).
42 CCIfType<[f80], CCAssignToReg<[ST0, ST1]>>
45 // X86-32 C return-value convention.
46 def RetCC_X86_32_C : CallingConv<[
47 // The X86-32 calling convention returns FP values in ST0, unless marked
48 // with "inreg" (used here to distinguish one kind of reg from another,
49 // weirdly; this is really the sse-regparm calling convention) in which
50 // case they use XMM0, otherwise it is the same as the common X86 calling
52 CCIfInReg<CCIfSubtarget<"hasSSE2()",
53 CCIfType<[f32, f64], CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
54 CCIfType<[f32,f64], CCAssignToReg<[ST0, ST1]>>,
55 CCDelegateTo<RetCC_X86Common>
58 // X86-32 FastCC return-value convention.
59 def RetCC_X86_32_Fast : CallingConv<[
60 // The X86-32 fastcc returns 1, 2, or 3 FP values in XMM0-2 if the target has
61 // SSE2, otherwise it is the the C calling conventions.
62 // This can happen when a float, 2 x float, or 3 x float vector is split by
63 // target lowering, and is returned in 1-3 sse regs.
64 CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
65 CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
66 CCDelegateTo<RetCC_X86Common>
69 // X86-64 C return-value convention.
70 def RetCC_X86_64_C : CallingConv<[
71 // The X86-64 calling convention always returns FP values in XMM0.
72 CCIfType<[f32], CCAssignToReg<[XMM0, XMM1]>>,
73 CCIfType<[f64], CCAssignToReg<[XMM0, XMM1]>>,
75 // MMX vector types are always returned in XMM0 except for v1i64 which is
76 // returned in RAX. This disagrees with ABI documentation but is bug
77 // compatible with gcc.
78 CCIfType<[v1i64], CCAssignToReg<[RAX]>>,
79 CCIfType<[v8i8, v4i16, v2i32, v2f32], CCAssignToReg<[XMM0, XMM1]>>,
80 CCDelegateTo<RetCC_X86Common>
83 // X86-Win64 C return-value convention.
84 def RetCC_X86_Win64_C : CallingConv<[
85 // The X86-Win64 calling convention always returns __m64 values in RAX.
86 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToReg<[RAX]>>,
88 // And FP in XMM0 only.
89 CCIfType<[f32], CCAssignToReg<[XMM0]>>,
90 CCIfType<[f64], CCAssignToReg<[XMM0]>>,
92 // Otherwise, everything is the same as 'normal' X86-64 C CC.
93 CCDelegateTo<RetCC_X86_64_C>
97 // This is the root return-value convention for the X86-32 backend.
98 def RetCC_X86_32 : CallingConv<[
99 // If FastCC, use RetCC_X86_32_Fast.
100 CCIfCC<"CallingConv::Fast", CCDelegateTo<RetCC_X86_32_Fast>>,
101 // Otherwise, use RetCC_X86_32_C.
102 CCDelegateTo<RetCC_X86_32_C>
105 // This is the root return-value convention for the X86-64 backend.
106 def RetCC_X86_64 : CallingConv<[
107 // Mingw64 and native Win64 use Win64 CC
108 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<RetCC_X86_Win64_C>>,
110 // Otherwise, drop to normal X86-64 CC
111 CCDelegateTo<RetCC_X86_64_C>
114 // This is the return-value convention used for the entire X86 backend.
115 def RetCC_X86 : CallingConv<[
116 CCIfSubtarget<"is64Bit()", CCDelegateTo<RetCC_X86_64>>,
117 CCDelegateTo<RetCC_X86_32>
120 //===----------------------------------------------------------------------===//
121 // X86-64 Argument Calling Conventions
122 //===----------------------------------------------------------------------===//
124 def CC_X86_64_C : CallingConv<[
125 // Handles byval parameters.
126 CCIfByVal<CCPassByVal<8, 8>>,
128 // Promote i8/i16 arguments to i32.
129 CCIfType<[i8, i16], CCPromoteToType<i32>>,
131 // The 'nest' parameter, if any, is passed in R10.
132 CCIfNest<CCAssignToReg<[R10]>>,
134 // The first 6 integer arguments are passed in integer registers.
135 CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D, R9D]>>,
136 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
138 // The first 8 FP/Vector arguments are passed in XMM registers.
139 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
140 CCIfSubtarget<"hasSSE1()",
141 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>,
143 // The first 8 MMX (except for v1i64) vector arguments are passed in XMM
144 // registers on Darwin.
145 CCIfType<[v8i8, v4i16, v2i32, v2f32],
146 CCIfSubtarget<"isTargetDarwin()",
147 CCIfSubtarget<"hasSSE2()",
148 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>>,
150 // The first 8 v1i64 vector arguments are passed in GPRs on Darwin.
152 CCIfSubtarget<"isTargetDarwin()",
153 CCAssignToReg<[RDI, RSI, RDX, RCX, R8]>>>,
155 // Integer/FP values get stored in stack slots that are 8 bytes in size and
156 // 8-byte aligned if there are no more registers to hold them.
157 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
159 // Long doubles get stack slots whose size and alignment depends on the
161 CCIfType<[f80], CCAssignToStack<0, 0>>,
163 // Vectors get 16-byte stack slots that are 16-byte aligned.
164 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
166 // __m64 vectors get 8-byte stack slots that are 8-byte aligned.
167 CCIfType<[v8i8, v4i16, v2i32, v1i64, v2f32], CCAssignToStack<8, 8>>
170 // Calling convention used on Win64
171 def CC_X86_Win64_C : CallingConv<[
172 // FIXME: Handle byval stuff.
173 // FIXME: Handle varargs.
175 // Promote i8/i16 arguments to i32.
176 CCIfType<[i8, i16], CCPromoteToType<i32>>,
178 // The 'nest' parameter, if any, is passed in R10.
179 CCIfNest<CCAssignToReg<[R10]>>,
181 // The first 4 integer arguments are passed in integer registers.
182 CCIfType<[i32], CCAssignToRegWithShadow<[ECX , EDX , R8D , R9D ],
183 [XMM0, XMM1, XMM2, XMM3]>>,
184 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
185 [XMM0, XMM1, XMM2, XMM3]>>,
187 // The first 4 FP/Vector arguments are passed in XMM registers.
188 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
189 CCAssignToRegWithShadow<[XMM0, XMM1, XMM2, XMM3],
190 [RCX , RDX , R8 , R9 ]>>,
192 // The first 4 MMX vector arguments are passed in GPRs.
193 CCIfType<[v8i8, v4i16, v2i32, v1i64, v2f32],
194 CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
195 [XMM0, XMM1, XMM2, XMM3]>>,
197 // Integer/FP values get stored in stack slots that are 8 bytes in size and
198 // 16-byte aligned if there are no more registers to hold them.
199 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 16>>,
201 // Long doubles get stack slots whose size and alignment depends on the
203 CCIfType<[f80], CCAssignToStack<0, 0>>,
205 // Vectors get 16-byte stack slots that are 16-byte aligned.
206 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
208 // __m64 vectors get 8-byte stack slots that are 16-byte aligned.
209 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 16>>
212 // Tail call convention (fast): One register is reserved for target address,
214 def CC_X86_64_TailCall : CallingConv<[
215 // Handles byval parameters.
216 CCIfByVal<CCPassByVal<8, 8>>,
218 // Promote i8/i16 arguments to i32.
219 CCIfType<[i8, i16], CCPromoteToType<i32>>,
221 // The 'nest' parameter, if any, is passed in R10.
222 CCIfNest<CCAssignToReg<[R10]>>,
224 // The first 6 integer arguments are passed in integer registers.
225 CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D]>>,
226 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8]>>,
228 // The first 8 FP/Vector arguments are passed in XMM registers.
229 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
230 CCIfSubtarget<"hasSSE1()",
231 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>,
233 // The first 8 MMX (except for v1i64) vector arguments are passed in XMM
234 // registers on Darwin.
235 CCIfType<[v8i8, v4i16, v2i32, v2f32],
236 CCIfSubtarget<"isTargetDarwin()",
237 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>,
239 // The first 8 v1i64 vector arguments are passed in GPRs on Darwin.
241 CCIfSubtarget<"isTargetDarwin()",
242 CCAssignToReg<[RDI, RSI, RDX, RCX, R8]>>>,
244 // Integer/FP values get stored in stack slots that are 8 bytes in size and
245 // 8-byte aligned if there are no more registers to hold them.
246 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
248 // Vectors get 16-byte stack slots that are 16-byte aligned.
249 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
251 // __m64 vectors get 8-byte stack slots that are 8-byte aligned.
252 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 8>>
256 //===----------------------------------------------------------------------===//
257 // X86 C Calling Convention
258 //===----------------------------------------------------------------------===//
260 /// CC_X86_32_Common - In all X86-32 calling conventions, extra integers and FP
261 /// values are spilled on the stack, and the first 4 vector values go in XMM
263 def CC_X86_32_Common : CallingConv<[
264 // Handles byval parameters.
265 CCIfByVal<CCPassByVal<4, 4>>,
267 // The first 3 float or double arguments, if marked 'inreg' and if the call
268 // is not a vararg call and if SSE2 is available, are passed in SSE registers.
269 CCIfNotVarArg<CCIfInReg<CCIfType<[f32,f64],
270 CCIfSubtarget<"hasSSE2()",
271 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>>,
273 // The first 3 __m64 (except for v1i64) vector arguments are passed in mmx
274 // registers if the call is not a vararg call.
275 CCIfNotVarArg<CCIfType<[v8i8, v4i16, v2i32, v2f32],
276 CCAssignToReg<[MM0, MM1, MM2]>>>,
278 // Integer/Float values get stored in stack slots that are 4 bytes in
279 // size and 4-byte aligned.
280 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
282 // Doubles get 8-byte slots that are 4-byte aligned.
283 CCIfType<[f64], CCAssignToStack<8, 4>>,
285 // Long doubles get slots whose size depends on the subtarget.
286 CCIfType<[f80], CCAssignToStack<0, 4>>,
288 // The first 4 SSE vector arguments are passed in XMM registers.
289 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
290 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>>,
292 // Other SSE vectors get 16-byte stack slots that are 16-byte aligned.
293 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
295 // __m64 vectors get 8-byte stack slots that are 4-byte aligned. They are
296 // passed in the parameter area.
297 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 4>>]>;
299 def CC_X86_32_C : CallingConv<[
300 // Promote i8/i16 arguments to i32.
301 CCIfType<[i8, i16], CCPromoteToType<i32>>,
303 // The 'nest' parameter, if any, is passed in ECX.
304 CCIfNest<CCAssignToReg<[ECX]>>,
306 // The first 3 integer arguments, if marked 'inreg' and if the call is not
307 // a vararg call, are passed in integer registers.
308 CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>>>,
310 // Otherwise, same as everything else.
311 CCDelegateTo<CC_X86_32_Common>
314 def CC_X86_32_FastCall : CallingConv<[
315 // Promote i8/i16 arguments to i32.
316 CCIfType<[i8, i16], CCPromoteToType<i32>>,
318 // The 'nest' parameter, if any, is passed in EAX.
319 CCIfNest<CCAssignToReg<[EAX]>>,
321 // The first 2 integer arguments are passed in ECX/EDX
322 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>,
324 // Otherwise, same as everything else.
325 CCDelegateTo<CC_X86_32_Common>
328 def CC_X86_32_FastCC : CallingConv<[
329 // Handles byval parameters. Note that we can't rely on the delegation
330 // to CC_X86_32_Common for this because that happens after code that
331 // puts arguments in registers.
332 CCIfByVal<CCPassByVal<4, 4>>,
334 // Promote i8/i16 arguments to i32.
335 CCIfType<[i8, i16], CCPromoteToType<i32>>,
337 // The 'nest' parameter, if any, is passed in EAX.
338 CCIfNest<CCAssignToReg<[EAX]>>,
340 // The first 2 integer arguments are passed in ECX/EDX
341 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>,
343 // The first 3 float or double arguments, if the call is not a vararg
344 // call and if SSE2 is available, are passed in SSE registers.
345 CCIfNotVarArg<CCIfType<[f32,f64],
346 CCIfSubtarget<"hasSSE2()",
347 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
349 // Doubles get 8-byte slots that are 8-byte aligned.
350 CCIfType<[f64], CCAssignToStack<8, 8>>,
352 // Otherwise, same as everything else.
353 CCDelegateTo<CC_X86_32_Common>