1 //===- X86CallingConv.td - Calling Conventions X86 32/64 ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This describes the calling conventions for the X86-32 and X86-64
13 //===----------------------------------------------------------------------===//
15 /// CCIfSubtarget - Match if the current subtarget has a feature F.
16 class CCIfSubtarget<string F, CCAction A>
17 : CCIf<!strconcat("State.getTarget().getSubtarget<X86Subtarget>().", F), A>;
19 //===----------------------------------------------------------------------===//
20 // Return Value Calling Conventions
21 //===----------------------------------------------------------------------===//
23 // Return-value conventions common to all X86 CC's.
24 def RetCC_X86Common : CallingConv<[
25 // Scalar values are returned in AX first, then DX.
26 CCIfType<[i8] , CCAssignToReg<[AL]>>,
27 CCIfType<[i16], CCAssignToReg<[AX, DX]>>,
28 CCIfType<[i32], CCAssignToReg<[EAX, EDX]>>,
29 CCIfType<[i64], CCAssignToReg<[RAX, RDX]>>,
31 // Vector types are returned in XMM0 and XMM1, when they fit. XMMM2 and XMM3
32 // can only be used by ABI non-compliant code. If the target doesn't have XMM
33 // registers, it won't have vector types.
34 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
35 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,
37 // MMX vector types are always returned in MM0. If the target doesn't have
38 // MM0, it doesn't support these vector types.
39 CCIfType<[v8i8, v4i16, v2i32, v1i64, v2f32], CCAssignToReg<[MM0]>>,
41 // Long double types are always returned in ST0 (even with SSE).
42 CCIfType<[f80], CCAssignToReg<[ST0, ST1]>>
45 // X86-32 C return-value convention.
46 def RetCC_X86_32_C : CallingConv<[
47 // The X86-32 calling convention returns FP values in ST0, unless marked
48 // with "inreg" (used here to distinguish one kind of reg from another,
49 // weirdly; this is really the sse-regparm calling convention) in which
50 // case they use XMM0, otherwise it is the same as the common X86 calling
52 CCIfInReg<CCIfSubtarget<"hasSSE2()",
53 CCIfType<[f32, f64], CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
54 CCIfType<[f32,f64], CCAssignToReg<[ST0, ST1]>>,
55 CCDelegateTo<RetCC_X86Common>
58 // X86-32 FastCC return-value convention.
59 def RetCC_X86_32_Fast : CallingConv<[
60 // The X86-32 fastcc returns 1, 2, or 3 FP values in XMM0-2 if the target has
61 // SSE2, otherwise it is the the C calling conventions.
62 // This can happen when a float, 2 x float, or 3 x float vector is split by
63 // target lowering, and is returned in 1-3 sse regs.
64 CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
65 CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
66 CCDelegateTo<RetCC_X86Common>
69 // X86-64 C return-value convention.
70 def RetCC_X86_64_C : CallingConv<[
71 // The X86-64 calling convention always returns FP values in XMM0.
72 CCIfType<[f32], CCAssignToReg<[XMM0, XMM1]>>,
73 CCIfType<[f64], CCAssignToReg<[XMM0, XMM1]>>,
75 // MMX vector types are always returned in XMM0.
76 CCIfType<[v8i8, v4i16, v2i32, v1i64, v2f32], CCAssignToReg<[XMM0, XMM1]>>,
77 CCDelegateTo<RetCC_X86Common>
80 // X86-Win64 C return-value convention.
81 def RetCC_X86_Win64_C : CallingConv<[
82 // The X86-Win64 calling convention always returns __m64 values in RAX.
83 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToReg<[RAX]>>,
85 // And FP in XMM0 only.
86 CCIfType<[f32], CCAssignToReg<[XMM0]>>,
87 CCIfType<[f64], CCAssignToReg<[XMM0]>>,
89 // Otherwise, everything is the same as 'normal' X86-64 C CC.
90 CCDelegateTo<RetCC_X86_64_C>
94 // This is the root return-value convention for the X86-32 backend.
95 def RetCC_X86_32 : CallingConv<[
96 // If FastCC, use RetCC_X86_32_Fast.
97 CCIfCC<"CallingConv::Fast", CCDelegateTo<RetCC_X86_32_Fast>>,
98 // Otherwise, use RetCC_X86_32_C.
99 CCDelegateTo<RetCC_X86_32_C>
102 // This is the root return-value convention for the X86-64 backend.
103 def RetCC_X86_64 : CallingConv<[
104 // Mingw64 and native Win64 use Win64 CC
105 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<RetCC_X86_Win64_C>>,
107 // Otherwise, drop to normal X86-64 CC
108 CCDelegateTo<RetCC_X86_64_C>
111 // This is the return-value convention used for the entire X86 backend.
112 def RetCC_X86 : CallingConv<[
113 CCIfSubtarget<"is64Bit()", CCDelegateTo<RetCC_X86_64>>,
114 CCDelegateTo<RetCC_X86_32>
117 //===----------------------------------------------------------------------===//
118 // X86-64 Argument Calling Conventions
119 //===----------------------------------------------------------------------===//
121 def CC_X86_64_C : CallingConv<[
122 // Handles byval parameters.
123 CCIfByVal<CCPassByVal<8, 8>>,
125 // Promote i8/i16 arguments to i32.
126 CCIfType<[i8, i16], CCPromoteToType<i32>>,
128 // The 'nest' parameter, if any, is passed in R10.
129 CCIfNest<CCAssignToReg<[R10]>>,
131 // The first 6 integer arguments are passed in integer registers.
132 CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D, R9D]>>,
133 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
135 // The first 8 FP/Vector arguments are passed in XMM registers.
136 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
137 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>,
139 // The first 8 MMX (except for v1i64) vector arguments are passed in XMM
140 // registers on Darwin.
141 CCIfType<[v8i8, v4i16, v2i32, v2f32],
142 CCIfSubtarget<"isTargetDarwin()",
143 CCIfSubtarget<"hasSSE2()",
144 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>>,
146 // The first 8 v1i64 vector arguments are passed in GPRs on Darwin.
148 CCIfSubtarget<"isTargetDarwin()",
149 CCAssignToReg<[RDI, RSI, RDX, RCX, R8]>>>,
151 // Integer/FP values get stored in stack slots that are 8 bytes in size and
152 // 8-byte aligned if there are no more registers to hold them.
153 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
155 // Long doubles get stack slots whose size and alignment depends on the
157 CCIfType<[f80], CCAssignToStack<0, 0>>,
159 // Vectors get 16-byte stack slots that are 16-byte aligned.
160 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
162 // __m64 vectors get 8-byte stack slots that are 8-byte aligned.
163 CCIfType<[v8i8, v4i16, v2i32, v1i64, v2f32], CCAssignToStack<8, 8>>
166 // Calling convention used on Win64
167 def CC_X86_Win64_C : CallingConv<[
168 // FIXME: Handle byval stuff.
169 // FIXME: Handle varargs.
171 // Promote i8/i16 arguments to i32.
172 CCIfType<[i8, i16], CCPromoteToType<i32>>,
174 // The 'nest' parameter, if any, is passed in R10.
175 CCIfNest<CCAssignToReg<[R10]>>,
177 // The first 4 integer arguments are passed in integer registers.
178 CCIfType<[i32], CCAssignToRegWithShadow<[ECX , EDX , R8D , R9D ],
179 [XMM0, XMM1, XMM2, XMM3]>>,
180 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
181 [XMM0, XMM1, XMM2, XMM3]>>,
183 // The first 4 FP/Vector arguments are passed in XMM registers.
184 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
185 CCAssignToRegWithShadow<[XMM0, XMM1, XMM2, XMM3],
186 [RCX , RDX , R8 , R9 ]>>,
188 // The first 4 MMX vector arguments are passed in GPRs.
189 CCIfType<[v8i8, v4i16, v2i32, v1i64, v2f32],
190 CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
191 [XMM0, XMM1, XMM2, XMM3]>>,
193 // Integer/FP values get stored in stack slots that are 8 bytes in size and
194 // 16-byte aligned if there are no more registers to hold them.
195 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 16>>,
197 // Long doubles get stack slots whose size and alignment depends on the
199 CCIfType<[f80], CCAssignToStack<0, 0>>,
201 // Vectors get 16-byte stack slots that are 16-byte aligned.
202 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
204 // __m64 vectors get 8-byte stack slots that are 16-byte aligned.
205 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 16>>
208 // Tail call convention (fast): One register is reserved for target address,
210 def CC_X86_64_TailCall : CallingConv<[
211 // Handles byval parameters.
212 CCIfByVal<CCPassByVal<8, 8>>,
214 // Promote i8/i16 arguments to i32.
215 CCIfType<[i8, i16], CCPromoteToType<i32>>,
217 // The 'nest' parameter, if any, is passed in R10.
218 CCIfNest<CCAssignToReg<[R10]>>,
220 // The first 6 integer arguments are passed in integer registers.
221 CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D]>>,
222 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8]>>,
224 // The first 8 FP/Vector arguments are passed in XMM registers.
225 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
226 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>,
228 // The first 8 MMX (except for v1i64) vector arguments are passed in XMM
229 // registers on Darwin.
230 CCIfType<[v8i8, v4i16, v2i32, v2f32],
231 CCIfSubtarget<"isTargetDarwin()",
232 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>,
234 // The first 8 v1i64 vector arguments are passed in GPRs on Darwin.
236 CCIfSubtarget<"isTargetDarwin()",
237 CCAssignToReg<[RDI, RSI, RDX, RCX, R8]>>>,
239 // Integer/FP values get stored in stack slots that are 8 bytes in size and
240 // 8-byte aligned if there are no more registers to hold them.
241 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
243 // Vectors get 16-byte stack slots that are 16-byte aligned.
244 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
246 // __m64 vectors get 8-byte stack slots that are 8-byte aligned.
247 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 8>>
251 //===----------------------------------------------------------------------===//
252 // X86 C Calling Convention
253 //===----------------------------------------------------------------------===//
255 /// CC_X86_32_Common - In all X86-32 calling conventions, extra integers and FP
256 /// values are spilled on the stack, and the first 4 vector values go in XMM
258 def CC_X86_32_Common : CallingConv<[
259 // Handles byval parameters.
260 CCIfByVal<CCPassByVal<4, 4>>,
262 // The first 3 float or double arguments, if marked 'inreg' and if the call
263 // is not a vararg call and if SSE2 is available, are passed in SSE registers.
264 CCIfNotVarArg<CCIfInReg<CCIfType<[f32,f64],
265 CCIfSubtarget<"hasSSE2()",
266 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>>,
268 // The first 3 __m64 (except for v1i64) vector arguments are passed in mmx
269 // registers if the call is not a vararg call.
270 CCIfNotVarArg<CCIfType<[v8i8, v4i16, v2i32, v2f32],
271 CCAssignToReg<[MM0, MM1, MM2]>>>,
273 // Integer/Float values get stored in stack slots that are 4 bytes in
274 // size and 4-byte aligned.
275 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
277 // Doubles get 8-byte slots that are 4-byte aligned.
278 CCIfType<[f64], CCAssignToStack<8, 4>>,
280 // Long doubles get slots whose size depends on the subtarget.
281 CCIfType<[f80], CCAssignToStack<0, 4>>,
283 // The first 4 SSE vector arguments are passed in XMM registers.
284 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
285 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>>,
287 // Other SSE vectors get 16-byte stack slots that are 16-byte aligned.
288 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
290 // __m64 vectors get 8-byte stack slots that are 4-byte aligned. They are
291 // passed in the parameter area.
292 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 4>>]>;
294 def CC_X86_32_C : CallingConv<[
295 // Promote i8/i16 arguments to i32.
296 CCIfType<[i8, i16], CCPromoteToType<i32>>,
298 // The 'nest' parameter, if any, is passed in ECX.
299 CCIfNest<CCAssignToReg<[ECX]>>,
301 // The first 3 integer arguments, if marked 'inreg' and if the call is not
302 // a vararg call, are passed in integer registers.
303 CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>>>,
305 // Otherwise, same as everything else.
306 CCDelegateTo<CC_X86_32_Common>
309 def CC_X86_32_FastCall : CallingConv<[
310 // Promote i8/i16 arguments to i32.
311 CCIfType<[i8, i16], CCPromoteToType<i32>>,
313 // The 'nest' parameter, if any, is passed in EAX.
314 CCIfNest<CCAssignToReg<[EAX]>>,
316 // The first 2 integer arguments are passed in ECX/EDX
317 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>,
319 // Otherwise, same as everything else.
320 CCDelegateTo<CC_X86_32_Common>
323 def CC_X86_32_FastCC : CallingConv<[
324 // Handles byval parameters. Note that we can't rely on the delegation
325 // to CC_X86_32_Common for this because that happens after code that
326 // puts arguments in registers.
327 CCIfByVal<CCPassByVal<4, 4>>,
329 // Promote i8/i16 arguments to i32.
330 CCIfType<[i8, i16], CCPromoteToType<i32>>,
332 // The 'nest' parameter, if any, is passed in EAX.
333 CCIfNest<CCAssignToReg<[EAX]>>,
335 // The first 2 integer arguments are passed in ECX/EDX
336 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>,
338 // The first 3 float or double arguments, if the call is not a vararg
339 // call and if SSE2 is available, are passed in SSE registers.
340 CCIfNotVarArg<CCIfType<[f32,f64],
341 CCIfSubtarget<"hasSSE2()",
342 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
344 // Doubles get 8-byte slots that are 8-byte aligned.
345 CCIfType<[f64], CCAssignToStack<8, 8>>,
347 // Otherwise, same as everything else.
348 CCDelegateTo<CC_X86_32_Common>