1 //===- X86CallingConv.td - Calling Conventions X86 32/64 ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This describes the calling conventions for the X86-32 and X86-64
13 //===----------------------------------------------------------------------===//
15 /// CCIfSubtarget - Match if the current subtarget has a feature F.
16 class CCIfSubtarget<string F, CCAction A>
17 : CCIf<!strconcat("State.getTarget().getSubtarget<X86Subtarget>().", F), A>;
19 //===----------------------------------------------------------------------===//
20 // Return Value Calling Conventions
21 //===----------------------------------------------------------------------===//
23 // Return-value conventions common to all X86 CC's.
24 def RetCC_X86Common : CallingConv<[
25 // Scalar values are returned in AX first, then DX. For i8, the ABI
26 // requires the values to be in AL and AH, however this code uses AL and DL
27 // instead. This is because using AH for the second register conflicts with
28 // the way LLVM does multiple return values -- a return of {i16,i8} would end
29 // up in AX and AH, which overlap. Front-ends wishing to conform to the ABI
30 // for functions that return two i8 values are currently expected to pack the
31 // values into an i16 (which uses AX, and thus AL:AH).
32 CCIfType<[i8] , CCAssignToReg<[AL, DL]>>,
33 CCIfType<[i16], CCAssignToReg<[AX, DX]>>,
34 CCIfType<[i32], CCAssignToReg<[EAX, EDX]>>,
35 CCIfType<[i64], CCAssignToReg<[RAX, RDX]>>,
37 // Vector types are returned in XMM0 and XMM1, when they fit. XMM2 and XMM3
38 // can only be used by ABI non-compliant code. If the target doesn't have XMM
39 // registers, it won't have vector types.
40 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
41 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,
43 // 256-bit vectors are returned in YMM0 and XMM1, when they fit. YMM2 and YMM3
44 // can only be used by ABI non-compliant code. This vector type is only
45 // supported while using the AVX target feature.
46 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
47 CCIfSubtarget<"hasAVX()", CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>>,
49 // MMX vector types are always returned in MM0. If the target doesn't have
50 // MM0, it doesn't support these vector types.
51 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToReg<[MM0]>>,
53 // Long double types are always returned in ST0 (even with SSE).
54 CCIfType<[f80], CCAssignToReg<[ST0, ST1]>>
57 // X86-32 C return-value convention.
58 def RetCC_X86_32_C : CallingConv<[
59 // The X86-32 calling convention returns FP values in ST0, unless marked
60 // with "inreg" (used here to distinguish one kind of reg from another,
61 // weirdly; this is really the sse-regparm calling convention) in which
62 // case they use XMM0, otherwise it is the same as the common X86 calling
64 CCIfInReg<CCIfSubtarget<"hasSSE2()",
65 CCIfType<[f32, f64], CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
66 CCIfType<[f32,f64], CCAssignToReg<[ST0, ST1]>>,
67 CCDelegateTo<RetCC_X86Common>
70 // X86-32 FastCC return-value convention.
71 def RetCC_X86_32_Fast : CallingConv<[
72 // The X86-32 fastcc returns 1, 2, or 3 FP values in XMM0-2 if the target has
74 // This can happen when a float, 2 x float, or 3 x float vector is split by
75 // target lowering, and is returned in 1-3 sse regs.
76 CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
77 CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
79 // For integers, ECX can be used as an extra return register
80 CCIfType<[i8], CCAssignToReg<[AL, DL, CL]>>,
81 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>,
82 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>,
84 // Otherwise, it is the same as the common X86 calling convention.
85 CCDelegateTo<RetCC_X86Common>
88 // X86-64 C return-value convention.
89 def RetCC_X86_64_C : CallingConv<[
90 // The X86-64 calling convention always returns FP values in XMM0.
91 CCIfType<[f32], CCAssignToReg<[XMM0, XMM1]>>,
92 CCIfType<[f64], CCAssignToReg<[XMM0, XMM1]>>,
94 // MMX vector types are always returned in XMM0 except for v1i64 which is
95 // returned in RAX. This disagrees with ABI documentation but is bug
96 // compatible with gcc.
97 CCIfType<[v1i64], CCAssignToReg<[RAX]>>,
98 CCIfType<[v8i8, v4i16, v2i32], CCAssignToReg<[XMM0, XMM1]>>,
99 CCDelegateTo<RetCC_X86Common>
102 // X86-Win64 C return-value convention.
103 def RetCC_X86_Win64_C : CallingConv<[
104 // The X86-Win64 calling convention always returns __m64 values in RAX.
105 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCBitConvertToType<i64>>,
107 // And FP in XMM0 only.
108 CCIfType<[f32], CCAssignToReg<[XMM0]>>,
109 CCIfType<[f64], CCAssignToReg<[XMM0]>>,
111 // Otherwise, everything is the same as 'normal' X86-64 C CC.
112 CCDelegateTo<RetCC_X86_64_C>
116 // This is the root return-value convention for the X86-32 backend.
117 def RetCC_X86_32 : CallingConv<[
118 // If FastCC, use RetCC_X86_32_Fast.
119 CCIfCC<"CallingConv::Fast", CCDelegateTo<RetCC_X86_32_Fast>>,
120 // Otherwise, use RetCC_X86_32_C.
121 CCDelegateTo<RetCC_X86_32_C>
124 // This is the root return-value convention for the X86-64 backend.
125 def RetCC_X86_64 : CallingConv<[
126 // Mingw64 and native Win64 use Win64 CC
127 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<RetCC_X86_Win64_C>>,
129 // Otherwise, drop to normal X86-64 CC
130 CCDelegateTo<RetCC_X86_64_C>
133 // This is the return-value convention used for the entire X86 backend.
134 def RetCC_X86 : CallingConv<[
135 CCIfSubtarget<"is64Bit()", CCDelegateTo<RetCC_X86_64>>,
136 CCDelegateTo<RetCC_X86_32>
139 //===----------------------------------------------------------------------===//
140 // X86-64 Argument Calling Conventions
141 //===----------------------------------------------------------------------===//
143 def CC_X86_64_C : CallingConv<[
144 // Handles byval parameters.
145 CCIfByVal<CCPassByVal<8, 8>>,
147 // Promote i8/i16 arguments to i32.
148 CCIfType<[i8, i16], CCPromoteToType<i32>>,
150 // The 'nest' parameter, if any, is passed in R10.
151 CCIfNest<CCAssignToReg<[R10]>>,
153 // The first 6 v1i64 vector arguments are passed in GPRs on Darwin.
155 CCIfSubtarget<"isTargetDarwin()",
156 CCBitConvertToType<i64>>>,
158 // The first 6 integer arguments are passed in integer registers.
159 CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D, R9D]>>,
160 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
162 // The first 8 MMX (except for v1i64) vector arguments are passed in XMM
163 // registers on Darwin.
164 CCIfType<[v8i8, v4i16, v2i32],
165 CCIfSubtarget<"isTargetDarwin()",
166 CCIfSubtarget<"hasSSE2()",
167 CCPromoteToType<v2i64>>>>,
169 // The first 8 FP/Vector arguments are passed in XMM registers.
170 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
171 CCIfSubtarget<"hasSSE1()",
172 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>,
174 // The first 8 256-bit vector arguments are passed in YMM registers.
175 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
176 CCIfSubtarget<"hasAVX()",
177 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7]>>>,
179 // Integer/FP values get stored in stack slots that are 8 bytes in size and
180 // 8-byte aligned if there are no more registers to hold them.
181 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
183 // Long doubles get stack slots whose size and alignment depends on the
185 CCIfType<[f80], CCAssignToStack<0, 0>>,
187 // Vectors get 16-byte stack slots that are 16-byte aligned.
188 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
190 // 256-bit vectors get 32-byte stack slots that are 32-byte aligned.
191 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
192 CCAssignToStack<32, 32>>,
194 // __m64 vectors get 8-byte stack slots that are 8-byte aligned.
195 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 8>>
198 // Calling convention used on Win64
199 def CC_X86_Win64_C : CallingConv<[
200 // FIXME: Handle byval stuff.
201 // FIXME: Handle varargs.
203 // Promote i8/i16 arguments to i32.
204 CCIfType<[i8, i16], CCPromoteToType<i32>>,
206 // The 'nest' parameter, if any, is passed in R10.
207 CCIfNest<CCAssignToReg<[R10]>>,
209 // 128 bit vectors are passed by pointer
210 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCPassIndirect<i64>>,
212 // The first 4 MMX vector arguments are passed in GPRs.
213 CCIfType<[v8i8, v4i16, v2i32, v1i64],
214 CCBitConvertToType<i64>>,
216 // The first 4 integer arguments are passed in integer registers.
217 CCIfType<[i32], CCAssignToRegWithShadow<[ECX , EDX , R8D , R9D ],
218 [XMM0, XMM1, XMM2, XMM3]>>,
219 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
220 [XMM0, XMM1, XMM2, XMM3]>>,
222 // The first 4 FP/Vector arguments are passed in XMM registers.
223 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
224 CCAssignToRegWithShadow<[XMM0, XMM1, XMM2, XMM3],
225 [RCX , RDX , R8 , R9 ]>>,
227 // Integer/FP values get stored in stack slots that are 8 bytes in size and
228 // 8-byte aligned if there are no more registers to hold them.
229 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
231 // Long doubles get stack slots whose size and alignment depends on the
233 CCIfType<[f80], CCAssignToStack<0, 0>>,
235 // __m64 vectors get 8-byte stack slots that are 8-byte aligned.
236 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 8>>
239 def CC_X86_64_GHC : CallingConv<[
240 // Promote i8/i16/i32 arguments to i64.
241 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
243 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim
245 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
247 // Pass in STG registers: F1, F2, F3, F4, D1, D2
248 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
249 CCIfSubtarget<"hasSSE1()",
250 CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>
253 //===----------------------------------------------------------------------===//
254 // X86 C Calling Convention
255 //===----------------------------------------------------------------------===//
257 /// CC_X86_32_Common - In all X86-32 calling conventions, extra integers and FP
258 /// values are spilled on the stack, and the first 4 vector values go in XMM
260 def CC_X86_32_Common : CallingConv<[
261 // Handles byval parameters.
262 CCIfByVal<CCPassByVal<4, 4>>,
264 // The first 3 float or double arguments, if marked 'inreg' and if the call
265 // is not a vararg call and if SSE2 is available, are passed in SSE registers.
266 CCIfNotVarArg<CCIfInReg<CCIfType<[f32,f64],
267 CCIfSubtarget<"hasSSE2()",
268 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>>,
270 // The first 3 __m64 (except for v1i64) vector arguments are passed in mmx
271 // registers if the call is not a vararg call.
272 CCIfNotVarArg<CCIfType<[v8i8, v4i16, v2i32],
273 CCAssignToReg<[MM0, MM1, MM2]>>>,
275 // Integer/Float values get stored in stack slots that are 4 bytes in
276 // size and 4-byte aligned.
277 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
279 // Doubles get 8-byte slots that are 4-byte aligned.
280 CCIfType<[f64], CCAssignToStack<8, 4>>,
282 // Long doubles get slots whose size depends on the subtarget.
283 CCIfType<[f80], CCAssignToStack<0, 4>>,
285 // The first 4 SSE vector arguments are passed in XMM registers.
286 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
287 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>>,
289 // The first 4 AVX 256-bit vector arguments are passed in YMM registers.
290 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
291 CCIfSubtarget<"hasAVX()",
292 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>>>,
294 // Other SSE vectors get 16-byte stack slots that are 16-byte aligned.
295 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
297 // 256-bit AVX vectors get 32-byte stack slots that are 32-byte aligned.
298 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
299 CCAssignToStack<32, 32>>,
301 // __m64 vectors get 8-byte stack slots that are 4-byte aligned. They are
302 // passed in the parameter area.
303 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 4>>]>;
305 def CC_X86_32_C : CallingConv<[
306 // Promote i8/i16 arguments to i32.
307 CCIfType<[i8, i16], CCPromoteToType<i32>>,
309 // The 'nest' parameter, if any, is passed in ECX.
310 CCIfNest<CCAssignToReg<[ECX]>>,
312 // The first 3 integer arguments, if marked 'inreg' and if the call is not
313 // a vararg call, are passed in integer registers.
314 CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>>>,
316 // Otherwise, same as everything else.
317 CCDelegateTo<CC_X86_32_Common>
320 def CC_X86_32_FastCall : CallingConv<[
321 // Promote i8/i16 arguments to i32.
322 CCIfType<[i8, i16], CCPromoteToType<i32>>,
324 // The 'nest' parameter, if any, is passed in EAX.
325 CCIfNest<CCAssignToReg<[EAX]>>,
327 // The first 2 integer arguments are passed in ECX/EDX
328 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>,
330 // Otherwise, same as everything else.
331 CCDelegateTo<CC_X86_32_Common>
334 def CC_X86_32_ThisCall : CallingConv<[
335 // Promote i8/i16 arguments to i32.
336 CCIfType<[i8, i16], CCPromoteToType<i32>>,
338 // The 'nest' parameter, if any, is passed in EAX.
339 CCIfNest<CCAssignToReg<[EAX]>>,
341 // The first integer argument is passed in ECX
342 CCIfType<[i32], CCAssignToReg<[ECX]>>,
344 // Otherwise, same as everything else.
345 CCDelegateTo<CC_X86_32_Common>
348 def CC_X86_32_FastCC : CallingConv<[
349 // Handles byval parameters. Note that we can't rely on the delegation
350 // to CC_X86_32_Common for this because that happens after code that
351 // puts arguments in registers.
352 CCIfByVal<CCPassByVal<4, 4>>,
354 // Promote i8/i16 arguments to i32.
355 CCIfType<[i8, i16], CCPromoteToType<i32>>,
357 // The 'nest' parameter, if any, is passed in EAX.
358 CCIfNest<CCAssignToReg<[EAX]>>,
360 // The first 2 integer arguments are passed in ECX/EDX
361 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>,
363 // The first 3 float or double arguments, if the call is not a vararg
364 // call and if SSE2 is available, are passed in SSE registers.
365 CCIfNotVarArg<CCIfType<[f32,f64],
366 CCIfSubtarget<"hasSSE2()",
367 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
369 // Doubles get 8-byte slots that are 8-byte aligned.
370 CCIfType<[f64], CCAssignToStack<8, 8>>,
372 // Otherwise, same as everything else.
373 CCDelegateTo<CC_X86_32_Common>
376 def CC_X86_32_GHC : CallingConv<[
377 // Promote i8/i16 arguments to i32.
378 CCIfType<[i8, i16], CCPromoteToType<i32>>,
380 // Pass in STG registers: Base, Sp, Hp, R1
381 CCIfType<[i32], CCAssignToReg<[EBX, EBP, EDI, ESI]>>