1 //===-- X86CallingConv.td - Calling Conventions X86 32/64 --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This describes the calling conventions for the X86-32 and X86-64
13 //===----------------------------------------------------------------------===//
15 /// CCIfSubtarget - Match if the current subtarget has a feature F.
16 class CCIfSubtarget<string F, CCAction A>
17 : CCIf<!strconcat("static_cast<const X86Subtarget&>"
18 "(State.getMachineFunction().getSubtarget()).", F),
21 //===----------------------------------------------------------------------===//
22 // Return Value Calling Conventions
23 //===----------------------------------------------------------------------===//
25 // Return-value conventions common to all X86 CC's.
26 def RetCC_X86Common : CallingConv<[
27 // Scalar values are returned in AX first, then DX. For i8, the ABI
28 // requires the values to be in AL and AH, however this code uses AL and DL
29 // instead. This is because using AH for the second register conflicts with
30 // the way LLVM does multiple return values -- a return of {i16,i8} would end
31 // up in AX and AH, which overlap. Front-ends wishing to conform to the ABI
32 // for functions that return two i8 values are currently expected to pack the
33 // values into an i16 (which uses AX, and thus AL:AH).
35 // For code that doesn't care about the ABI, we allow returning more than two
36 // integer values in registers.
37 CCIfType<[i1], CCPromoteToType<i8>>,
38 CCIfType<[i8] , CCAssignToReg<[AL, DL, CL]>>,
39 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>,
40 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>,
41 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX]>>,
43 // Boolean vectors of AVX-512 are returned in SIMD registers.
44 // The call from AVX to AVX-512 function should work,
45 // since the boolean types in AVX/AVX2 are promoted by default.
46 CCIfType<[v2i1], CCPromoteToType<v2i64>>,
47 CCIfType<[v4i1], CCPromoteToType<v4i32>>,
48 CCIfType<[v8i1], CCPromoteToType<v8i16>>,
49 CCIfType<[v16i1], CCPromoteToType<v16i8>>,
50 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
51 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
53 // Vector types are returned in XMM0 and XMM1, when they fit. XMM2 and XMM3
54 // can only be used by ABI non-compliant code. If the target doesn't have XMM
55 // registers, it won't have vector types.
56 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
57 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,
59 // 256-bit vectors are returned in YMM0 and XMM1, when they fit. YMM2 and YMM3
60 // can only be used by ABI non-compliant code. This vector type is only
61 // supported while using the AVX target feature.
62 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
63 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>,
65 // 512-bit vectors are returned in ZMM0 and ZMM1, when they fit. ZMM2 and ZMM3
66 // can only be used by ABI non-compliant code. This vector type is only
67 // supported while using the AVX-512 target feature.
68 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
69 CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>,
71 // MMX vector types are always returned in MM0. If the target doesn't have
72 // MM0, it doesn't support these vector types.
73 CCIfType<[x86mmx], CCAssignToReg<[MM0]>>,
75 // Long double types are always returned in FP0 (even with SSE).
76 CCIfType<[f80], CCAssignToReg<[FP0, FP1]>>
79 // X86-32 C return-value convention.
80 def RetCC_X86_32_C : CallingConv<[
81 // The X86-32 calling convention returns FP values in FP0, unless marked
82 // with "inreg" (used here to distinguish one kind of reg from another,
83 // weirdly; this is really the sse-regparm calling convention) in which
84 // case they use XMM0, otherwise it is the same as the common X86 calling
86 CCIfInReg<CCIfSubtarget<"hasSSE2()",
87 CCIfType<[f32, f64], CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
88 CCIfType<[f32,f64], CCAssignToReg<[FP0, FP1]>>,
89 CCDelegateTo<RetCC_X86Common>
92 // X86-32 FastCC return-value convention.
93 def RetCC_X86_32_Fast : CallingConv<[
94 // The X86-32 fastcc returns 1, 2, or 3 FP values in XMM0-2 if the target has
96 // This can happen when a float, 2 x float, or 3 x float vector is split by
97 // target lowering, and is returned in 1-3 sse regs.
98 CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
99 CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
101 // For integers, ECX can be used as an extra return register
102 CCIfType<[i8], CCAssignToReg<[AL, DL, CL]>>,
103 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>,
104 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>,
106 // Otherwise, it is the same as the common X86 calling convention.
107 CCDelegateTo<RetCC_X86Common>
110 // Intel_OCL_BI return-value convention.
111 def RetCC_Intel_OCL_BI : CallingConv<[
112 // Vector types are returned in XMM0,XMM1,XMMM2 and XMM3.
113 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64],
114 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,
116 // 256-bit FP vectors
117 // No more than 4 registers
118 CCIfType<[v8f32, v4f64, v8i32, v4i64],
119 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>,
121 // 512-bit FP vectors
122 CCIfType<[v16f32, v8f64, v16i32, v8i64],
123 CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>,
125 // i32, i64 in the standard way
126 CCDelegateTo<RetCC_X86Common>
129 // X86-32 HiPE return-value convention.
130 def RetCC_X86_32_HiPE : CallingConv<[
131 // Promote all types to i32
132 CCIfType<[i8, i16], CCPromoteToType<i32>>,
134 // Return: HP, P, VAL1, VAL2
135 CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX]>>
138 // X86-32 HiPE return-value convention.
139 def RetCC_X86_32_VectorCall : CallingConv<[
140 // Vector types are returned in XMM0,XMM1,XMMM2 and XMM3.
141 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
142 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,
144 // 256-bit FP vectors
145 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
146 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>,
148 // 512-bit FP vectors
149 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
150 CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>,
152 // Return integers in the standard way.
153 CCDelegateTo<RetCC_X86Common>
156 // X86-64 C return-value convention.
157 def RetCC_X86_64_C : CallingConv<[
158 // The X86-64 calling convention always returns FP values in XMM0.
159 CCIfType<[f32], CCAssignToReg<[XMM0, XMM1]>>,
160 CCIfType<[f64], CCAssignToReg<[XMM0, XMM1]>>,
161 CCIfType<[f128], CCAssignToReg<[XMM0, XMM1]>>,
163 // MMX vector types are always returned in XMM0.
164 CCIfType<[x86mmx], CCAssignToReg<[XMM0, XMM1]>>,
165 CCDelegateTo<RetCC_X86Common>
168 // X86-Win64 C return-value convention.
169 def RetCC_X86_Win64_C : CallingConv<[
170 // The X86-Win64 calling convention always returns __m64 values in RAX.
171 CCIfType<[x86mmx], CCBitConvertToType<i64>>,
173 // Otherwise, everything is the same as 'normal' X86-64 C CC.
174 CCDelegateTo<RetCC_X86_64_C>
177 // X86-64 HiPE return-value convention.
178 def RetCC_X86_64_HiPE : CallingConv<[
179 // Promote all types to i64
180 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
182 // Return: HP, P, VAL1, VAL2
183 CCIfType<[i64], CCAssignToReg<[R15, RBP, RAX, RDX]>>
186 // X86-64 WebKit_JS return-value convention.
187 def RetCC_X86_64_WebKit_JS : CallingConv<[
188 // Promote all types to i64
189 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
192 CCIfType<[i64], CCAssignToReg<[RAX]>>
195 // X86-64 AnyReg return-value convention. No explicit register is specified for
196 // the return-value. The register allocator is allowed and expected to choose
197 // any free register.
199 // This calling convention is currently only supported by the stackmap and
200 // patchpoint intrinsics. All other uses will result in an assert on Debug
201 // builds. On Release builds we fallback to the X86 C calling convention.
202 def RetCC_X86_64_AnyReg : CallingConv<[
203 CCCustom<"CC_X86_AnyReg_Error">
206 // X86-64 HHVM return-value convention.
207 def RetCC_X86_64_HHVM: CallingConv<[
208 // Promote all types to i64
209 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
211 // Return: could return in any GP register save RSP and R12.
212 CCIfType<[i64], CCAssignToReg<[RBX, RBP, RDI, RSI, RDX, RCX, R8, R9,
213 RAX, R10, R11, R13, R14, R15]>>
216 // This is the root return-value convention for the X86-32 backend.
217 def RetCC_X86_32 : CallingConv<[
218 // If FastCC, use RetCC_X86_32_Fast.
219 CCIfCC<"CallingConv::Fast", CCDelegateTo<RetCC_X86_32_Fast>>,
220 // If HiPE, use RetCC_X86_32_HiPE.
221 CCIfCC<"CallingConv::HiPE", CCDelegateTo<RetCC_X86_32_HiPE>>,
222 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<RetCC_X86_32_VectorCall>>,
224 // Otherwise, use RetCC_X86_32_C.
225 CCDelegateTo<RetCC_X86_32_C>
228 // This is the root return-value convention for the X86-64 backend.
229 def RetCC_X86_64 : CallingConv<[
230 // HiPE uses RetCC_X86_64_HiPE
231 CCIfCC<"CallingConv::HiPE", CCDelegateTo<RetCC_X86_64_HiPE>>,
233 // Handle JavaScript calls.
234 CCIfCC<"CallingConv::WebKit_JS", CCDelegateTo<RetCC_X86_64_WebKit_JS>>,
235 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<RetCC_X86_64_AnyReg>>,
237 // Handle explicit CC selection
238 CCIfCC<"CallingConv::X86_64_Win64", CCDelegateTo<RetCC_X86_Win64_C>>,
239 CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo<RetCC_X86_64_C>>,
241 // Handle HHVM calls.
242 CCIfCC<"CallingConv::HHVM", CCDelegateTo<RetCC_X86_64_HHVM>>,
244 // Mingw64 and native Win64 use Win64 CC
245 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<RetCC_X86_Win64_C>>,
247 // Otherwise, drop to normal X86-64 CC
248 CCDelegateTo<RetCC_X86_64_C>
251 // This is the return-value convention used for the entire X86 backend.
252 def RetCC_X86 : CallingConv<[
254 // Check if this is the Intel OpenCL built-ins calling convention
255 CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo<RetCC_Intel_OCL_BI>>,
257 CCIfSubtarget<"is64Bit()", CCDelegateTo<RetCC_X86_64>>,
258 CCDelegateTo<RetCC_X86_32>
261 //===----------------------------------------------------------------------===//
262 // X86-64 Argument Calling Conventions
263 //===----------------------------------------------------------------------===//
265 def CC_X86_64_C : CallingConv<[
266 // Handles byval parameters.
267 CCIfByVal<CCPassByVal<8, 8>>,
269 // Promote i1/i8/i16 arguments to i32.
270 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
272 // The 'nest' parameter, if any, is passed in R10.
273 CCIfNest<CCIfSubtarget<"isTarget64BitILP32()", CCAssignToReg<[R10D]>>>,
274 CCIfNest<CCAssignToReg<[R10]>>,
276 // The first 6 integer arguments are passed in integer registers.
277 CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D, R9D]>>,
278 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
280 // The first 8 MMX vector arguments are passed in XMM registers on Darwin.
282 CCIfSubtarget<"isTargetDarwin()",
283 CCIfSubtarget<"hasSSE2()",
284 CCPromoteToType<v2i64>>>>,
286 // Boolean vectors of AVX-512 are passed in SIMD registers.
287 // The call from AVX to AVX-512 function should work,
288 // since the boolean types in AVX/AVX2 are promoted by default.
289 CCIfType<[v2i1], CCPromoteToType<v2i64>>,
290 CCIfType<[v4i1], CCPromoteToType<v4i32>>,
291 CCIfType<[v8i1], CCPromoteToType<v8i16>>,
292 CCIfType<[v16i1], CCPromoteToType<v16i8>>,
293 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
294 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
296 // The first 8 FP/Vector arguments are passed in XMM registers.
297 CCIfType<[f32, f64, f128, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
298 CCIfSubtarget<"hasSSE1()",
299 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>,
301 // The first 8 256-bit vector arguments are passed in YMM registers, unless
302 // this is a vararg function.
303 // FIXME: This isn't precisely correct; the x86-64 ABI document says that
304 // fixed arguments to vararg functions are supposed to be passed in
305 // registers. Actually modeling that would be a lot of work, though.
306 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
307 CCIfSubtarget<"hasFp256()",
308 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3,
309 YMM4, YMM5, YMM6, YMM7]>>>>,
311 // The first 8 512-bit vector arguments are passed in ZMM registers.
312 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
313 CCIfSubtarget<"hasAVX512()",
314 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7]>>>>,
316 // Integer/FP values get stored in stack slots that are 8 bytes in size and
317 // 8-byte aligned if there are no more registers to hold them.
318 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
320 // Long doubles get stack slots whose size and alignment depends on the
322 CCIfType<[f80, f128], CCAssignToStack<0, 0>>,
324 // Vectors get 16-byte stack slots that are 16-byte aligned.
325 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
327 // 256-bit vectors get 32-byte stack slots that are 32-byte aligned.
328 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
329 CCAssignToStack<32, 32>>,
331 // 512-bit vectors get 64-byte stack slots that are 64-byte aligned.
332 CCIfType<[v16i32, v8i64, v16f32, v8f64],
333 CCAssignToStack<64, 64>>
336 // Calling convention for X86-64 HHVM.
337 def CC_X86_64_HHVM : CallingConv<[
338 // Use all/any GP registers for args, except RSP.
339 CCIfType<[i64], CCAssignToReg<[RBX, R12, RBP, R15,
340 RDI, RSI, RDX, RCX, R8, R9,
341 RAX, R10, R11, R13, R14]>>
344 // Calling convention for helper functions in HHVM.
345 def CC_X86_64_HHVM_C : CallingConv<[
346 // Pass the first argument in RBP.
347 CCIfType<[i64], CCAssignToReg<[RBP]>>,
349 // Otherwise it's the same as the regular C calling convention.
350 CCDelegateTo<CC_X86_64_C>
353 // Calling convention used on Win64
354 def CC_X86_Win64_C : CallingConv<[
355 // FIXME: Handle byval stuff.
356 // FIXME: Handle varargs.
358 // Promote i1/i8/i16 arguments to i32.
359 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
361 // The 'nest' parameter, if any, is passed in R10.
362 CCIfNest<CCAssignToReg<[R10]>>,
364 // 128 bit vectors are passed by pointer
365 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCPassIndirect<i64>>,
368 // 256 bit vectors are passed by pointer
369 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>,
371 // 512 bit vectors are passed by pointer
372 CCIfType<[v16i32, v16f32, v8f64, v8i64], CCPassIndirect<i64>>,
374 // The first 4 MMX vector arguments are passed in GPRs.
375 CCIfType<[x86mmx], CCBitConvertToType<i64>>,
377 // The first 4 integer arguments are passed in integer registers.
378 CCIfType<[i32], CCAssignToRegWithShadow<[ECX , EDX , R8D , R9D ],
379 [XMM0, XMM1, XMM2, XMM3]>>,
381 // Do not pass the sret argument in RCX, the Win64 thiscall calling
382 // convention requires "this" to be passed in RCX.
383 CCIfCC<"CallingConv::X86_ThisCall",
384 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[RDX , R8 , R9 ],
385 [XMM1, XMM2, XMM3]>>>>,
387 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
388 [XMM0, XMM1, XMM2, XMM3]>>,
390 // The first 4 FP/Vector arguments are passed in XMM registers.
391 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
392 CCAssignToRegWithShadow<[XMM0, XMM1, XMM2, XMM3],
393 [RCX , RDX , R8 , R9 ]>>,
395 // Integer/FP values get stored in stack slots that are 8 bytes in size and
396 // 8-byte aligned if there are no more registers to hold them.
397 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
399 // Long doubles get stack slots whose size and alignment depends on the
401 CCIfType<[f80], CCAssignToStack<0, 0>>
404 def CC_X86_Win64_VectorCall : CallingConv<[
405 // The first 6 floating point and vector types of 128 bits or less use
407 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
408 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5]>>,
410 // 256-bit vectors use YMM registers.
411 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
412 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3, YMM4, YMM5]>>,
414 // 512-bit vectors use ZMM registers.
415 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
416 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5]>>,
418 // Delegate to fastcall to handle integer types.
419 CCDelegateTo<CC_X86_Win64_C>
423 def CC_X86_64_GHC : CallingConv<[
424 // Promote i8/i16/i32 arguments to i64.
425 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
427 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim
429 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
431 // Pass in STG registers: F1, F2, F3, F4, D1, D2
432 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
433 CCIfSubtarget<"hasSSE1()",
434 CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>
437 def CC_X86_64_HiPE : CallingConv<[
438 // Promote i8/i16/i32 arguments to i64.
439 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
441 // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2, ARG3
442 CCIfType<[i64], CCAssignToReg<[R15, RBP, RSI, RDX, RCX, R8]>>,
444 // Integer/FP values get stored in stack slots that are 8 bytes in size and
445 // 8-byte aligned if there are no more registers to hold them.
446 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>
449 def CC_X86_64_WebKit_JS : CallingConv<[
450 // Promote i8/i16 arguments to i32.
451 CCIfType<[i8, i16], CCPromoteToType<i32>>,
453 // Only the first integer argument is passed in register.
454 CCIfType<[i32], CCAssignToReg<[EAX]>>,
455 CCIfType<[i64], CCAssignToReg<[RAX]>>,
457 // The remaining integer arguments are passed on the stack. 32bit integer and
458 // floating-point arguments are aligned to 4 byte and stored in 4 byte slots.
459 // 64bit integer and floating-point arguments are aligned to 8 byte and stored
460 // in 8 byte stack slots.
461 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
462 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
465 // No explicit register is specified for the AnyReg calling convention. The
466 // register allocator may assign the arguments to any free register.
468 // This calling convention is currently only supported by the stackmap and
469 // patchpoint intrinsics. All other uses will result in an assert on Debug
470 // builds. On Release builds we fallback to the X86 C calling convention.
471 def CC_X86_64_AnyReg : CallingConv<[
472 CCCustom<"CC_X86_AnyReg_Error">
475 //===----------------------------------------------------------------------===//
476 // X86 C Calling Convention
477 //===----------------------------------------------------------------------===//
479 /// CC_X86_32_Vector_Common - In all X86-32 calling conventions, extra vector
480 /// values are spilled on the stack.
481 def CC_X86_32_Vector_Common : CallingConv<[
482 // Other SSE vectors get 16-byte stack slots that are 16-byte aligned.
483 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
485 // 256-bit AVX vectors get 32-byte stack slots that are 32-byte aligned.
486 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
487 CCAssignToStack<32, 32>>,
489 // 512-bit AVX 512-bit vectors get 64-byte stack slots that are 64-byte aligned.
490 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
491 CCAssignToStack<64, 64>>
494 // CC_X86_32_Vector_Standard - The first 3 vector arguments are passed in
496 def CC_X86_32_Vector_Standard : CallingConv<[
497 // SSE vector arguments are passed in XMM registers.
498 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
499 CCAssignToReg<[XMM0, XMM1, XMM2]>>>,
501 // AVX 256-bit vector arguments are passed in YMM registers.
502 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
503 CCIfSubtarget<"hasFp256()",
504 CCAssignToReg<[YMM0, YMM1, YMM2]>>>>,
506 // AVX 512-bit vector arguments are passed in ZMM registers.
507 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
508 CCAssignToReg<[ZMM0, ZMM1, ZMM2]>>>,
510 CCDelegateTo<CC_X86_32_Vector_Common>
513 // CC_X86_32_Vector_Darwin - The first 4 vector arguments are passed in
515 def CC_X86_32_Vector_Darwin : CallingConv<[
516 // SSE vector arguments are passed in XMM registers.
517 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
518 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>>,
520 // AVX 256-bit vector arguments are passed in YMM registers.
521 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
522 CCIfSubtarget<"hasFp256()",
523 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>>>,
525 // AVX 512-bit vector arguments are passed in ZMM registers.
526 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
527 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3]>>>,
529 CCDelegateTo<CC_X86_32_Vector_Common>
532 /// CC_X86_32_Common - In all X86-32 calling conventions, extra integers and FP
533 /// values are spilled on the stack.
534 def CC_X86_32_Common : CallingConv<[
535 // Handles byval parameters.
536 CCIfByVal<CCPassByVal<4, 4>>,
538 // The first 3 float or double arguments, if marked 'inreg' and if the call
539 // is not a vararg call and if SSE2 is available, are passed in SSE registers.
540 CCIfNotVarArg<CCIfInReg<CCIfType<[f32,f64],
541 CCIfSubtarget<"hasSSE2()",
542 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>>,
544 // The first 3 __m64 vector arguments are passed in mmx registers if the
545 // call is not a vararg call.
546 CCIfNotVarArg<CCIfType<[x86mmx],
547 CCAssignToReg<[MM0, MM1, MM2]>>>,
549 // Integer/Float values get stored in stack slots that are 4 bytes in
550 // size and 4-byte aligned.
551 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
553 // Doubles get 8-byte slots that are 4-byte aligned.
554 CCIfType<[f64], CCAssignToStack<8, 4>>,
556 // Long doubles get slots whose size depends on the subtarget.
557 CCIfType<[f80], CCAssignToStack<0, 4>>,
559 // Boolean vectors of AVX-512 are passed in SIMD registers.
560 // The call from AVX to AVX-512 function should work,
561 // since the boolean types in AVX/AVX2 are promoted by default.
562 CCIfType<[v2i1], CCPromoteToType<v2i64>>,
563 CCIfType<[v4i1], CCPromoteToType<v4i32>>,
564 CCIfType<[v8i1], CCPromoteToType<v8i16>>,
565 CCIfType<[v16i1], CCPromoteToType<v16i8>>,
566 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
567 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
569 // __m64 vectors get 8-byte stack slots that are 4-byte aligned. They are
570 // passed in the parameter area.
571 CCIfType<[x86mmx], CCAssignToStack<8, 4>>,
573 // Darwin passes vectors in a form that differs from the i386 psABI
574 CCIfSubtarget<"isTargetDarwin()", CCDelegateTo<CC_X86_32_Vector_Darwin>>,
576 // Otherwise, drop to 'normal' X86-32 CC
577 CCDelegateTo<CC_X86_32_Vector_Standard>
580 def CC_X86_32_C : CallingConv<[
581 // Promote i1/i8/i16 arguments to i32.
582 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
584 // The 'nest' parameter, if any, is passed in ECX.
585 CCIfNest<CCAssignToReg<[ECX]>>,
587 // The first 3 integer arguments, if marked 'inreg' and if the call is not
588 // a vararg call, are passed in integer registers.
589 CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>>>,
591 // Otherwise, same as everything else.
592 CCDelegateTo<CC_X86_32_Common>
595 def CC_X86_32_MCU : CallingConv<[
596 // Handles byval parameters. Note that, like FastCC, we can't rely on
597 // the delegation to CC_X86_32_Common because that happens after code that
598 // puts arguments in registers.
599 CCIfByVal<CCPassByVal<4, 4>>,
601 // Promote i1/i8/i16 arguments to i32.
602 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
604 // If the call is not a vararg call, some arguments may be passed
605 // in integer registers.
606 CCIfNotVarArg<CCIfType<[i32], CCCustom<"CC_X86_32_MCUInReg">>>,
608 // Otherwise, same as everything else.
609 CCDelegateTo<CC_X86_32_Common>
612 def CC_X86_32_FastCall : CallingConv<[
613 // Promote i1/i8/i16 arguments to i32.
614 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
616 // The 'nest' parameter, if any, is passed in EAX.
617 CCIfNest<CCAssignToReg<[EAX]>>,
619 // The first 2 integer arguments are passed in ECX/EDX
620 CCIfInReg<CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>>,
622 // Otherwise, same as everything else.
623 CCDelegateTo<CC_X86_32_Common>
626 def CC_X86_32_VectorCall : CallingConv<[
627 // The first 6 floating point and vector types of 128 bits or less use
629 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
630 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5]>>,
632 // 256-bit vectors use YMM registers.
633 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
634 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3, YMM4, YMM5]>>,
636 // 512-bit vectors use ZMM registers.
637 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
638 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5]>>,
640 // Otherwise, pass it indirectly.
641 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64,
642 v32i8, v16i16, v8i32, v4i64, v8f32, v4f64,
643 v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
644 CCCustom<"CC_X86_32_VectorCallIndirect">>,
646 // Delegate to fastcall to handle integer types.
647 CCDelegateTo<CC_X86_32_FastCall>
650 def CC_X86_32_ThisCall_Common : CallingConv<[
651 // The first integer argument is passed in ECX
652 CCIfType<[i32], CCAssignToReg<[ECX]>>,
654 // Otherwise, same as everything else.
655 CCDelegateTo<CC_X86_32_Common>
658 def CC_X86_32_ThisCall_Mingw : CallingConv<[
659 // Promote i1/i8/i16 arguments to i32.
660 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
662 CCDelegateTo<CC_X86_32_ThisCall_Common>
665 def CC_X86_32_ThisCall_Win : CallingConv<[
666 // Promote i1/i8/i16 arguments to i32.
667 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
669 // Pass sret arguments indirectly through stack.
670 CCIfSRet<CCAssignToStack<4, 4>>,
672 CCDelegateTo<CC_X86_32_ThisCall_Common>
675 def CC_X86_32_ThisCall : CallingConv<[
676 CCIfSubtarget<"isTargetCygMing()", CCDelegateTo<CC_X86_32_ThisCall_Mingw>>,
677 CCDelegateTo<CC_X86_32_ThisCall_Win>
680 def CC_X86_32_FastCC : CallingConv<[
681 // Handles byval parameters. Note that we can't rely on the delegation
682 // to CC_X86_32_Common for this because that happens after code that
683 // puts arguments in registers.
684 CCIfByVal<CCPassByVal<4, 4>>,
686 // Promote i1/i8/i16 arguments to i32.
687 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
689 // The 'nest' parameter, if any, is passed in EAX.
690 CCIfNest<CCAssignToReg<[EAX]>>,
692 // The first 2 integer arguments are passed in ECX/EDX
693 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>,
695 // The first 3 float or double arguments, if the call is not a vararg
696 // call and if SSE2 is available, are passed in SSE registers.
697 CCIfNotVarArg<CCIfType<[f32,f64],
698 CCIfSubtarget<"hasSSE2()",
699 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
701 // Doubles get 8-byte slots that are 8-byte aligned.
702 CCIfType<[f64], CCAssignToStack<8, 8>>,
704 // Otherwise, same as everything else.
705 CCDelegateTo<CC_X86_32_Common>
708 def CC_X86_32_GHC : CallingConv<[
709 // Promote i8/i16 arguments to i32.
710 CCIfType<[i8, i16], CCPromoteToType<i32>>,
712 // Pass in STG registers: Base, Sp, Hp, R1
713 CCIfType<[i32], CCAssignToReg<[EBX, EBP, EDI, ESI]>>
716 def CC_X86_32_HiPE : CallingConv<[
717 // Promote i8/i16 arguments to i32.
718 CCIfType<[i8, i16], CCPromoteToType<i32>>,
720 // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2
721 CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX, ECX]>>,
723 // Integer/Float values get stored in stack slots that are 4 bytes in
724 // size and 4-byte aligned.
725 CCIfType<[i32, f32], CCAssignToStack<4, 4>>
728 // X86-64 Intel OpenCL built-ins calling convention.
729 def CC_Intel_OCL_BI : CallingConv<[
731 CCIfType<[i32], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[ECX, EDX, R8D, R9D]>>>,
732 CCIfType<[i64], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[RCX, RDX, R8, R9 ]>>>,
734 CCIfType<[i32], CCIfSubtarget<"is64Bit()", CCAssignToReg<[EDI, ESI, EDX, ECX]>>>,
735 CCIfType<[i64], CCIfSubtarget<"is64Bit()", CCAssignToReg<[RDI, RSI, RDX, RCX]>>>,
737 CCIfType<[i32], CCAssignToStack<4, 4>>,
739 // The SSE vector arguments are passed in XMM registers.
740 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64],
741 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>,
743 // The 256-bit vector arguments are passed in YMM registers.
744 CCIfType<[v8f32, v4f64, v8i32, v4i64],
745 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>,
747 // The 512-bit vector arguments are passed in ZMM registers.
748 CCIfType<[v16f32, v8f64, v16i32, v8i64],
749 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3]>>,
751 // Pass masks in mask registers
752 CCIfType<[v16i1, v8i1], CCAssignToReg<[K1]>>,
754 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>,
755 CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64_C>>,
756 CCDelegateTo<CC_X86_32_C>
759 def CC_X86_32_Intr : CallingConv<[
760 CCAssignToStack<4, 4>
763 def CC_X86_64_Intr : CallingConv<[
764 CCAssignToStack<8, 8>
767 //===----------------------------------------------------------------------===//
768 // X86 Root Argument Calling Conventions
769 //===----------------------------------------------------------------------===//
771 // This is the root argument convention for the X86-32 backend.
772 def CC_X86_32 : CallingConv<[
773 CCIfSubtarget<"isTargetMCU()", CCDelegateTo<CC_X86_32_MCU>>,
774 CCIfCC<"CallingConv::X86_FastCall", CCDelegateTo<CC_X86_32_FastCall>>,
775 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<CC_X86_32_VectorCall>>,
776 CCIfCC<"CallingConv::X86_ThisCall", CCDelegateTo<CC_X86_32_ThisCall>>,
777 CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_X86_32_FastCC>>,
778 CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_32_GHC>>,
779 CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_32_HiPE>>,
780 CCIfCC<"CallingConv::X86_INTR", CCDelegateTo<CC_X86_32_Intr>>,
782 // Otherwise, drop to normal X86-32 CC
783 CCDelegateTo<CC_X86_32_C>
786 // This is the root argument convention for the X86-64 backend.
787 def CC_X86_64 : CallingConv<[
788 CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_64_GHC>>,
789 CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_64_HiPE>>,
790 CCIfCC<"CallingConv::WebKit_JS", CCDelegateTo<CC_X86_64_WebKit_JS>>,
791 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<CC_X86_64_AnyReg>>,
792 CCIfCC<"CallingConv::X86_64_Win64", CCDelegateTo<CC_X86_Win64_C>>,
793 CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo<CC_X86_64_C>>,
794 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<CC_X86_Win64_VectorCall>>,
795 CCIfCC<"CallingConv::HHVM", CCDelegateTo<CC_X86_64_HHVM>>,
796 CCIfCC<"CallingConv::HHVM_C", CCDelegateTo<CC_X86_64_HHVM_C>>,
797 CCIfCC<"CallingConv::X86_INTR", CCDelegateTo<CC_X86_64_Intr>>,
799 // Mingw64 and native Win64 use Win64 CC
800 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>,
802 // Otherwise, drop to normal X86-64 CC
803 CCDelegateTo<CC_X86_64_C>
806 // This is the argument convention used for the entire X86 backend.
807 def CC_X86 : CallingConv<[
808 CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo<CC_Intel_OCL_BI>>,
809 CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64>>,
810 CCDelegateTo<CC_X86_32>
813 //===----------------------------------------------------------------------===//
814 // Callee-saved Registers.
815 //===----------------------------------------------------------------------===//
817 def CSR_NoRegs : CalleeSavedRegs<(add)>;
819 def CSR_32 : CalleeSavedRegs<(add ESI, EDI, EBX, EBP)>;
820 def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>;
822 def CSR_32EHRet : CalleeSavedRegs<(add EAX, EDX, CSR_32)>;
823 def CSR_64EHRet : CalleeSavedRegs<(add RAX, RDX, CSR_64)>;
825 def CSR_Win64 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15,
826 (sequence "XMM%u", 6, 15))>;
828 // The function used by Darwin to obtain the address of a thread-local variable
829 // uses rdi to pass a single parameter and rax for the return value. All other
830 // GPRs are preserved.
831 def CSR_64_TLS_Darwin : CalleeSavedRegs<(add CSR_64, RCX, RDX, RSI,
834 // CSRs that are handled by prologue, epilogue.
835 def CSR_64_CXX_TLS_Darwin_PE : CalleeSavedRegs<(add RBP)>;
837 // CSRs that are handled explicitly via copies.
838 def CSR_64_CXX_TLS_Darwin_ViaCopy : CalleeSavedRegs<(sub CSR_64_TLS_Darwin, RBP)>;
840 // All GPRs - except r11
841 def CSR_64_RT_MostRegs : CalleeSavedRegs<(add CSR_64, RAX, RCX, RDX, RSI, RDI,
844 // All registers - except r11
845 def CSR_64_RT_AllRegs : CalleeSavedRegs<(add CSR_64_RT_MostRegs,
846 (sequence "XMM%u", 0, 15))>;
847 def CSR_64_RT_AllRegs_AVX : CalleeSavedRegs<(add CSR_64_RT_MostRegs,
848 (sequence "YMM%u", 0, 15))>;
850 def CSR_64_MostRegs : CalleeSavedRegs<(add RBX, RCX, RDX, RSI, RDI, R8, R9, R10,
851 R11, R12, R13, R14, R15, RBP,
852 (sequence "XMM%u", 0, 15))>;
854 def CSR_32_AllRegs : CalleeSavedRegs<(add EAX, EBX, ECX, EDX, EBP, ESI,
856 def CSR_32_AllRegs_SSE : CalleeSavedRegs<(add CSR_32_AllRegs,
857 (sequence "XMM%u", 0, 7))>;
859 def CSR_64_AllRegs : CalleeSavedRegs<(add CSR_64_MostRegs, RAX, RSP,
860 (sequence "XMM%u", 16, 31))>;
861 def CSR_64_AllRegs_AVX : CalleeSavedRegs<(sub (add CSR_64_MostRegs, RAX, RSP,
862 (sequence "YMM%u", 0, 31)),
863 (sequence "XMM%u", 0, 15))>;
865 // Standard C + YMM6-15
866 def CSR_Win64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12,
868 (sequence "YMM%u", 6, 15))>;
870 def CSR_Win64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI,
872 (sequence "ZMM%u", 6, 21),
874 //Standard C + XMM 8-15
875 def CSR_64_Intel_OCL_BI : CalleeSavedRegs<(add CSR_64,
876 (sequence "XMM%u", 8, 15))>;
878 //Standard C + YMM 8-15
879 def CSR_64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add CSR_64,
880 (sequence "YMM%u", 8, 15))>;
882 def CSR_64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RDI, RSI, R14, R15,
883 (sequence "ZMM%u", 16, 31),
886 // Only R12 is preserved for PHP calls in HHVM.
887 def CSR_64_HHVM : CalleeSavedRegs<(add R12)>;