1 //===- X86CallingConv.td - Calling Conventions X86 32/64 ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This describes the calling conventions for the X86-32 and X86-64
13 //===----------------------------------------------------------------------===//
15 /// CCIfSubtarget - Match if the current subtarget has a feature F.
16 class CCIfSubtarget<string F, CCAction A>
17 : CCIf<!strconcat("State.getTarget().getSubtarget<X86Subtarget>().", F), A>;
19 //===----------------------------------------------------------------------===//
20 // Return Value Calling Conventions
21 //===----------------------------------------------------------------------===//
23 // Return-value conventions common to all X86 CC's.
24 def RetCC_X86Common : CallingConv<[
25 // Scalar values are returned in AX first, then DX. For i8, the ABI
26 // requires the values to be in AL and AH, however this code uses AL and DL
27 // instead. This is because using AH for the second register conflicts with
28 // the way LLVM does multiple return values -- a return of {i16,i8} would end
29 // up in AX and AH, which overlap. Front-ends wishing to conform to the ABI
30 // for functions that return two i8 values are currently expected to pack the
31 // values into an i16 (which uses AX, and thus AL:AH).
32 CCIfType<[i8] , CCAssignToReg<[AL, DL]>>,
33 CCIfType<[i16], CCAssignToReg<[AX, DX]>>,
34 CCIfType<[i32], CCAssignToReg<[EAX, EDX]>>,
35 CCIfType<[i64], CCAssignToReg<[RAX, RDX]>>,
37 // Vector types are returned in XMM0 and XMM1, when they fit. XMM2 and XMM3
38 // can only be used by ABI non-compliant code. If the target doesn't have XMM
39 // registers, it won't have vector types.
40 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
41 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,
43 // 256-bit vectors are returned in YMM0 and XMM1, when they fit. YMM2 and YMM3
44 // can only be used by ABI non-compliant code. This vector type is only
45 // supported while using the AVX target feature.
46 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
47 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>,
49 // MMX vector types are always returned in MM0. If the target doesn't have
50 // MM0, it doesn't support these vector types.
51 CCIfType<[x86mmx], CCAssignToReg<[MM0]>>,
53 // Long double types are always returned in ST0 (even with SSE).
54 CCIfType<[f80], CCAssignToReg<[ST0, ST1]>>
57 // X86-32 C return-value convention.
58 def RetCC_X86_32_C : CallingConv<[
59 // The X86-32 calling convention returns FP values in ST0, unless marked
60 // with "inreg" (used here to distinguish one kind of reg from another,
61 // weirdly; this is really the sse-regparm calling convention) in which
62 // case they use XMM0, otherwise it is the same as the common X86 calling
64 CCIfInReg<CCIfSubtarget<"hasSSE2()",
65 CCIfType<[f32, f64], CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
66 CCIfType<[f32,f64], CCAssignToReg<[ST0, ST1]>>,
67 CCDelegateTo<RetCC_X86Common>
70 // X86-32 FastCC return-value convention.
71 def RetCC_X86_32_Fast : CallingConv<[
72 // The X86-32 fastcc returns 1, 2, or 3 FP values in XMM0-2 if the target has
74 // This can happen when a float, 2 x float, or 3 x float vector is split by
75 // target lowering, and is returned in 1-3 sse regs.
76 CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
77 CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
79 // For integers, ECX can be used as an extra return register
80 CCIfType<[i8], CCAssignToReg<[AL, DL, CL]>>,
81 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>,
82 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>,
84 // Otherwise, it is the same as the common X86 calling convention.
85 CCDelegateTo<RetCC_X86Common>
88 // X86-64 C return-value convention.
89 def RetCC_X86_64_C : CallingConv<[
90 // The X86-64 calling convention always returns FP values in XMM0.
91 CCIfType<[f32], CCAssignToReg<[XMM0, XMM1]>>,
92 CCIfType<[f64], CCAssignToReg<[XMM0, XMM1]>>,
94 // MMX vector types are always returned in XMM0.
95 CCIfType<[x86mmx], CCAssignToReg<[XMM0, XMM1]>>,
96 CCDelegateTo<RetCC_X86Common>
99 // X86-Win64 C return-value convention.
100 def RetCC_X86_Win64_C : CallingConv<[
101 // The X86-Win64 calling convention always returns __m64 values in RAX.
102 CCIfType<[x86mmx], CCBitConvertToType<i64>>,
104 // Otherwise, everything is the same as 'normal' X86-64 C CC.
105 CCDelegateTo<RetCC_X86_64_C>
109 // This is the root return-value convention for the X86-32 backend.
110 def RetCC_X86_32 : CallingConv<[
111 // If FastCC, use RetCC_X86_32_Fast.
112 CCIfCC<"CallingConv::Fast", CCDelegateTo<RetCC_X86_32_Fast>>,
113 // Otherwise, use RetCC_X86_32_C.
114 CCDelegateTo<RetCC_X86_32_C>
117 // This is the root return-value convention for the X86-64 backend.
118 def RetCC_X86_64 : CallingConv<[
119 // Mingw64 and native Win64 use Win64 CC
120 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<RetCC_X86_Win64_C>>,
122 // Otherwise, drop to normal X86-64 CC
123 CCDelegateTo<RetCC_X86_64_C>
126 // This is the return-value convention used for the entire X86 backend.
127 def RetCC_X86 : CallingConv<[
128 CCIfSubtarget<"is64Bit()", CCDelegateTo<RetCC_X86_64>>,
129 CCDelegateTo<RetCC_X86_32>
132 //===----------------------------------------------------------------------===//
133 // X86-64 Argument Calling Conventions
134 //===----------------------------------------------------------------------===//
136 def CC_X86_64_C : CallingConv<[
137 // Handles byval parameters.
138 CCIfByVal<CCPassByVal<8, 8>>,
140 // Promote i8/i16 arguments to i32.
141 CCIfType<[i8, i16], CCPromoteToType<i32>>,
143 // The 'nest' parameter, if any, is passed in R10.
144 CCIfNest<CCAssignToReg<[R10]>>,
146 // The first 6 integer arguments are passed in integer registers.
147 CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D, R9D]>>,
148 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
150 // The first 8 MMX vector arguments are passed in XMM registers on Darwin.
152 CCIfSubtarget<"isTargetDarwin()",
153 CCIfSubtarget<"hasSSE2()",
154 CCPromoteToType<v2i64>>>>,
156 // The first 8 FP/Vector arguments are passed in XMM registers.
157 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
158 CCIfSubtarget<"hasSSE1()",
159 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>,
161 // The first 8 256-bit vector arguments are passed in YMM registers, unless
162 // this is a vararg function.
163 // FIXME: This isn't precisely correct; the x86-64 ABI document says that
164 // fixed arguments to vararg functions are supposed to be passed in
165 // registers. Actually modeling that would be a lot of work, though.
166 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
167 CCIfSubtarget<"hasAVX()",
168 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3,
169 YMM4, YMM5, YMM6, YMM7]>>>>,
171 // Integer/FP values get stored in stack slots that are 8 bytes in size and
172 // 8-byte aligned if there are no more registers to hold them.
173 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
175 // Long doubles get stack slots whose size and alignment depends on the
177 CCIfType<[f80], CCAssignToStack<0, 0>>,
179 // Vectors get 16-byte stack slots that are 16-byte aligned.
180 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
182 // 256-bit vectors get 32-byte stack slots that are 32-byte aligned.
183 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
184 CCAssignToStack<32, 32>>
187 // Calling convention used on Win64
188 def CC_X86_Win64_C : CallingConv<[
189 // FIXME: Handle byval stuff.
190 // FIXME: Handle varargs.
192 // Promote i8/i16 arguments to i32.
193 CCIfType<[i8, i16], CCPromoteToType<i32>>,
195 // The 'nest' parameter, if any, is passed in R10.
196 CCIfNest<CCAssignToReg<[R10]>>,
198 // 128 bit vectors are passed by pointer
199 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCPassIndirect<i64>>,
201 // The first 4 MMX vector arguments are passed in GPRs.
202 CCIfType<[x86mmx], CCBitConvertToType<i64>>,
204 // The first 4 integer arguments are passed in integer registers.
205 CCIfType<[i32], CCAssignToRegWithShadow<[ECX , EDX , R8D , R9D ],
206 [XMM0, XMM1, XMM2, XMM3]>>,
208 // Do not pass the sret argument in RCX, the Win64 thiscall calling
209 // convention requires "this" to be passed in RCX.
210 CCIfCC<"CallingConv::X86_ThisCall",
211 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[RDX , R8 , R9 ],
212 [XMM1, XMM2, XMM3]>>>>,
214 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
215 [XMM0, XMM1, XMM2, XMM3]>>,
217 // The first 4 FP/Vector arguments are passed in XMM registers.
218 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
219 CCAssignToRegWithShadow<[XMM0, XMM1, XMM2, XMM3],
220 [RCX , RDX , R8 , R9 ]>>,
222 // Integer/FP values get stored in stack slots that are 8 bytes in size and
223 // 8-byte aligned if there are no more registers to hold them.
224 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
226 // Long doubles get stack slots whose size and alignment depends on the
228 CCIfType<[f80], CCAssignToStack<0, 0>>
231 def CC_X86_64_GHC : CallingConv<[
232 // Promote i8/i16/i32 arguments to i64.
233 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
235 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim
237 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
239 // Pass in STG registers: F1, F2, F3, F4, D1, D2
240 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
241 CCIfSubtarget<"hasSSE1()",
242 CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>
245 //===----------------------------------------------------------------------===//
246 // X86 C Calling Convention
247 //===----------------------------------------------------------------------===//
249 /// CC_X86_32_Common - In all X86-32 calling conventions, extra integers and FP
250 /// values are spilled on the stack, and the first 4 vector values go in XMM
252 def CC_X86_32_Common : CallingConv<[
253 // Handles byval parameters.
254 CCIfByVal<CCPassByVal<4, 4>>,
256 // The first 3 float or double arguments, if marked 'inreg' and if the call
257 // is not a vararg call and if SSE2 is available, are passed in SSE registers.
258 CCIfNotVarArg<CCIfInReg<CCIfType<[f32,f64],
259 CCIfSubtarget<"hasSSE2()",
260 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>>,
262 // The first 3 __m64 vector arguments are passed in mmx registers if the
263 // call is not a vararg call.
264 CCIfNotVarArg<CCIfType<[x86mmx],
265 CCAssignToReg<[MM0, MM1, MM2]>>>,
267 // Integer/Float values get stored in stack slots that are 4 bytes in
268 // size and 4-byte aligned.
269 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
271 // Doubles get 8-byte slots that are 4-byte aligned.
272 CCIfType<[f64], CCAssignToStack<8, 4>>,
274 // Long doubles get slots whose size depends on the subtarget.
275 CCIfType<[f80], CCAssignToStack<0, 4>>,
277 // The first 4 SSE vector arguments are passed in XMM registers.
278 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
279 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>>,
281 // The first 4 AVX 256-bit vector arguments are passed in YMM registers.
282 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
283 CCIfSubtarget<"hasAVX()",
284 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>>>,
286 // Other SSE vectors get 16-byte stack slots that are 16-byte aligned.
287 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
289 // 256-bit AVX vectors get 32-byte stack slots that are 32-byte aligned.
290 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
291 CCAssignToStack<32, 32>>,
293 // __m64 vectors get 8-byte stack slots that are 4-byte aligned. They are
294 // passed in the parameter area.
295 CCIfType<[x86mmx], CCAssignToStack<8, 4>>]>;
297 def CC_X86_32_C : CallingConv<[
298 // Promote i8/i16 arguments to i32.
299 CCIfType<[i8, i16], CCPromoteToType<i32>>,
301 // The 'nest' parameter, if any, is passed in ECX.
302 CCIfNest<CCAssignToReg<[ECX]>>,
304 // The first 3 integer arguments, if marked 'inreg' and if the call is not
305 // a vararg call, are passed in integer registers.
306 CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>>>,
308 // Otherwise, same as everything else.
309 CCDelegateTo<CC_X86_32_Common>
312 def CC_X86_32_FastCall : CallingConv<[
313 // Promote i8/i16 arguments to i32.
314 CCIfType<[i8, i16], CCPromoteToType<i32>>,
316 // The 'nest' parameter, if any, is passed in EAX.
317 CCIfNest<CCAssignToReg<[EAX]>>,
319 // The first 2 integer arguments are passed in ECX/EDX
320 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>,
322 // Otherwise, same as everything else.
323 CCDelegateTo<CC_X86_32_Common>
326 def CC_X86_32_ThisCall : CallingConv<[
327 // Promote i8/i16 arguments to i32.
328 CCIfType<[i8, i16], CCPromoteToType<i32>>,
330 // The 'nest' parameter, if any, is passed in EAX.
331 CCIfNest<CCAssignToReg<[EAX]>>,
333 // The first integer argument is passed in ECX
334 CCIfType<[i32], CCAssignToReg<[ECX]>>,
336 // Otherwise, same as everything else.
337 CCDelegateTo<CC_X86_32_Common>
340 def CC_X86_32_FastCC : CallingConv<[
341 // Handles byval parameters. Note that we can't rely on the delegation
342 // to CC_X86_32_Common for this because that happens after code that
343 // puts arguments in registers.
344 CCIfByVal<CCPassByVal<4, 4>>,
346 // Promote i8/i16 arguments to i32.
347 CCIfType<[i8, i16], CCPromoteToType<i32>>,
349 // The 'nest' parameter, if any, is passed in EAX.
350 CCIfNest<CCAssignToReg<[EAX]>>,
352 // The first 2 integer arguments are passed in ECX/EDX
353 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>,
355 // The first 3 float or double arguments, if the call is not a vararg
356 // call and if SSE2 is available, are passed in SSE registers.
357 CCIfNotVarArg<CCIfType<[f32,f64],
358 CCIfSubtarget<"hasSSE2()",
359 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
361 // Doubles get 8-byte slots that are 8-byte aligned.
362 CCIfType<[f64], CCAssignToStack<8, 8>>,
364 // Otherwise, same as everything else.
365 CCDelegateTo<CC_X86_32_Common>
368 def CC_X86_32_GHC : CallingConv<[
369 // Promote i8/i16 arguments to i32.
370 CCIfType<[i8, i16], CCPromoteToType<i32>>,
372 // Pass in STG registers: Base, Sp, Hp, R1
373 CCIfType<[i32], CCAssignToReg<[EBX, EBP, EDI, ESI]>>
376 //===----------------------------------------------------------------------===//
377 // X86 Root Argument Calling Conventions
378 //===----------------------------------------------------------------------===//
380 // This is the root argument convention for the X86-32 backend.
381 def CC_X86_32 : CallingConv<[
382 CCIfCC<"CallingConv::X86_FastCall", CCDelegateTo<CC_X86_32_FastCall>>,
383 CCIfCC<"CallingConv::X86_ThisCall", CCDelegateTo<CC_X86_32_ThisCall>>,
384 CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_X86_32_FastCC>>,
385 CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_32_GHC>>,
387 // Otherwise, drop to normal X86-32 CC
388 CCDelegateTo<CC_X86_32_C>
391 // This is the root argument convention for the X86-64 backend.
392 def CC_X86_64 : CallingConv<[
393 CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_64_GHC>>,
395 // Mingw64 and native Win64 use Win64 CC
396 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>,
398 // Otherwise, drop to normal X86-64 CC
399 CCDelegateTo<CC_X86_64_C>
402 // This is the argument convention used for the entire X86 backend.
403 def CC_X86 : CallingConv<[
404 CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64>>,
405 CCDelegateTo<CC_X86_32>
408 //===----------------------------------------------------------------------===//
409 // Callee-saved Registers.
410 //===----------------------------------------------------------------------===//
412 def CSR_Ghc : CalleeSavedRegs<(add)>;
414 def CSR_32 : CalleeSavedRegs<(add ESI, EDI, EBX, EBP)>;
415 def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>;
417 def CSR_32EHRet : CalleeSavedRegs<(add EAX, EDX, CSR_32)>;
418 def CSR_64EHRet : CalleeSavedRegs<(add RAX, RDX, CSR_64)>;
420 def CSR_Win64 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15,
421 (sequence "XMM%u", 6, 15))>;