1 //===-- X86CallingConv.td - Calling Conventions X86 32/64 --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This describes the calling conventions for the X86-32 and X86-64
13 //===----------------------------------------------------------------------===//
15 /// CCIfSubtarget - Match if the current subtarget has a feature F.
16 class CCIfSubtarget<string F, CCAction A>
17 : CCIf<!strconcat("State.getTarget().getSubtarget<X86Subtarget>().", F), A>;
19 //===----------------------------------------------------------------------===//
20 // Return Value Calling Conventions
21 //===----------------------------------------------------------------------===//
23 // Return-value conventions common to all X86 CC's.
24 def RetCC_X86Common : CallingConv<[
25 // Scalar values are returned in AX first, then DX. For i8, the ABI
26 // requires the values to be in AL and AH, however this code uses AL and DL
27 // instead. This is because using AH for the second register conflicts with
28 // the way LLVM does multiple return values -- a return of {i16,i8} would end
29 // up in AX and AH, which overlap. Front-ends wishing to conform to the ABI
30 // for functions that return two i8 values are currently expected to pack the
31 // values into an i16 (which uses AX, and thus AL:AH).
33 // For code that doesn't care about the ABI, we allow returning more than two
34 // integer values in registers.
35 CCIfType<[i8] , CCAssignToReg<[AL, DL, CL]>>,
36 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>,
37 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>,
38 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX]>>,
40 // Vector types are returned in XMM0 and XMM1, when they fit. XMM2 and XMM3
41 // can only be used by ABI non-compliant code. If the target doesn't have XMM
42 // registers, it won't have vector types.
43 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
44 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,
46 // 256-bit vectors are returned in YMM0 and XMM1, when they fit. YMM2 and YMM3
47 // can only be used by ABI non-compliant code. This vector type is only
48 // supported while using the AVX target feature.
49 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
50 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>,
52 // 512-bit vectors are returned in ZMM0 and ZMM1, when they fit. ZMM2 and ZMM3
53 // can only be used by ABI non-compliant code. This vector type is only
54 // supported while using the AVX-512 target feature.
55 CCIfType<[v16i32, v8i64, v16f32, v8f64],
56 CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>,
58 // MMX vector types are always returned in MM0. If the target doesn't have
59 // MM0, it doesn't support these vector types.
60 CCIfType<[x86mmx], CCAssignToReg<[MM0]>>,
62 // Long double types are always returned in ST0 (even with SSE).
63 CCIfType<[f80], CCAssignToReg<[ST0, ST1]>>
66 // X86-32 C return-value convention.
67 def RetCC_X86_32_C : CallingConv<[
68 // The X86-32 calling convention returns FP values in ST0, unless marked
69 // with "inreg" (used here to distinguish one kind of reg from another,
70 // weirdly; this is really the sse-regparm calling convention) in which
71 // case they use XMM0, otherwise it is the same as the common X86 calling
73 CCIfInReg<CCIfSubtarget<"hasSSE2()",
74 CCIfType<[f32, f64], CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
75 CCIfType<[f32,f64], CCAssignToReg<[ST0, ST1]>>,
76 CCDelegateTo<RetCC_X86Common>
79 // X86-32 FastCC return-value convention.
80 def RetCC_X86_32_Fast : CallingConv<[
81 // The X86-32 fastcc returns 1, 2, or 3 FP values in XMM0-2 if the target has
83 // This can happen when a float, 2 x float, or 3 x float vector is split by
84 // target lowering, and is returned in 1-3 sse regs.
85 CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
86 CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
88 // For integers, ECX can be used as an extra return register
89 CCIfType<[i8], CCAssignToReg<[AL, DL, CL]>>,
90 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>,
91 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>,
93 // Otherwise, it is the same as the common X86 calling convention.
94 CCDelegateTo<RetCC_X86Common>
97 // Intel_OCL_BI return-value convention.
98 def RetCC_Intel_OCL_BI : CallingConv<[
99 // Vector types are returned in XMM0,XMM1,XMMM2 and XMM3.
100 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64],
101 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,
103 // 256-bit FP vectors
104 // No more than 4 registers
105 CCIfType<[v8f32, v4f64, v8i32, v4i64],
106 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>,
108 // 512-bit FP vectors
109 CCIfType<[v16f32, v8f64, v16i32, v8i64],
110 CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>,
112 // i32, i64 in the standard way
113 CCDelegateTo<RetCC_X86Common>
116 // X86-32 HiPE return-value convention.
117 def RetCC_X86_32_HiPE : CallingConv<[
118 // Promote all types to i32
119 CCIfType<[i8, i16], CCPromoteToType<i32>>,
121 // Return: HP, P, VAL1, VAL2
122 CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX]>>
125 // X86-64 C return-value convention.
126 def RetCC_X86_64_C : CallingConv<[
127 // The X86-64 calling convention always returns FP values in XMM0.
128 CCIfType<[f32], CCAssignToReg<[XMM0, XMM1]>>,
129 CCIfType<[f64], CCAssignToReg<[XMM0, XMM1]>>,
131 // MMX vector types are always returned in XMM0.
132 CCIfType<[x86mmx], CCAssignToReg<[XMM0, XMM1]>>,
133 CCDelegateTo<RetCC_X86Common>
136 // X86-Win64 C return-value convention.
137 def RetCC_X86_Win64_C : CallingConv<[
138 // The X86-Win64 calling convention always returns __m64 values in RAX.
139 CCIfType<[x86mmx], CCBitConvertToType<i64>>,
141 // Otherwise, everything is the same as 'normal' X86-64 C CC.
142 CCDelegateTo<RetCC_X86_64_C>
145 // X86-64 HiPE return-value convention.
146 def RetCC_X86_64_HiPE : CallingConv<[
147 // Promote all types to i64
148 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
150 // Return: HP, P, VAL1, VAL2
151 CCIfType<[i64], CCAssignToReg<[R15, RBP, RAX, RDX]>>
154 // X86-64 WebKit_JS return-value convention.
155 def RetCC_X86_64_WebKit_JS : CallingConv<[
156 // Promote all types to i64
157 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
160 CCIfType<[i64], CCAssignToReg<[RAX]>>
163 // This is the root return-value convention for the X86-32 backend.
164 def RetCC_X86_32 : CallingConv<[
165 // If FastCC, use RetCC_X86_32_Fast.
166 CCIfCC<"CallingConv::Fast", CCDelegateTo<RetCC_X86_32_Fast>>,
167 // If HiPE, use RetCC_X86_32_HiPE.
168 CCIfCC<"CallingConv::HiPE", CCDelegateTo<RetCC_X86_32_HiPE>>,
170 // Otherwise, use RetCC_X86_32_C.
171 CCDelegateTo<RetCC_X86_32_C>
174 // This is the root return-value convention for the X86-64 backend.
175 def RetCC_X86_64 : CallingConv<[
176 // HiPE uses RetCC_X86_64_HiPE
177 CCIfCC<"CallingConv::HiPE", CCDelegateTo<RetCC_X86_64_HiPE>>,
179 // Handle JavaScript calls.
180 CCIfCC<"CallingConv::WebKit_JS", CCDelegateTo<RetCC_X86_64_WebKit_JS>>,
182 // Handle explicit CC selection
183 CCIfCC<"CallingConv::X86_64_Win64", CCDelegateTo<RetCC_X86_Win64_C>>,
184 CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo<RetCC_X86_64_C>>,
186 // Mingw64 and native Win64 use Win64 CC
187 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<RetCC_X86_Win64_C>>,
189 // Otherwise, drop to normal X86-64 CC
190 CCDelegateTo<RetCC_X86_64_C>
193 // This is the return-value convention used for the entire X86 backend.
194 def RetCC_X86 : CallingConv<[
196 // Check if this is the Intel OpenCL built-ins calling convention
197 CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo<RetCC_Intel_OCL_BI>>,
199 CCIfSubtarget<"is64Bit()", CCDelegateTo<RetCC_X86_64>>,
200 CCDelegateTo<RetCC_X86_32>
203 //===----------------------------------------------------------------------===//
204 // X86-64 Argument Calling Conventions
205 //===----------------------------------------------------------------------===//
207 def CC_X86_64_C : CallingConv<[
208 // Handles byval parameters.
209 CCIfByVal<CCPassByVal<8, 8>>,
211 // Promote i8/i16 arguments to i32.
212 CCIfType<[i8, i16], CCPromoteToType<i32>>,
214 // The 'nest' parameter, if any, is passed in R10.
215 CCIfNest<CCAssignToReg<[R10]>>,
217 // The first 6 integer arguments are passed in integer registers.
218 CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D, R9D]>>,
219 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
221 // The first 8 MMX vector arguments are passed in XMM registers on Darwin.
223 CCIfSubtarget<"isTargetDarwin()",
224 CCIfSubtarget<"hasSSE2()",
225 CCPromoteToType<v2i64>>>>,
227 // The first 8 FP/Vector arguments are passed in XMM registers.
228 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
229 CCIfSubtarget<"hasSSE1()",
230 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>,
232 // The first 8 256-bit vector arguments are passed in YMM registers, unless
233 // this is a vararg function.
234 // FIXME: This isn't precisely correct; the x86-64 ABI document says that
235 // fixed arguments to vararg functions are supposed to be passed in
236 // registers. Actually modeling that would be a lot of work, though.
237 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
238 CCIfSubtarget<"hasFp256()",
239 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3,
240 YMM4, YMM5, YMM6, YMM7]>>>>,
242 // The first 8 512-bit vector arguments are passed in ZMM registers.
243 CCIfNotVarArg<CCIfType<[v16i32, v8i64, v16f32, v8f64],
244 CCIfSubtarget<"hasAVX512()",
245 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7]>>>>,
247 // Integer/FP values get stored in stack slots that are 8 bytes in size and
248 // 8-byte aligned if there are no more registers to hold them.
249 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
251 // Long doubles get stack slots whose size and alignment depends on the
253 CCIfType<[f80], CCAssignToStack<0, 0>>,
255 // Vectors get 16-byte stack slots that are 16-byte aligned.
256 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
258 // 256-bit vectors get 32-byte stack slots that are 32-byte aligned.
259 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
260 CCAssignToStack<32, 32>>,
262 // 512-bit vectors get 64-byte stack slots that are 64-byte aligned.
263 CCIfType<[v16i32, v8i64, v16f32, v8f64],
264 CCAssignToStack<64, 64>>
267 // Calling convention used on Win64
268 def CC_X86_Win64_C : CallingConv<[
269 // FIXME: Handle byval stuff.
270 // FIXME: Handle varargs.
272 // Promote i8/i16 arguments to i32.
273 CCIfType<[i8, i16], CCPromoteToType<i32>>,
275 // The 'nest' parameter, if any, is passed in R10.
276 CCIfNest<CCAssignToReg<[R10]>>,
278 // 128 bit vectors are passed by pointer
279 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCPassIndirect<i64>>,
282 // 256 bit vectors are passed by pointer
283 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>,
285 // 512 bit vectors are passed by pointer
286 CCIfType<[v16i32, v16f32, v8f64, v8i64], CCPassIndirect<i64>>,
288 // The first 4 MMX vector arguments are passed in GPRs.
289 CCIfType<[x86mmx], CCBitConvertToType<i64>>,
291 // The first 4 integer arguments are passed in integer registers.
292 CCIfType<[i32], CCAssignToRegWithShadow<[ECX , EDX , R8D , R9D ],
293 [XMM0, XMM1, XMM2, XMM3]>>,
295 // Do not pass the sret argument in RCX, the Win64 thiscall calling
296 // convention requires "this" to be passed in RCX.
297 CCIfCC<"CallingConv::X86_ThisCall",
298 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[RDX , R8 , R9 ],
299 [XMM1, XMM2, XMM3]>>>>,
301 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
302 [XMM0, XMM1, XMM2, XMM3]>>,
304 // The first 4 FP/Vector arguments are passed in XMM registers.
305 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
306 CCAssignToRegWithShadow<[XMM0, XMM1, XMM2, XMM3],
307 [RCX , RDX , R8 , R9 ]>>,
309 // Integer/FP values get stored in stack slots that are 8 bytes in size and
310 // 8-byte aligned if there are no more registers to hold them.
311 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
313 // Long doubles get stack slots whose size and alignment depends on the
315 CCIfType<[f80], CCAssignToStack<0, 0>>
318 def CC_X86_64_GHC : CallingConv<[
319 // Promote i8/i16/i32 arguments to i64.
320 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
322 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim
324 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
326 // Pass in STG registers: F1, F2, F3, F4, D1, D2
327 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
328 CCIfSubtarget<"hasSSE1()",
329 CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>
332 def CC_X86_64_HiPE : CallingConv<[
333 // Promote i8/i16/i32 arguments to i64.
334 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
336 // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2, ARG3
337 CCIfType<[i64], CCAssignToReg<[R15, RBP, RSI, RDX, RCX, R8]>>,
339 // Integer/FP values get stored in stack slots that are 8 bytes in size and
340 // 8-byte aligned if there are no more registers to hold them.
341 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>
344 def CC_X86_64_WebKit_JS : CallingConv<[
345 // Promote i8/i16 arguments to i32.
346 CCIfType<[i8, i16], CCPromoteToType<i32>>,
348 // Integer/FP values are always stored in stack slots that are 8 bytes in size
349 // and 8-byte aligned.
350 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>
353 //===----------------------------------------------------------------------===//
354 // X86 C Calling Convention
355 //===----------------------------------------------------------------------===//
357 /// CC_X86_32_Common - In all X86-32 calling conventions, extra integers and FP
358 /// values are spilled on the stack, and the first 4 vector values go in XMM
360 def CC_X86_32_Common : CallingConv<[
361 // Handles byval parameters.
362 CCIfByVal<CCPassByVal<4, 4>>,
364 // The first 3 float or double arguments, if marked 'inreg' and if the call
365 // is not a vararg call and if SSE2 is available, are passed in SSE registers.
366 CCIfNotVarArg<CCIfInReg<CCIfType<[f32,f64],
367 CCIfSubtarget<"hasSSE2()",
368 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>>,
370 // The first 3 __m64 vector arguments are passed in mmx registers if the
371 // call is not a vararg call.
372 CCIfNotVarArg<CCIfType<[x86mmx],
373 CCAssignToReg<[MM0, MM1, MM2]>>>,
375 // Integer/Float values get stored in stack slots that are 4 bytes in
376 // size and 4-byte aligned.
377 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
379 // Doubles get 8-byte slots that are 4-byte aligned.
380 CCIfType<[f64], CCAssignToStack<8, 4>>,
382 // Long doubles get slots whose size depends on the subtarget.
383 CCIfType<[f80], CCAssignToStack<0, 4>>,
385 // The first 4 SSE vector arguments are passed in XMM registers.
386 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
387 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>>,
389 // The first 4 AVX 256-bit vector arguments are passed in YMM registers.
390 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
391 CCIfSubtarget<"hasFp256()",
392 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>>>,
394 // Other SSE vectors get 16-byte stack slots that are 16-byte aligned.
395 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
397 // 256-bit AVX vectors get 32-byte stack slots that are 32-byte aligned.
398 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
399 CCAssignToStack<32, 32>>,
401 // __m64 vectors get 8-byte stack slots that are 4-byte aligned. They are
402 // passed in the parameter area.
403 CCIfType<[x86mmx], CCAssignToStack<8, 4>>]>;
405 def CC_X86_32_C : CallingConv<[
406 // Promote i8/i16 arguments to i32.
407 CCIfType<[i8, i16], CCPromoteToType<i32>>,
409 // The 'nest' parameter, if any, is passed in ECX.
410 CCIfNest<CCAssignToReg<[ECX]>>,
412 // The first 3 integer arguments, if marked 'inreg' and if the call is not
413 // a vararg call, are passed in integer registers.
414 CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>>>,
416 // Otherwise, same as everything else.
417 CCDelegateTo<CC_X86_32_Common>
420 def CC_X86_32_FastCall : CallingConv<[
421 // Promote i8/i16 arguments to i32.
422 CCIfType<[i8, i16], CCPromoteToType<i32>>,
424 // The 'nest' parameter, if any, is passed in EAX.
425 CCIfNest<CCAssignToReg<[EAX]>>,
427 // The first 2 integer arguments are passed in ECX/EDX
428 CCIfInReg<CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>>,
430 // Otherwise, same as everything else.
431 CCDelegateTo<CC_X86_32_Common>
434 def CC_X86_32_ThisCall : CallingConv<[
435 // Promote i8/i16 arguments to i32.
436 CCIfType<[i8, i16], CCPromoteToType<i32>>,
438 // Pass sret arguments indirectly through stack.
439 CCIfSRet<CCAssignToStack<4, 4>>,
441 // The first integer argument is passed in ECX
442 CCIfType<[i32], CCAssignToReg<[ECX]>>,
444 // Otherwise, same as everything else.
445 CCDelegateTo<CC_X86_32_Common>
448 def CC_X86_32_FastCC : CallingConv<[
449 // Handles byval parameters. Note that we can't rely on the delegation
450 // to CC_X86_32_Common for this because that happens after code that
451 // puts arguments in registers.
452 CCIfByVal<CCPassByVal<4, 4>>,
454 // Promote i8/i16 arguments to i32.
455 CCIfType<[i8, i16], CCPromoteToType<i32>>,
457 // The 'nest' parameter, if any, is passed in EAX.
458 CCIfNest<CCAssignToReg<[EAX]>>,
460 // The first 2 integer arguments are passed in ECX/EDX
461 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>,
463 // The first 3 float or double arguments, if the call is not a vararg
464 // call and if SSE2 is available, are passed in SSE registers.
465 CCIfNotVarArg<CCIfType<[f32,f64],
466 CCIfSubtarget<"hasSSE2()",
467 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
469 // Doubles get 8-byte slots that are 8-byte aligned.
470 CCIfType<[f64], CCAssignToStack<8, 8>>,
472 // Otherwise, same as everything else.
473 CCDelegateTo<CC_X86_32_Common>
476 def CC_X86_32_GHC : CallingConv<[
477 // Promote i8/i16 arguments to i32.
478 CCIfType<[i8, i16], CCPromoteToType<i32>>,
480 // Pass in STG registers: Base, Sp, Hp, R1
481 CCIfType<[i32], CCAssignToReg<[EBX, EBP, EDI, ESI]>>
484 def CC_X86_32_HiPE : CallingConv<[
485 // Promote i8/i16 arguments to i32.
486 CCIfType<[i8, i16], CCPromoteToType<i32>>,
488 // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2
489 CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX, ECX]>>,
491 // Integer/Float values get stored in stack slots that are 4 bytes in
492 // size and 4-byte aligned.
493 CCIfType<[i32, f32], CCAssignToStack<4, 4>>
496 // X86-64 Intel OpenCL built-ins calling convention.
497 def CC_Intel_OCL_BI : CallingConv<[
499 CCIfType<[i32], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[ECX, EDX, R8D, R9D]>>>,
500 CCIfType<[i64], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[RCX, RDX, R8, R9 ]>>>,
502 CCIfType<[i32], CCIfSubtarget<"is64Bit()", CCAssignToReg<[EDI, ESI, EDX, ECX]>>>,
503 CCIfType<[i64], CCIfSubtarget<"is64Bit()", CCAssignToReg<[RDI, RSI, RDX, RCX]>>>,
505 CCIfType<[i32], CCAssignToStack<4, 4>>,
507 // The SSE vector arguments are passed in XMM registers.
508 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64],
509 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>,
511 // The 256-bit vector arguments are passed in YMM registers.
512 CCIfType<[v8f32, v4f64, v8i32, v4i64],
513 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>,
515 // The 512-bit vector arguments are passed in ZMM registers.
516 CCIfType<[v16f32, v8f64, v16i32, v8i64],
517 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3]>>,
519 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>,
520 CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64_C>>,
521 CCDelegateTo<CC_X86_32_C>
524 //===----------------------------------------------------------------------===//
525 // X86 Root Argument Calling Conventions
526 //===----------------------------------------------------------------------===//
528 // This is the root argument convention for the X86-32 backend.
529 def CC_X86_32 : CallingConv<[
530 CCIfCC<"CallingConv::X86_FastCall", CCDelegateTo<CC_X86_32_FastCall>>,
531 CCIfCC<"CallingConv::X86_ThisCall", CCDelegateTo<CC_X86_32_ThisCall>>,
532 CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_X86_32_FastCC>>,
533 CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_32_GHC>>,
534 CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_32_HiPE>>,
536 // Otherwise, drop to normal X86-32 CC
537 CCDelegateTo<CC_X86_32_C>
540 // This is the root argument convention for the X86-64 backend.
541 def CC_X86_64 : CallingConv<[
542 CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_64_GHC>>,
543 CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_64_HiPE>>,
544 CCIfCC<"CallingConv::WebKit_JS", CCDelegateTo<CC_X86_64_WebKit_JS>>,
545 CCIfCC<"CallingConv::X86_64_Win64", CCDelegateTo<CC_X86_Win64_C>>,
546 CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo<CC_X86_64_C>>,
548 // Mingw64 and native Win64 use Win64 CC
549 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>,
551 // Otherwise, drop to normal X86-64 CC
552 CCDelegateTo<CC_X86_64_C>
555 // This is the argument convention used for the entire X86 backend.
556 def CC_X86 : CallingConv<[
557 CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo<CC_Intel_OCL_BI>>,
558 CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64>>,
559 CCDelegateTo<CC_X86_32>
562 //===----------------------------------------------------------------------===//
563 // Callee-saved Registers.
564 //===----------------------------------------------------------------------===//
566 def CSR_NoRegs : CalleeSavedRegs<(add)>;
568 def CSR_32 : CalleeSavedRegs<(add ESI, EDI, EBX, EBP)>;
569 def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>;
571 def CSR_32EHRet : CalleeSavedRegs<(add EAX, EDX, CSR_32)>;
572 def CSR_64EHRet : CalleeSavedRegs<(add RAX, RDX, CSR_64)>;
574 def CSR_Win64 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15,
575 (sequence "XMM%u", 6, 15))>;
577 def CSR_MostRegs_64 : CalleeSavedRegs<(add RBX, RCX, RDX, RSI, RDI, R8, R9, R10,
578 R11, R12, R13, R14, R15, RBP,
579 (sequence "XMM%u", 0, 15))>;
581 // Standard C + YMM6-15
582 def CSR_Win64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12,
584 (sequence "YMM%u", 6, 15))>;
586 def CSR_Win64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI,
588 (sequence "ZMM%u", 6, 21),
590 //Standard C + XMM 8-15
591 def CSR_64_Intel_OCL_BI : CalleeSavedRegs<(add CSR_64,
592 (sequence "XMM%u", 8, 15))>;
594 //Standard C + YMM 8-15
595 def CSR_64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add CSR_64,
596 (sequence "YMM%u", 8, 15))>;
598 def CSR_64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add CSR_64,
599 (sequence "ZMM%u", 16, 31),