1 //===- X86CallingConv.td - Calling Conventions X86 32/64 ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This describes the calling conventions for the X86-32 and X86-64
13 //===----------------------------------------------------------------------===//
15 /// CCIfSubtarget - Match if the current subtarget has a feature F.
16 class CCIfSubtarget<string F, CCAction A>
17 : CCIf<!strconcat("State.getTarget().getSubtarget<X86Subtarget>().", F), A>;
19 //===----------------------------------------------------------------------===//
20 // Return Value Calling Conventions
21 //===----------------------------------------------------------------------===//
23 // Return-value conventions common to all X86 CC's.
24 def RetCC_X86Common : CallingConv<[
25 // Scalar values are returned in AX first, then DX. For i8, the ABI
26 // requires the values to be in AL and AH, however this code uses AL and DL
27 // instead. This is because using AH for the second register conflicts with
28 // the way LLVM does multiple return values -- a return of {i16,i8} would end
29 // up in AX and AH, which overlap. Front-ends wishing to conform to the ABI
30 // for functions that return two i8 values are currently expected to pack the
31 // values into an i16 (which uses AX, and thus AL:AH).
32 CCIfType<[i8] , CCAssignToReg<[AL, DL]>>,
33 CCIfType<[i16], CCAssignToReg<[AX, DX]>>,
34 CCIfType<[i32], CCAssignToReg<[EAX, EDX]>>,
35 CCIfType<[i64], CCAssignToReg<[RAX, RDX]>>,
37 // Vector types are returned in XMM0 and XMM1, when they fit. XMMM2 and XMM3
38 // can only be used by ABI non-compliant code. If the target doesn't have XMM
39 // registers, it won't have vector types.
40 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
41 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,
43 // MMX vector types are always returned in MM0. If the target doesn't have
44 // MM0, it doesn't support these vector types.
45 CCIfType<[v8i8, v4i16, v2i32, v1i64, v2f32], CCAssignToReg<[MM0]>>,
47 // Long double types are always returned in ST0 (even with SSE).
48 CCIfType<[f80], CCAssignToReg<[ST0, ST1]>>
51 // X86-32 C return-value convention.
52 def RetCC_X86_32_C : CallingConv<[
53 // The X86-32 calling convention returns FP values in ST0, unless marked
54 // with "inreg" (used here to distinguish one kind of reg from another,
55 // weirdly; this is really the sse-regparm calling convention) in which
56 // case they use XMM0, otherwise it is the same as the common X86 calling
58 CCIfInReg<CCIfSubtarget<"hasSSE2()",
59 CCIfType<[f32, f64], CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
60 CCIfType<[f32,f64], CCAssignToReg<[ST0, ST1]>>,
61 CCDelegateTo<RetCC_X86Common>
64 // X86-32 FastCC return-value convention.
65 def RetCC_X86_32_Fast : CallingConv<[
66 // The X86-32 fastcc returns 1, 2, or 3 FP values in XMM0-2 if the target has
68 // This can happen when a float, 2 x float, or 3 x float vector is split by
69 // target lowering, and is returned in 1-3 sse regs.
70 CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
71 CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
73 // For integers, ECX can be used as an extra return register
74 CCIfType<[i8], CCAssignToReg<[AL, DL, CL]>>,
75 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>,
76 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>,
78 // Otherwise, it is the same as the common X86 calling convention.
79 CCDelegateTo<RetCC_X86Common>
82 // X86-64 C return-value convention.
83 def RetCC_X86_64_C : CallingConv<[
84 // The X86-64 calling convention always returns FP values in XMM0.
85 CCIfType<[f32], CCAssignToReg<[XMM0, XMM1]>>,
86 CCIfType<[f64], CCAssignToReg<[XMM0, XMM1]>>,
88 // MMX vector types are always returned in XMM0 except for v1i64 which is
89 // returned in RAX. This disagrees with ABI documentation but is bug
90 // compatible with gcc.
91 CCIfType<[v1i64], CCAssignToReg<[RAX]>>,
92 CCIfType<[v8i8, v4i16, v2i32, v2f32], CCAssignToReg<[XMM0, XMM1]>>,
93 CCDelegateTo<RetCC_X86Common>
96 // X86-Win64 C return-value convention.
97 def RetCC_X86_Win64_C : CallingConv<[
98 // The X86-Win64 calling convention always returns __m64 values in RAX.
99 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCBitConvertToType<i64>>,
101 // And FP in XMM0 only.
102 CCIfType<[f32], CCAssignToReg<[XMM0]>>,
103 CCIfType<[f64], CCAssignToReg<[XMM0]>>,
105 // Otherwise, everything is the same as 'normal' X86-64 C CC.
106 CCDelegateTo<RetCC_X86_64_C>
110 // This is the root return-value convention for the X86-32 backend.
111 def RetCC_X86_32 : CallingConv<[
112 // If FastCC, use RetCC_X86_32_Fast.
113 CCIfCC<"CallingConv::Fast", CCDelegateTo<RetCC_X86_32_Fast>>,
114 // Otherwise, use RetCC_X86_32_C.
115 CCDelegateTo<RetCC_X86_32_C>
118 // This is the root return-value convention for the X86-64 backend.
119 def RetCC_X86_64 : CallingConv<[
120 // Mingw64 and native Win64 use Win64 CC
121 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<RetCC_X86_Win64_C>>,
123 // Otherwise, drop to normal X86-64 CC
124 CCDelegateTo<RetCC_X86_64_C>
127 // This is the return-value convention used for the entire X86 backend.
128 def RetCC_X86 : CallingConv<[
129 CCIfSubtarget<"is64Bit()", CCDelegateTo<RetCC_X86_64>>,
130 CCDelegateTo<RetCC_X86_32>
133 //===----------------------------------------------------------------------===//
134 // X86-64 Argument Calling Conventions
135 //===----------------------------------------------------------------------===//
137 def CC_X86_64_C : CallingConv<[
138 // Handles byval parameters.
139 CCIfByVal<CCPassByVal<8, 8>>,
141 // Promote i8/i16 arguments to i32.
142 CCIfType<[i8, i16], CCPromoteToType<i32>>,
144 // The 'nest' parameter, if any, is passed in R10.
145 CCIfNest<CCAssignToReg<[R10]>>,
147 // The first 6 v1i64 vector arguments are passed in GPRs on Darwin.
149 CCIfSubtarget<"isTargetDarwin()",
150 CCBitConvertToType<i64>>>,
152 // The first 6 integer arguments are passed in integer registers.
153 CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D, R9D]>>,
154 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
156 // The first 8 MMX (except for v1i64) vector arguments are passed in XMM
157 // registers on Darwin.
158 CCIfType<[v8i8, v4i16, v2i32, v2f32],
159 CCIfSubtarget<"isTargetDarwin()",
160 CCIfSubtarget<"hasSSE2()",
161 CCPromoteToType<v2i64>>>>,
163 // The first 8 FP/Vector arguments are passed in XMM registers.
164 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
165 CCIfSubtarget<"hasSSE1()",
166 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>,
168 // Integer/FP values get stored in stack slots that are 8 bytes in size and
169 // 8-byte aligned if there are no more registers to hold them.
170 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
172 // Long doubles get stack slots whose size and alignment depends on the
174 CCIfType<[f80], CCAssignToStack<0, 0>>,
176 // Vectors get 16-byte stack slots that are 16-byte aligned.
177 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
179 // __m64 vectors get 8-byte stack slots that are 8-byte aligned.
180 CCIfType<[v8i8, v4i16, v2i32, v1i64, v2f32], CCAssignToStack<8, 8>>
183 // Calling convention used on Win64
184 def CC_X86_Win64_C : CallingConv<[
185 // FIXME: Handle byval stuff.
186 // FIXME: Handle varargs.
188 // Promote i8/i16 arguments to i32.
189 CCIfType<[i8, i16], CCPromoteToType<i32>>,
191 // The 'nest' parameter, if any, is passed in R10.
192 CCIfNest<CCAssignToReg<[R10]>>,
194 // 128 bit vectors are passed by pointer
195 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCPassIndirect<i64>>,
197 // The first 4 MMX vector arguments are passed in GPRs.
198 CCIfType<[v8i8, v4i16, v2i32, v1i64, v2f32],
199 CCBitConvertToType<i64>>,
201 // The first 4 integer arguments are passed in integer registers.
202 CCIfType<[i32], CCAssignToRegWithShadow<[ECX , EDX , R8D , R9D ],
203 [XMM0, XMM1, XMM2, XMM3]>>,
204 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
205 [XMM0, XMM1, XMM2, XMM3]>>,
207 // The first 4 FP/Vector arguments are passed in XMM registers.
208 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
209 CCAssignToRegWithShadow<[XMM0, XMM1, XMM2, XMM3],
210 [RCX , RDX , R8 , R9 ]>>,
212 // Integer/FP values get stored in stack slots that are 8 bytes in size and
213 // 8-byte aligned if there are no more registers to hold them.
214 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
216 // Long doubles get stack slots whose size and alignment depends on the
218 CCIfType<[f80], CCAssignToStack<0, 0>>,
220 // __m64 vectors get 8-byte stack slots that are 8-byte aligned.
221 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 8>>
224 def CC_X86_64_GHC : CallingConv<[
225 // Promote i8/i16/i32 arguments to i64.
226 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
228 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim
230 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
232 // Pass in STG registers: F1, F2, F3, F4, D1, D2
233 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
234 CCIfSubtarget<"hasSSE1()",
235 CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>
238 //===----------------------------------------------------------------------===//
239 // X86 C Calling Convention
240 //===----------------------------------------------------------------------===//
242 /// CC_X86_32_Common - In all X86-32 calling conventions, extra integers and FP
243 /// values are spilled on the stack, and the first 4 vector values go in XMM
245 def CC_X86_32_Common : CallingConv<[
246 // Handles byval parameters.
247 CCIfByVal<CCPassByVal<4, 4>>,
249 // The first 3 float or double arguments, if marked 'inreg' and if the call
250 // is not a vararg call and if SSE2 is available, are passed in SSE registers.
251 CCIfNotVarArg<CCIfInReg<CCIfType<[f32,f64],
252 CCIfSubtarget<"hasSSE2()",
253 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>>,
255 // The first 3 __m64 (except for v1i64) vector arguments are passed in mmx
256 // registers if the call is not a vararg call.
257 CCIfNotVarArg<CCIfType<[v8i8, v4i16, v2i32, v2f32],
258 CCAssignToReg<[MM0, MM1, MM2]>>>,
260 // Integer/Float values get stored in stack slots that are 4 bytes in
261 // size and 4-byte aligned.
262 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
264 // Doubles get 8-byte slots that are 4-byte aligned.
265 CCIfType<[f64], CCAssignToStack<8, 4>>,
267 // Long doubles get slots whose size depends on the subtarget.
268 CCIfType<[f80], CCAssignToStack<0, 4>>,
270 // The first 4 SSE vector arguments are passed in XMM registers.
271 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
272 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>>,
274 // Other SSE vectors get 16-byte stack slots that are 16-byte aligned.
275 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
277 // __m64 vectors get 8-byte stack slots that are 4-byte aligned. They are
278 // passed in the parameter area.
279 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 4>>]>;
281 def CC_X86_32_C : CallingConv<[
282 // Promote i8/i16 arguments to i32.
283 CCIfType<[i8, i16], CCPromoteToType<i32>>,
285 // The 'nest' parameter, if any, is passed in ECX.
286 CCIfNest<CCAssignToReg<[ECX]>>,
288 // The first 3 integer arguments, if marked 'inreg' and if the call is not
289 // a vararg call, are passed in integer registers.
290 CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>>>,
292 // Otherwise, same as everything else.
293 CCDelegateTo<CC_X86_32_Common>
296 def CC_X86_32_FastCall : CallingConv<[
297 // Promote i8/i16 arguments to i32.
298 CCIfType<[i8, i16], CCPromoteToType<i32>>,
300 // The 'nest' parameter, if any, is passed in EAX.
301 CCIfNest<CCAssignToReg<[EAX]>>,
303 // The first 2 integer arguments are passed in ECX/EDX
304 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>,
306 // Otherwise, same as everything else.
307 CCDelegateTo<CC_X86_32_Common>
310 def CC_X86_32_FastCC : CallingConv<[
311 // Handles byval parameters. Note that we can't rely on the delegation
312 // to CC_X86_32_Common for this because that happens after code that
313 // puts arguments in registers.
314 CCIfByVal<CCPassByVal<4, 4>>,
316 // Promote i8/i16 arguments to i32.
317 CCIfType<[i8, i16], CCPromoteToType<i32>>,
319 // The 'nest' parameter, if any, is passed in EAX.
320 CCIfNest<CCAssignToReg<[EAX]>>,
322 // The first 2 integer arguments are passed in ECX/EDX
323 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>,
325 // The first 3 float or double arguments, if the call is not a vararg
326 // call and if SSE2 is available, are passed in SSE registers.
327 CCIfNotVarArg<CCIfType<[f32,f64],
328 CCIfSubtarget<"hasSSE2()",
329 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
331 // Doubles get 8-byte slots that are 8-byte aligned.
332 CCIfType<[f64], CCAssignToStack<8, 8>>,
334 // Otherwise, same as everything else.
335 CCDelegateTo<CC_X86_32_Common>
338 def CC_X86_32_GHC : CallingConv<[
339 // Promote i8/i16 arguments to i32.
340 CCIfType<[i8, i16], CCPromoteToType<i32>>,
342 // Pass in STG registers: Base, Sp, Hp, R1
343 CCIfType<[i32], CCAssignToReg<[EBX, EBP, EDI, ESI]>>