1 //===- X86CallingConv.td - Calling Conventions X86 32/64 ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This describes the calling conventions for the X86-32 and X86-64
13 //===----------------------------------------------------------------------===//
15 /// CCIfSubtarget - Match if the current subtarget has a feature F.
16 class CCIfSubtarget<string F, CCAction A>
17 : CCIf<!strconcat("State.getTarget().getSubtarget<X86Subtarget>().", F), A>;
19 //===----------------------------------------------------------------------===//
20 // Return Value Calling Conventions
21 //===----------------------------------------------------------------------===//
23 // Return-value conventions common to all X86 CC's.
24 def RetCC_X86Common : CallingConv<[
25 // Scalar values are returned in AX first, then DX, except for i8 where
26 // the convention is to return values in AL and AH. However, using AL and
27 // is AH problematic -- a return of {i16,i8} would end up using AX and AH,
28 // and one value would clobber the other. C front-ends are currently expected
29 // to pack two i8 values into an i16 in the rare situations where this
31 CCIfType<[i8] , CCAssignToReg<[AL]>>,
32 CCIfType<[i16], CCAssignToReg<[AX, DX]>>,
33 CCIfType<[i32], CCAssignToReg<[EAX, EDX]>>,
34 CCIfType<[i64], CCAssignToReg<[RAX, RDX]>>,
36 // Vector types are returned in XMM0 and XMM1, when they fit. XMMM2 and XMM3
37 // can only be used by ABI non-compliant code. If the target doesn't have XMM
38 // registers, it won't have vector types.
39 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
40 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,
42 // MMX vector types are always returned in MM0. If the target doesn't have
43 // MM0, it doesn't support these vector types.
44 CCIfType<[v8i8, v4i16, v2i32, v1i64, v2f32], CCAssignToReg<[MM0]>>,
46 // Long double types are always returned in ST0 (even with SSE).
47 CCIfType<[f80], CCAssignToReg<[ST0, ST1]>>
50 // X86-32 C return-value convention.
51 def RetCC_X86_32_C : CallingConv<[
52 // The X86-32 calling convention returns FP values in ST0, unless marked
53 // with "inreg" (used here to distinguish one kind of reg from another,
54 // weirdly; this is really the sse-regparm calling convention) in which
55 // case they use XMM0, otherwise it is the same as the common X86 calling
57 CCIfInReg<CCIfSubtarget<"hasSSE2()",
58 CCIfType<[f32, f64], CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
59 CCIfType<[f32,f64], CCAssignToReg<[ST0, ST1]>>,
60 CCDelegateTo<RetCC_X86Common>
63 // X86-32 FastCC return-value convention.
64 def RetCC_X86_32_Fast : CallingConv<[
65 // The X86-32 fastcc returns 1, 2, or 3 FP values in XMM0-2 if the target has
66 // SSE2, otherwise it is the the C calling conventions.
67 // This can happen when a float, 2 x float, or 3 x float vector is split by
68 // target lowering, and is returned in 1-3 sse regs.
69 CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
70 CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
71 CCDelegateTo<RetCC_X86Common>
74 // X86-64 C return-value convention.
75 def RetCC_X86_64_C : CallingConv<[
76 // The X86-64 calling convention always returns FP values in XMM0.
77 CCIfType<[f32], CCAssignToReg<[XMM0, XMM1]>>,
78 CCIfType<[f64], CCAssignToReg<[XMM0, XMM1]>>,
80 // MMX vector types are always returned in XMM0 except for v1i64 which is
81 // returned in RAX. This disagrees with ABI documentation but is bug
82 // compatible with gcc.
83 CCIfType<[v1i64], CCAssignToReg<[RAX]>>,
84 CCIfType<[v8i8, v4i16, v2i32, v2f32], CCAssignToReg<[XMM0, XMM1]>>,
85 CCDelegateTo<RetCC_X86Common>
88 // X86-Win64 C return-value convention.
89 def RetCC_X86_Win64_C : CallingConv<[
90 // The X86-Win64 calling convention always returns __m64 values in RAX.
91 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToReg<[RAX]>>,
93 // And FP in XMM0 only.
94 CCIfType<[f32], CCAssignToReg<[XMM0]>>,
95 CCIfType<[f64], CCAssignToReg<[XMM0]>>,
97 // Otherwise, everything is the same as 'normal' X86-64 C CC.
98 CCDelegateTo<RetCC_X86_64_C>
102 // This is the root return-value convention for the X86-32 backend.
103 def RetCC_X86_32 : CallingConv<[
104 // If FastCC, use RetCC_X86_32_Fast.
105 CCIfCC<"CallingConv::Fast", CCDelegateTo<RetCC_X86_32_Fast>>,
106 // Otherwise, use RetCC_X86_32_C.
107 CCDelegateTo<RetCC_X86_32_C>
110 // This is the root return-value convention for the X86-64 backend.
111 def RetCC_X86_64 : CallingConv<[
112 // Mingw64 and native Win64 use Win64 CC
113 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<RetCC_X86_Win64_C>>,
115 // Otherwise, drop to normal X86-64 CC
116 CCDelegateTo<RetCC_X86_64_C>
119 // This is the return-value convention used for the entire X86 backend.
120 def RetCC_X86 : CallingConv<[
121 CCIfSubtarget<"is64Bit()", CCDelegateTo<RetCC_X86_64>>,
122 CCDelegateTo<RetCC_X86_32>
125 //===----------------------------------------------------------------------===//
126 // X86-64 Argument Calling Conventions
127 //===----------------------------------------------------------------------===//
129 def CC_X86_64_C : CallingConv<[
130 // Handles byval parameters.
131 CCIfByVal<CCPassByVal<8, 8>>,
133 // Promote i8/i16 arguments to i32.
134 CCIfType<[i8, i16], CCPromoteToType<i32>>,
136 // The 'nest' parameter, if any, is passed in R10.
137 CCIfNest<CCAssignToReg<[R10]>>,
139 // The first 6 integer arguments are passed in integer registers.
140 CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D, R9D]>>,
141 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
143 // The first 8 FP/Vector arguments are passed in XMM registers.
144 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
145 CCIfSubtarget<"hasSSE1()",
146 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>,
148 // The first 8 MMX (except for v1i64) vector arguments are passed in XMM
149 // registers on Darwin.
150 CCIfType<[v8i8, v4i16, v2i32, v2f32],
151 CCIfSubtarget<"isTargetDarwin()",
152 CCIfSubtarget<"hasSSE2()",
153 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>>,
155 // The first 8 v1i64 vector arguments are passed in GPRs on Darwin.
157 CCIfSubtarget<"isTargetDarwin()",
158 CCAssignToReg<[RDI, RSI, RDX, RCX, R8]>>>,
160 // Integer/FP values get stored in stack slots that are 8 bytes in size and
161 // 8-byte aligned if there are no more registers to hold them.
162 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
164 // Long doubles get stack slots whose size and alignment depends on the
166 CCIfType<[f80], CCAssignToStack<0, 0>>,
168 // Vectors get 16-byte stack slots that are 16-byte aligned.
169 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
171 // __m64 vectors get 8-byte stack slots that are 8-byte aligned.
172 CCIfType<[v8i8, v4i16, v2i32, v1i64, v2f32], CCAssignToStack<8, 8>>
175 // Calling convention used on Win64
176 def CC_X86_Win64_C : CallingConv<[
177 // FIXME: Handle byval stuff.
178 // FIXME: Handle varargs.
180 // Promote i8/i16 arguments to i32.
181 CCIfType<[i8, i16], CCPromoteToType<i32>>,
183 // The 'nest' parameter, if any, is passed in R10.
184 CCIfNest<CCAssignToReg<[R10]>>,
186 // The first 4 integer arguments are passed in integer registers.
187 CCIfType<[i32], CCAssignToRegWithShadow<[ECX , EDX , R8D , R9D ],
188 [XMM0, XMM1, XMM2, XMM3]>>,
189 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
190 [XMM0, XMM1, XMM2, XMM3]>>,
192 // The first 4 FP/Vector arguments are passed in XMM registers.
193 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
194 CCAssignToRegWithShadow<[XMM0, XMM1, XMM2, XMM3],
195 [RCX , RDX , R8 , R9 ]>>,
197 // The first 4 MMX vector arguments are passed in GPRs.
198 CCIfType<[v8i8, v4i16, v2i32, v1i64, v2f32],
199 CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
200 [XMM0, XMM1, XMM2, XMM3]>>,
202 // Integer/FP values get stored in stack slots that are 8 bytes in size and
203 // 16-byte aligned if there are no more registers to hold them.
204 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 16>>,
206 // Long doubles get stack slots whose size and alignment depends on the
208 CCIfType<[f80], CCAssignToStack<0, 0>>,
210 // Vectors get 16-byte stack slots that are 16-byte aligned.
211 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
213 // __m64 vectors get 8-byte stack slots that are 16-byte aligned.
214 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 16>>
217 // Tail call convention (fast): One register is reserved for target address,
219 def CC_X86_64_TailCall : CallingConv<[
220 // Handles byval parameters.
221 CCIfByVal<CCPassByVal<8, 8>>,
223 // Promote i8/i16 arguments to i32.
224 CCIfType<[i8, i16], CCPromoteToType<i32>>,
226 // The 'nest' parameter, if any, is passed in R10.
227 CCIfNest<CCAssignToReg<[R10]>>,
229 // The first 6 integer arguments are passed in integer registers.
230 CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D]>>,
231 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8]>>,
233 // The first 8 FP/Vector arguments are passed in XMM registers.
234 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
235 CCIfSubtarget<"hasSSE1()",
236 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>,
238 // The first 8 MMX (except for v1i64) vector arguments are passed in XMM
239 // registers on Darwin.
240 CCIfType<[v8i8, v4i16, v2i32, v2f32],
241 CCIfSubtarget<"isTargetDarwin()",
242 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>,
244 // The first 8 v1i64 vector arguments are passed in GPRs on Darwin.
246 CCIfSubtarget<"isTargetDarwin()",
247 CCAssignToReg<[RDI, RSI, RDX, RCX, R8]>>>,
249 // Integer/FP values get stored in stack slots that are 8 bytes in size and
250 // 8-byte aligned if there are no more registers to hold them.
251 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
253 // Vectors get 16-byte stack slots that are 16-byte aligned.
254 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
256 // __m64 vectors get 8-byte stack slots that are 8-byte aligned.
257 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 8>>
261 //===----------------------------------------------------------------------===//
262 // X86 C Calling Convention
263 //===----------------------------------------------------------------------===//
265 /// CC_X86_32_Common - In all X86-32 calling conventions, extra integers and FP
266 /// values are spilled on the stack, and the first 4 vector values go in XMM
268 def CC_X86_32_Common : CallingConv<[
269 // Handles byval parameters.
270 CCIfByVal<CCPassByVal<4, 4>>,
272 // The first 3 float or double arguments, if marked 'inreg' and if the call
273 // is not a vararg call and if SSE2 is available, are passed in SSE registers.
274 CCIfNotVarArg<CCIfInReg<CCIfType<[f32,f64],
275 CCIfSubtarget<"hasSSE2()",
276 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>>,
278 // The first 3 __m64 (except for v1i64) vector arguments are passed in mmx
279 // registers if the call is not a vararg call.
280 CCIfNotVarArg<CCIfType<[v8i8, v4i16, v2i32, v2f32],
281 CCAssignToReg<[MM0, MM1, MM2]>>>,
283 // Integer/Float values get stored in stack slots that are 4 bytes in
284 // size and 4-byte aligned.
285 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
287 // Doubles get 8-byte slots that are 4-byte aligned.
288 CCIfType<[f64], CCAssignToStack<8, 4>>,
290 // Long doubles get slots whose size depends on the subtarget.
291 CCIfType<[f80], CCAssignToStack<0, 4>>,
293 // The first 4 SSE vector arguments are passed in XMM registers.
294 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
295 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>>,
297 // Other SSE vectors get 16-byte stack slots that are 16-byte aligned.
298 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
300 // __m64 vectors get 8-byte stack slots that are 4-byte aligned. They are
301 // passed in the parameter area.
302 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 4>>]>;
304 def CC_X86_32_C : CallingConv<[
305 // Promote i8/i16 arguments to i32.
306 CCIfType<[i8, i16], CCPromoteToType<i32>>,
308 // The 'nest' parameter, if any, is passed in ECX.
309 CCIfNest<CCAssignToReg<[ECX]>>,
311 // The first 3 integer arguments, if marked 'inreg' and if the call is not
312 // a vararg call, are passed in integer registers.
313 CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>>>,
315 // Otherwise, same as everything else.
316 CCDelegateTo<CC_X86_32_Common>
319 def CC_X86_32_FastCall : CallingConv<[
320 // Promote i8/i16 arguments to i32.
321 CCIfType<[i8, i16], CCPromoteToType<i32>>,
323 // The 'nest' parameter, if any, is passed in EAX.
324 CCIfNest<CCAssignToReg<[EAX]>>,
326 // The first 2 integer arguments are passed in ECX/EDX
327 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>,
329 // Otherwise, same as everything else.
330 CCDelegateTo<CC_X86_32_Common>
333 def CC_X86_32_FastCC : CallingConv<[
334 // Handles byval parameters. Note that we can't rely on the delegation
335 // to CC_X86_32_Common for this because that happens after code that
336 // puts arguments in registers.
337 CCIfByVal<CCPassByVal<4, 4>>,
339 // Promote i8/i16 arguments to i32.
340 CCIfType<[i8, i16], CCPromoteToType<i32>>,
342 // The 'nest' parameter, if any, is passed in EAX.
343 CCIfNest<CCAssignToReg<[EAX]>>,
345 // The first 2 integer arguments are passed in ECX/EDX
346 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>,
348 // The first 3 float or double arguments, if the call is not a vararg
349 // call and if SSE2 is available, are passed in SSE registers.
350 CCIfNotVarArg<CCIfType<[f32,f64],
351 CCIfSubtarget<"hasSSE2()",
352 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
354 // Doubles get 8-byte slots that are 8-byte aligned.
355 CCIfType<[f64], CCAssignToStack<8, 8>>,
357 // Otherwise, same as everything else.
358 CCDelegateTo<CC_X86_32_Common>