1 //===- X86CallingConv.td - Calling Conventions X86 32/64 ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This describes the calling conventions for the X86-32 and X86-64
13 //===----------------------------------------------------------------------===//
15 /// CCIfSubtarget - Match if the current subtarget has a feature F.
16 class CCIfSubtarget<string F, CCAction A>
17 : CCIf<!strconcat("State.getTarget().getSubtarget<X86Subtarget>().", F), A>;
19 //===----------------------------------------------------------------------===//
20 // Return Value Calling Conventions
21 //===----------------------------------------------------------------------===//
23 // Return-value conventions common to all X86 CC's.
24 def RetCC_X86Common : CallingConv<[
25 // Scalar values are returned in AX first, then DX.
26 CCIfType<[i8] , CCAssignToReg<[AL]>>,
27 CCIfType<[i16], CCAssignToReg<[AX, DX]>>,
28 CCIfType<[i32], CCAssignToReg<[EAX, EDX]>>,
29 CCIfType<[i64], CCAssignToReg<[RAX, RDX]>>,
31 // Vector types are returned in XMM0 and XMM1, when they fit. If the target
32 // doesn't have XMM registers, it won't have vector types.
33 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
34 CCAssignToReg<[XMM0,XMM1]>>,
36 // MMX vector types are always returned in MM0. If the target doesn't have
37 // MM0, it doesn't support these vector types.
38 CCIfType<[v8i8, v4i16, v2i32, v1i64, v2f32], CCAssignToReg<[MM0]>>,
40 // Long double types are always returned in ST0 (even with SSE).
41 CCIfType<[f80], CCAssignToReg<[ST0, ST1]>>
44 // X86-32 C return-value convention.
45 def RetCC_X86_32_C : CallingConv<[
46 // The X86-32 calling convention returns FP values in ST0, otherwise it is the
47 // same as the common X86 calling conv.
48 CCIfType<[f32], CCAssignToReg<[ST0, ST1]>>,
49 CCIfType<[f64], CCAssignToReg<[ST0, ST1]>>,
50 CCDelegateTo<RetCC_X86Common>
53 // X86-32 FastCC return-value convention.
54 def RetCC_X86_32_Fast : CallingConv<[
55 // The X86-32 fastcc returns 1, 2, or 3 FP values in XMM0-2 if the target has
56 // SSE2, otherwise it is the the C calling conventions.
57 // This can happen when a float, 2 x float, or 3 x float vector is split by
58 // target lowering, and is returned in 1-3 sse regs.
59 CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
60 CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
61 CCDelegateTo<RetCC_X86Common>
64 // X86-32 SSEregparm return-value convention.
65 def RetCC_X86_32_SSE : CallingConv<[
66 // The X86-32 sseregparm calling convention returns FP values in XMM0 if the
67 // target has SSE2, otherwise it is the C calling convention.
68 CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0, XMM1]>>>,
69 CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0, XMM1]>>>,
70 CCDelegateTo<RetCC_X86Common>
73 // X86-64 C return-value convention.
74 def RetCC_X86_64_C : CallingConv<[
75 // The X86-64 calling convention always returns FP values in XMM0.
76 CCIfType<[f32], CCAssignToReg<[XMM0, XMM1]>>,
77 CCIfType<[f64], CCAssignToReg<[XMM0, XMM1]>>,
79 // MMX vector types are always returned in XMM0.
80 CCIfType<[v8i8, v4i16, v2i32, v1i64, v2f32], CCAssignToReg<[XMM0, XMM1]>>,
81 CCDelegateTo<RetCC_X86Common>
84 // X86-Win64 C return-value convention.
85 def RetCC_X86_Win64_C : CallingConv<[
86 // The X86-Win64 calling convention always returns __m64 values in RAX.
87 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToReg<[RAX]>>,
89 // And FP in XMM0 only.
90 CCIfType<[f32], CCAssignToReg<[XMM0]>>,
91 CCIfType<[f64], CCAssignToReg<[XMM0]>>,
93 // Otherwise, everything is the same as 'normal' X86-64 C CC.
94 CCDelegateTo<RetCC_X86_64_C>
98 // This is the root return-value convention for the X86-32 backend.
99 def RetCC_X86_32 : CallingConv<[
100 // If FastCC, use RetCC_X86_32_Fast.
101 CCIfCC<"CallingConv::Fast", CCDelegateTo<RetCC_X86_32_Fast>>,
102 // If SSECC, use RetCC_X86_32_SSE.
103 CCIfCC<"CallingConv::X86_SSECall", CCDelegateTo<RetCC_X86_32_SSE>>,
104 // Otherwise, use RetCC_X86_32_C.
105 CCDelegateTo<RetCC_X86_32_C>
108 // This is the root return-value convention for the X86-64 backend.
109 def RetCC_X86_64 : CallingConv<[
110 // Mingw64 and native Win64 use Win64 CC
111 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<RetCC_X86_Win64_C>>,
113 // Otherwise, drop to normal X86-64 CC
114 CCDelegateTo<RetCC_X86_64_C>
117 // This is the return-value convention used for the entire X86 backend.
118 def RetCC_X86 : CallingConv<[
119 CCIfSubtarget<"is64Bit()", CCDelegateTo<RetCC_X86_64>>,
120 CCDelegateTo<RetCC_X86_32>
123 //===----------------------------------------------------------------------===//
124 // X86-64 Argument Calling Conventions
125 //===----------------------------------------------------------------------===//
127 def CC_X86_64_C : CallingConv<[
128 // Handles byval parameters.
129 CCIfByVal<CCPassByVal<8, 8>>,
131 // Promote i8/i16 arguments to i32.
132 CCIfType<[i8, i16], CCPromoteToType<i32>>,
134 // The 'nest' parameter, if any, is passed in R10.
135 CCIfNest<CCAssignToReg<[R10]>>,
137 // The first 6 integer arguments are passed in integer registers.
138 CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D, R9D]>>,
139 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
141 // The first 8 FP/Vector arguments are passed in XMM registers.
142 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
143 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>,
145 // The first 8 MMX (except for v1i64) vector arguments are passed in XMM
146 // registers on Darwin.
147 CCIfType<[v8i8, v4i16, v2i32, v2f32],
148 CCIfSubtarget<"isTargetDarwin()",
149 CCIfSubtarget<"hasSSE2()",
150 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>>,
152 // The first 8 v1i64 vector arguments are passed in GPRs on Darwin.
154 CCIfSubtarget<"isTargetDarwin()",
155 CCAssignToReg<[RDI, RSI, RDX, RCX, R8]>>>,
157 // Integer/FP values get stored in stack slots that are 8 bytes in size and
158 // 8-byte aligned if there are no more registers to hold them.
159 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
161 // Long doubles get stack slots whose size and alignment depends on the
163 CCIfType<[f80], CCAssignToStack<0, 0>>,
165 // Vectors get 16-byte stack slots that are 16-byte aligned.
166 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
168 // __m64 vectors get 8-byte stack slots that are 8-byte aligned.
169 CCIfType<[v8i8, v4i16, v2i32, v1i64, v2f32], CCAssignToStack<8, 8>>
172 // Calling convention used on Win64
173 def CC_X86_Win64_C : CallingConv<[
174 // FIXME: Handle byval stuff.
175 // FIXME: Handle varargs.
177 // Promote i8/i16 arguments to i32.
178 CCIfType<[i8, i16], CCPromoteToType<i32>>,
180 // The 'nest' parameter, if any, is passed in R10.
181 CCIfNest<CCAssignToReg<[R10]>>,
183 // The first 4 integer arguments are passed in integer registers.
184 CCIfType<[i32], CCAssignToRegWithShadow<[ECX , EDX , R8D , R9D ],
185 [XMM0, XMM1, XMM2, XMM3]>>,
186 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
187 [XMM0, XMM1, XMM2, XMM3]>>,
189 // The first 4 FP/Vector arguments are passed in XMM registers.
190 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
191 CCAssignToRegWithShadow<[XMM0, XMM1, XMM2, XMM3],
192 [RCX , RDX , R8 , R9 ]>>,
194 // The first 4 MMX vector arguments are passed in GPRs.
195 CCIfType<[v8i8, v4i16, v2i32, v1i64, v2f32],
196 CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
197 [XMM0, XMM1, XMM2, XMM3]>>,
199 // Integer/FP values get stored in stack slots that are 8 bytes in size and
200 // 16-byte aligned if there are no more registers to hold them.
201 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 16>>,
203 // Long doubles get stack slots whose size and alignment depends on the
205 CCIfType<[f80], CCAssignToStack<0, 0>>,
207 // Vectors get 16-byte stack slots that are 16-byte aligned.
208 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
210 // __m64 vectors get 8-byte stack slots that are 16-byte aligned.
211 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 16>>
214 // Tail call convention (fast): One register is reserved for target address,
216 def CC_X86_64_TailCall : CallingConv<[
217 // Handles byval parameters.
218 CCIfByVal<CCPassByVal<8, 8>>,
220 // Promote i8/i16 arguments to i32.
221 CCIfType<[i8, i16], CCPromoteToType<i32>>,
223 // The 'nest' parameter, if any, is passed in R10.
224 CCIfNest<CCAssignToReg<[R10]>>,
226 // The first 6 integer arguments are passed in integer registers.
227 CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D]>>,
228 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8]>>,
230 // The first 8 FP/Vector arguments are passed in XMM registers.
231 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
232 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>,
234 // The first 8 MMX (except for v1i64) vector arguments are passed in XMM
235 // registers on Darwin.
236 CCIfType<[v8i8, v4i16, v2i32, v2f32],
237 CCIfSubtarget<"isTargetDarwin()",
238 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>,
240 // The first 8 v1i64 vector arguments are passed in GPRs on Darwin.
242 CCIfSubtarget<"isTargetDarwin()",
243 CCAssignToReg<[RDI, RSI, RDX, RCX, R8]>>>,
245 // Integer/FP values get stored in stack slots that are 8 bytes in size and
246 // 8-byte aligned if there are no more registers to hold them.
247 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
249 // Vectors get 16-byte stack slots that are 16-byte aligned.
250 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
252 // __m64 vectors get 8-byte stack slots that are 8-byte aligned.
253 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 8>>
257 //===----------------------------------------------------------------------===//
258 // X86 C Calling Convention
259 //===----------------------------------------------------------------------===//
261 /// CC_X86_32_Common - In all X86-32 calling conventions, extra integers and FP
262 /// values are spilled on the stack, and the first 4 vector values go in XMM
264 def CC_X86_32_Common : CallingConv<[
265 // Handles byval parameters.
266 CCIfByVal<CCPassByVal<4, 4>>,
268 // The first 3 float or double arguments, if marked 'inreg' and if the call
269 // is not a vararg call and if SSE2 is available, are passed in SSE registers.
270 CCIfNotVarArg<CCIfInReg<CCIfType<[f32,f64],
271 CCIfSubtarget<"hasSSE2()",
272 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>>,
274 // The first 3 __m64 (except for v1i64) vector arguments are passed in mmx
275 // registers if the call is not a vararg call.
276 CCIfNotVarArg<CCIfType<[v8i8, v4i16, v2i32, v2f32],
277 CCAssignToReg<[MM0, MM1, MM2]>>>,
279 // Integer/Float values get stored in stack slots that are 4 bytes in
280 // size and 4-byte aligned.
281 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
283 // Doubles get 8-byte slots that are 4-byte aligned.
284 CCIfType<[f64], CCAssignToStack<8, 4>>,
286 // Long doubles get slots whose size depends on the subtarget.
287 CCIfType<[f80], CCAssignToStack<0, 4>>,
289 // The first 4 SSE vector arguments are passed in XMM registers.
290 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
291 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>>,
293 // Other SSE vectors get 16-byte stack slots that are 16-byte aligned.
294 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
296 // __m64 vectors get 8-byte stack slots that are 4-byte aligned. They are
297 // passed in the parameter area.
298 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 4>>]>;
300 def CC_X86_32_C : CallingConv<[
301 // Promote i8/i16 arguments to i32.
302 CCIfType<[i8, i16], CCPromoteToType<i32>>,
304 // The 'nest' parameter, if any, is passed in ECX.
305 CCIfNest<CCAssignToReg<[ECX]>>,
307 // The first 3 integer arguments, if marked 'inreg' and if the call is not
308 // a vararg call, are passed in integer registers.
309 CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>>>,
311 // Otherwise, same as everything else.
312 CCDelegateTo<CC_X86_32_Common>
315 /// Same as C calling convention except for non-free ECX which is used for storing
316 /// a potential pointer to the tail called function.
317 def CC_X86_32_TailCall : CallingConv<[
318 // Promote i8/i16 arguments to i32.
319 CCIfType<[i8, i16], CCPromoteToType<i32>>,
321 // Nested function trampolines are currently not supported by fastcc.
323 // The first 3 integer arguments, if marked 'inreg' and if the call is not
324 // a vararg call, are passed in integer registers.
325 CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX]>>>>,
327 // Otherwise, same as everything else.
328 CCDelegateTo<CC_X86_32_Common>
331 def CC_X86_32_FastCall : CallingConv<[
332 // Promote i8/i16 arguments to i32.
333 CCIfType<[i8, i16], CCPromoteToType<i32>>,
335 // The 'nest' parameter, if any, is passed in EAX.
336 CCIfNest<CCAssignToReg<[EAX]>>,
338 // The first 2 integer arguments are passed in ECX/EDX
339 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>,
341 // Otherwise, same as everything else.
342 CCDelegateTo<CC_X86_32_Common>
345 def CC_X86_32_FastCC : CallingConv<[
346 // Promote i8/i16 arguments to i32.
347 CCIfType<[i8, i16], CCPromoteToType<i32>>,
349 // The 'nest' parameter, if any, is passed in EAX.
350 CCIfNest<CCAssignToReg<[EAX]>>,
352 // The first 2 integer arguments are passed in ECX/EDX
353 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>,
355 // The first 3 float or double arguments, if the call is not a vararg
356 // call and if SSE2 is available, are passed in SSE registers.
357 CCIfNotVarArg<CCIfType<[f32,f64],
358 CCIfSubtarget<"hasSSE2()",
359 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
361 // Doubles get 8-byte slots that are 8-byte aligned.
362 CCIfType<[f64], CCAssignToStack<8, 8>>,
364 // Otherwise, same as everything else.
365 CCDelegateTo<CC_X86_32_Common>