1 //===-- X86/X86CodeEmitter.cpp - Convert X86 code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the X86 machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-emitter"
16 #include "X86InstrInfo.h"
17 #include "X86JITInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "X86Relocations.h"
22 #include "llvm/PassManager.h"
23 #include "llvm/CodeGen/MachineCodeEmitter.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/Function.h"
28 #include "llvm/ADT/Statistic.h"
29 #include "llvm/Support/Compiler.h"
30 #include "llvm/Target/TargetOptions.h"
33 STATISTIC(NumEmitted, "Number of machine instructions emitted");
36 class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass {
37 const X86InstrInfo *II;
40 MachineCodeEmitter &MCE;
41 intptr_t PICBaseOffset;
46 explicit Emitter(TargetMachine &tm, MachineCodeEmitter &mce)
47 : MachineFunctionPass((intptr_t)&ID), II(0), TD(0), TM(tm),
48 MCE(mce), PICBaseOffset(0), Is64BitMode(false),
49 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
50 Emitter(TargetMachine &tm, MachineCodeEmitter &mce,
51 const X86InstrInfo &ii, const TargetData &td, bool is64)
52 : MachineFunctionPass((intptr_t)&ID), II(&ii), TD(&td), TM(tm),
53 MCE(mce), PICBaseOffset(0), Is64BitMode(is64),
54 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
56 bool runOnMachineFunction(MachineFunction &MF);
58 virtual const char *getPassName() const {
59 return "X86 Machine Code Emitter";
62 void emitInstruction(const MachineInstr &MI,
63 const TargetInstrDesc *Desc);
66 void emitPCRelativeBlockAddress(MachineBasicBlock *MBB);
67 void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
68 int Disp = 0, intptr_t PCAdj = 0,
69 bool NeedStub = false, bool IsLazy = false);
70 void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
71 void emitConstPoolAddress(unsigned CPI, unsigned Reloc, int Disp = 0,
73 void emitJumpTableAddress(unsigned JTI, unsigned Reloc,
76 void emitDisplacementField(const MachineOperand *RelocOp, int DispVal,
79 void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField);
80 void emitSIBByte(unsigned SS, unsigned Index, unsigned Base);
81 void emitConstant(uint64_t Val, unsigned Size);
83 void emitMemModRMByte(const MachineInstr &MI,
84 unsigned Op, unsigned RegOpcodeField,
87 unsigned getX86RegNum(unsigned RegNo) const;
88 bool isX86_64ExtendedReg(const MachineOperand &MO);
89 unsigned determineREX(const MachineInstr &MI);
91 bool gvNeedsLazyPtr(const GlobalValue *GV);
96 /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
97 /// to the specified MCE object.
98 FunctionPass *llvm::createX86CodeEmitterPass(X86TargetMachine &TM,
99 MachineCodeEmitter &MCE) {
100 return new Emitter(TM, MCE);
103 bool Emitter::runOnMachineFunction(MachineFunction &MF) {
104 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
105 MF.getTarget().getRelocationModel() != Reloc::Static) &&
106 "JIT relocation model must be set to static or default!");
107 II = ((X86TargetMachine&)TM).getInstrInfo();
108 TD = ((X86TargetMachine&)TM).getTargetData();
109 Is64BitMode = TM.getSubtarget<X86Subtarget>().is64Bit();
112 MCE.startFunction(MF);
113 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
115 MCE.StartMachineBasicBlock(MBB);
116 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
118 const TargetInstrDesc &Desc = I->getDesc();
119 emitInstruction(*I, &Desc);
120 // MOVPC32r is basically a call plus a pop instruction.
121 if (Desc.getOpcode() == X86::MOVPC32r)
122 emitInstruction(*I, &II->get(X86::POP32r));
123 NumEmitted++; // Keep track of the # of mi's emitted
126 } while (MCE.finishFunction(MF));
131 /// emitPCRelativeBlockAddress - This method keeps track of the information
132 /// necessary to resolve the address of this block later and emits a dummy
135 void Emitter::emitPCRelativeBlockAddress(MachineBasicBlock *MBB) {
136 // Remember where this reference was and where it is to so we can
137 // deal with it later.
138 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
139 X86::reloc_pcrel_word, MBB));
143 /// emitGlobalAddress - Emit the specified address to the code stream assuming
144 /// this is part of a "take the address of a global" instruction.
146 void Emitter::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
147 int Disp /* = 0 */, intptr_t PCAdj /* = 0 */,
148 bool NeedStub /* = false */,
149 bool isLazy /* = false */) {
150 intptr_t RelocCST = 0;
151 if (Reloc == X86::reloc_picrel_word)
152 RelocCST = PICBaseOffset;
153 else if (Reloc == X86::reloc_pcrel_word)
155 MachineRelocation MR = isLazy
156 ? MachineRelocation::getGVLazyPtr(MCE.getCurrentPCOffset(), Reloc,
157 GV, RelocCST, NeedStub)
158 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
159 GV, RelocCST, NeedStub);
160 MCE.addRelocation(MR);
161 if (Reloc == X86::reloc_absolute_dword)
163 MCE.emitWordLE(Disp); // The relocated value will be added to the displacement
166 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
167 /// be emitted to the current location in the function, and allow it to be PC
169 void Emitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
170 intptr_t RelocCST = (Reloc == X86::reloc_picrel_word) ? PICBaseOffset : 0;
171 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
172 Reloc, ES, RelocCST));
173 if (Reloc == X86::reloc_absolute_dword)
178 /// emitConstPoolAddress - Arrange for the address of an constant pool
179 /// to be emitted to the current location in the function, and allow it to be PC
181 void Emitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc,
183 intptr_t PCAdj /* = 0 */) {
184 intptr_t RelocCST = 0;
185 if (Reloc == X86::reloc_picrel_word)
186 RelocCST = PICBaseOffset;
187 else if (Reloc == X86::reloc_pcrel_word)
189 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
190 Reloc, CPI, RelocCST));
191 if (Reloc == X86::reloc_absolute_dword)
193 MCE.emitWordLE(Disp); // The relocated value will be added to the displacement
196 /// emitJumpTableAddress - Arrange for the address of a jump table to
197 /// be emitted to the current location in the function, and allow it to be PC
199 void Emitter::emitJumpTableAddress(unsigned JTI, unsigned Reloc,
200 intptr_t PCAdj /* = 0 */) {
201 intptr_t RelocCST = 0;
202 if (Reloc == X86::reloc_picrel_word)
203 RelocCST = PICBaseOffset;
204 else if (Reloc == X86::reloc_pcrel_word)
206 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
207 Reloc, JTI, RelocCST));
208 if (Reloc == X86::reloc_absolute_dword)
210 MCE.emitWordLE(0); // The relocated value will be added to the displacement
213 unsigned Emitter::getX86RegNum(unsigned RegNo) const {
214 return ((const X86RegisterInfo&)II->getRegisterInfo()).getX86RegNum(RegNo);
217 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
219 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
220 return RM | (RegOpcode << 3) | (Mod << 6);
223 void Emitter::emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeFld){
224 MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)));
227 void Emitter::emitSIBByte(unsigned SS, unsigned Index, unsigned Base) {
228 // SIB byte is in the same format as the ModRMByte...
229 MCE.emitByte(ModRMByte(SS, Index, Base));
232 void Emitter::emitConstant(uint64_t Val, unsigned Size) {
233 // Output the constant in little endian byte order...
234 for (unsigned i = 0; i != Size; ++i) {
235 MCE.emitByte(Val & 255);
240 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
241 /// sign-extended field.
242 static bool isDisp8(int Value) {
243 return Value == (signed char)Value;
246 bool Emitter::gvNeedsLazyPtr(const GlobalValue *GV) {
247 return !Is64BitMode &&
248 TM.getSubtarget<X86Subtarget>().GVRequiresExtraLoad(GV, TM, false);
251 void Emitter::emitDisplacementField(const MachineOperand *RelocOp,
252 int DispVal, intptr_t PCAdj) {
253 // If this is a simple integer displacement that doesn't require a relocation,
256 emitConstant(DispVal, 4);
260 // Otherwise, this is something that requires a relocation. Emit it as such
262 if (RelocOp->isGlobalAddress()) {
263 // In 64-bit static small code model, we could potentially emit absolute.
264 // But it's probably not beneficial.
265 // 89 05 00 00 00 00 mov %eax,0(%rip) # PC-relative
266 // 89 04 25 00 00 00 00 mov %eax,0x0 # Absolute
267 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
268 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
269 bool NeedStub = isa<Function>(RelocOp->getGlobal());
270 bool isLazy = gvNeedsLazyPtr(RelocOp->getGlobal());
271 emitGlobalAddress(RelocOp->getGlobal(), rt, RelocOp->getOffset(),
272 PCAdj, NeedStub, isLazy);
273 } else if (RelocOp->isConstantPoolIndex()) {
274 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_picrel_word;
275 emitConstPoolAddress(RelocOp->getIndex(), rt,
276 RelocOp->getOffset(), PCAdj);
277 } else if (RelocOp->isJumpTableIndex()) {
278 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_picrel_word;
279 emitJumpTableAddress(RelocOp->getIndex(), rt, PCAdj);
281 assert(0 && "Unknown value to relocate!");
285 void Emitter::emitMemModRMByte(const MachineInstr &MI,
286 unsigned Op, unsigned RegOpcodeField,
288 const MachineOperand &Op3 = MI.getOperand(Op+3);
290 const MachineOperand *DispForReloc = 0;
292 // Figure out what sort of displacement we have to handle here.
293 if (Op3.isGlobalAddress()) {
295 } else if (Op3.isConstantPoolIndex()) {
296 if (Is64BitMode || IsPIC) {
299 DispVal += MCE.getConstantPoolEntryAddress(Op3.getIndex());
300 DispVal += Op3.getOffset();
302 } else if (Op3.isJumpTableIndex()) {
303 if (Is64BitMode || IsPIC) {
306 DispVal += MCE.getJumpTableEntryAddress(Op3.getIndex());
309 DispVal = Op3.getImm();
312 const MachineOperand &Base = MI.getOperand(Op);
313 const MachineOperand &Scale = MI.getOperand(Op+1);
314 const MachineOperand &IndexReg = MI.getOperand(Op+2);
316 unsigned BaseReg = Base.getReg();
318 // Is a SIB byte needed?
319 if (IndexReg.getReg() == 0 &&
320 (BaseReg == 0 || getX86RegNum(BaseReg) != N86::ESP)) {
321 if (BaseReg == 0) { // Just a displacement?
322 // Emit special case [disp32] encoding
323 MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
325 emitDisplacementField(DispForReloc, DispVal, PCAdj);
327 unsigned BaseRegNo = getX86RegNum(BaseReg);
328 if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
329 // Emit simple indirect register encoding... [EAX] f.e.
330 MCE.emitByte(ModRMByte(0, RegOpcodeField, BaseRegNo));
331 } else if (!DispForReloc && isDisp8(DispVal)) {
332 // Emit the disp8 encoding... [REG+disp8]
333 MCE.emitByte(ModRMByte(1, RegOpcodeField, BaseRegNo));
334 emitConstant(DispVal, 1);
336 // Emit the most general non-SIB encoding: [REG+disp32]
337 MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo));
338 emitDisplacementField(DispForReloc, DispVal, PCAdj);
342 } else { // We need a SIB byte, so start by outputting the ModR/M byte first
343 assert(IndexReg.getReg() != X86::ESP &&
344 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
346 bool ForceDisp32 = false;
347 bool ForceDisp8 = false;
349 // If there is no base register, we emit the special case SIB byte with
350 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
351 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
353 } else if (DispForReloc) {
354 // Emit the normal disp32 encoding.
355 MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
357 } else if (DispVal == 0 && getX86RegNum(BaseReg) != N86::EBP) {
358 // Emit no displacement ModR/M byte
359 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
360 } else if (isDisp8(DispVal)) {
361 // Emit the disp8 encoding...
362 MCE.emitByte(ModRMByte(1, RegOpcodeField, 4));
363 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
365 // Emit the normal disp32 encoding...
366 MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
369 // Calculate what the SS field value should be...
370 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
371 unsigned SS = SSTable[Scale.getImm()];
374 // Handle the SIB byte for the case where there is no base. The
375 // displacement has already been output.
376 assert(IndexReg.getReg() && "Index register must be specified!");
377 emitSIBByte(SS, getX86RegNum(IndexReg.getReg()), 5);
379 unsigned BaseRegNo = getX86RegNum(BaseReg);
381 if (IndexReg.getReg())
382 IndexRegNo = getX86RegNum(IndexReg.getReg());
384 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
385 emitSIBByte(SS, IndexRegNo, BaseRegNo);
388 // Do we need to output a displacement?
390 emitConstant(DispVal, 1);
391 } else if (DispVal != 0 || ForceDisp32) {
392 emitDisplacementField(DispForReloc, DispVal, PCAdj);
397 static unsigned sizeOfImm(const TargetInstrDesc *Desc) {
398 switch (Desc->TSFlags & X86II::ImmMask) {
399 case X86II::Imm8: return 1;
400 case X86II::Imm16: return 2;
401 case X86II::Imm32: return 4;
402 case X86II::Imm64: return 8;
403 default: assert(0 && "Immediate size not set!");
408 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended register?
409 /// e.g. r8, xmm8, etc.
410 bool Emitter::isX86_64ExtendedReg(const MachineOperand &MO) {
411 if (!MO.isRegister()) return false;
412 switch (MO.getReg()) {
414 case X86::R8: case X86::R9: case X86::R10: case X86::R11:
415 case X86::R12: case X86::R13: case X86::R14: case X86::R15:
416 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D:
417 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D:
418 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W:
419 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W:
420 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B:
421 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B:
422 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
423 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
429 inline static bool isX86_64NonExtLowByteReg(unsigned reg) {
430 return (reg == X86::SPL || reg == X86::BPL ||
431 reg == X86::SIL || reg == X86::DIL);
434 /// determineREX - Determine if the MachineInstr has to be encoded with a X86-64
435 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
436 /// size, and 3) use of X86-64 extended registers.
437 unsigned Emitter::determineREX(const MachineInstr &MI) {
439 const TargetInstrDesc &Desc = MI.getDesc();
441 // Pseudo instructions do not need REX prefix byte.
442 if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
444 if (Desc.TSFlags & X86II::REX_W)
447 unsigned NumOps = Desc.getNumOperands();
449 bool isTwoAddr = NumOps > 1 &&
450 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
452 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
453 unsigned i = isTwoAddr ? 1 : 0;
454 for (unsigned e = NumOps; i != e; ++i) {
455 const MachineOperand& MO = MI.getOperand(i);
456 if (MO.isRegister()) {
457 unsigned Reg = MO.getReg();
458 if (isX86_64NonExtLowByteReg(Reg))
463 switch (Desc.TSFlags & X86II::FormMask) {
464 case X86II::MRMInitReg:
465 if (isX86_64ExtendedReg(MI.getOperand(0)))
466 REX |= (1 << 0) | (1 << 2);
468 case X86II::MRMSrcReg: {
469 if (isX86_64ExtendedReg(MI.getOperand(0)))
471 i = isTwoAddr ? 2 : 1;
472 for (unsigned e = NumOps; i != e; ++i) {
473 const MachineOperand& MO = MI.getOperand(i);
474 if (isX86_64ExtendedReg(MO))
479 case X86II::MRMSrcMem: {
480 if (isX86_64ExtendedReg(MI.getOperand(0)))
483 i = isTwoAddr ? 2 : 1;
484 for (; i != NumOps; ++i) {
485 const MachineOperand& MO = MI.getOperand(i);
486 if (MO.isRegister()) {
487 if (isX86_64ExtendedReg(MO))
494 case X86II::MRM0m: case X86II::MRM1m:
495 case X86II::MRM2m: case X86II::MRM3m:
496 case X86II::MRM4m: case X86II::MRM5m:
497 case X86II::MRM6m: case X86II::MRM7m:
498 case X86II::MRMDestMem: {
499 unsigned e = isTwoAddr ? 5 : 4;
500 i = isTwoAddr ? 1 : 0;
501 if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e)))
504 for (; i != e; ++i) {
505 const MachineOperand& MO = MI.getOperand(i);
506 if (MO.isRegister()) {
507 if (isX86_64ExtendedReg(MO))
515 if (isX86_64ExtendedReg(MI.getOperand(0)))
517 i = isTwoAddr ? 2 : 1;
518 for (unsigned e = NumOps; i != e; ++i) {
519 const MachineOperand& MO = MI.getOperand(i);
520 if (isX86_64ExtendedReg(MO))
530 void Emitter::emitInstruction(const MachineInstr &MI,
531 const TargetInstrDesc *Desc) {
532 unsigned Opcode = Desc->Opcode;
534 // Emit the repeat opcode prefix as needed.
535 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) MCE.emitByte(0xF3);
537 // Emit the operand size opcode prefix as needed.
538 if (Desc->TSFlags & X86II::OpSize) MCE.emitByte(0x66);
540 // Emit the address size opcode prefix as needed.
541 if (Desc->TSFlags & X86II::AdSize) MCE.emitByte(0x67);
543 bool Need0FPrefix = false;
544 switch (Desc->TSFlags & X86II::Op0Mask) {
546 Need0FPrefix = true; // Two-byte opcode prefix
556 case X86II::REP: break; // already handled.
557 case X86II::XS: // F3 0F
561 case X86II::XD: // F2 0F
565 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
566 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
568 (((Desc->TSFlags & X86II::Op0Mask)-X86II::D8)
569 >> X86II::Op0Shift));
570 break; // Two-byte opcode prefix
571 default: assert(0 && "Invalid prefix!");
572 case 0: break; // No prefix!
577 unsigned REX = determineREX(MI);
579 MCE.emitByte(0x40 | REX);
582 // 0x0F escape code must be emitted just before the opcode.
586 // If this is a two-address instruction, skip one of the register operands.
587 unsigned NumOps = Desc->getNumOperands();
589 if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
592 unsigned char BaseOpcode = II->getBaseOpcodeFor(Desc);
593 switch (Desc->TSFlags & X86II::FormMask) {
594 default: assert(0 && "Unknown FormMask value in X86 MachineCodeEmitter!");
596 // Remember the current PC offset, this is the PIC relocation
601 assert(0 && "psuedo instructions should be removed before code emission");
602 case TargetInstrInfo::INLINEASM:
603 assert(0 && "JIT does not support inline asm!\n");
604 case TargetInstrInfo::LABEL:
605 assert(0 && "JIT does not support meta labels!\n");
606 case X86::IMPLICIT_DEF_GR8:
607 case X86::IMPLICIT_DEF_GR16:
608 case X86::IMPLICIT_DEF_GR32:
609 case X86::IMPLICIT_DEF_GR64:
610 case X86::IMPLICIT_DEF_FR32:
611 case X86::IMPLICIT_DEF_FR64:
612 case X86::IMPLICIT_DEF_VR64:
613 case X86::IMPLICIT_DEF_VR128:
614 case X86::FP_REG_KILL:
617 case X86::MOVPC32r: {
618 // This emits the "call" portion of this pseudo instruction.
619 MCE.emitByte(BaseOpcode);
620 emitConstant(0, sizeOfImm(Desc));
621 // Remember PIC base.
622 PICBaseOffset = MCE.getCurrentPCOffset();
623 X86JITInfo *JTI = dynamic_cast<X86JITInfo*>(TM.getJITInfo());
624 JTI->setPICBase(MCE.getCurrentPCValue());
632 MCE.emitByte(BaseOpcode);
634 if (CurOp != NumOps) {
635 const MachineOperand &MO = MI.getOperand(CurOp++);
636 if (MO.isMachineBasicBlock()) {
637 emitPCRelativeBlockAddress(MO.getMBB());
638 } else if (MO.isGlobalAddress()) {
639 bool NeedStub = (Is64BitMode && TM.getCodeModel() == CodeModel::Large)
640 || Opcode == X86::TAILJMPd;
641 emitGlobalAddress(MO.getGlobal(), X86::reloc_pcrel_word,
643 } else if (MO.isExternalSymbol()) {
644 emitExternalSymbolAddress(MO.getSymbolName(), X86::reloc_pcrel_word);
645 } else if (MO.isImmediate()) {
646 emitConstant(MO.getImm(), sizeOfImm(Desc));
648 assert(0 && "Unknown RawFrm operand!");
653 case X86II::AddRegFrm:
654 MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++).getReg()));
656 if (CurOp != NumOps) {
657 const MachineOperand &MO1 = MI.getOperand(CurOp++);
658 unsigned Size = sizeOfImm(Desc);
659 if (MO1.isImmediate())
660 emitConstant(MO1.getImm(), Size);
662 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
663 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
664 if (Opcode == X86::MOV64ri)
665 rt = X86::reloc_absolute_dword; // FIXME: add X86II flag?
666 if (MO1.isGlobalAddress()) {
667 bool NeedStub = isa<Function>(MO1.getGlobal());
668 bool isLazy = gvNeedsLazyPtr(MO1.getGlobal());
669 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
671 } else if (MO1.isExternalSymbol())
672 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
673 else if (MO1.isConstantPoolIndex())
674 emitConstPoolAddress(MO1.getIndex(), rt);
675 else if (MO1.isJumpTableIndex())
676 emitJumpTableAddress(MO1.getIndex(), rt);
681 case X86II::MRMDestReg: {
682 MCE.emitByte(BaseOpcode);
683 emitRegModRMByte(MI.getOperand(CurOp).getReg(),
684 getX86RegNum(MI.getOperand(CurOp+1).getReg()));
687 emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
690 case X86II::MRMDestMem: {
691 MCE.emitByte(BaseOpcode);
692 emitMemModRMByte(MI, CurOp, getX86RegNum(MI.getOperand(CurOp+4).getReg()));
695 emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
699 case X86II::MRMSrcReg:
700 MCE.emitByte(BaseOpcode);
701 emitRegModRMByte(MI.getOperand(CurOp+1).getReg(),
702 getX86RegNum(MI.getOperand(CurOp).getReg()));
705 emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
708 case X86II::MRMSrcMem: {
709 intptr_t PCAdj = (CurOp+5 != NumOps) ? sizeOfImm(Desc) : 0;
711 MCE.emitByte(BaseOpcode);
712 emitMemModRMByte(MI, CurOp+1, getX86RegNum(MI.getOperand(CurOp).getReg()),
716 emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
720 case X86II::MRM0r: case X86II::MRM1r:
721 case X86II::MRM2r: case X86II::MRM3r:
722 case X86II::MRM4r: case X86II::MRM5r:
723 case X86II::MRM6r: case X86II::MRM7r:
724 MCE.emitByte(BaseOpcode);
725 emitRegModRMByte(MI.getOperand(CurOp++).getReg(),
726 (Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
728 if (CurOp != NumOps) {
729 const MachineOperand &MO1 = MI.getOperand(CurOp++);
730 unsigned Size = sizeOfImm(Desc);
731 if (MO1.isImmediate())
732 emitConstant(MO1.getImm(), Size);
734 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
735 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
736 if (Opcode == X86::MOV64ri32)
737 rt = X86::reloc_absolute_word; // FIXME: add X86II flag?
738 if (MO1.isGlobalAddress()) {
739 bool NeedStub = isa<Function>(MO1.getGlobal());
740 bool isLazy = gvNeedsLazyPtr(MO1.getGlobal());
741 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
743 } else if (MO1.isExternalSymbol())
744 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
745 else if (MO1.isConstantPoolIndex())
746 emitConstPoolAddress(MO1.getIndex(), rt);
747 else if (MO1.isJumpTableIndex())
748 emitJumpTableAddress(MO1.getIndex(), rt);
753 case X86II::MRM0m: case X86II::MRM1m:
754 case X86II::MRM2m: case X86II::MRM3m:
755 case X86II::MRM4m: case X86II::MRM5m:
756 case X86II::MRM6m: case X86II::MRM7m: {
757 intptr_t PCAdj = (CurOp+4 != NumOps) ?
758 (MI.getOperand(CurOp+4).isImmediate() ? sizeOfImm(Desc) : 4) : 0;
760 MCE.emitByte(BaseOpcode);
761 emitMemModRMByte(MI, CurOp, (Desc->TSFlags & X86II::FormMask)-X86II::MRM0m,
765 if (CurOp != NumOps) {
766 const MachineOperand &MO = MI.getOperand(CurOp++);
767 unsigned Size = sizeOfImm(Desc);
768 if (MO.isImmediate())
769 emitConstant(MO.getImm(), Size);
771 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
772 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
773 if (Opcode == X86::MOV64mi32)
774 rt = X86::reloc_absolute_word; // FIXME: add X86II flag?
775 if (MO.isGlobalAddress()) {
776 bool NeedStub = isa<Function>(MO.getGlobal());
777 bool isLazy = gvNeedsLazyPtr(MO.getGlobal());
778 emitGlobalAddress(MO.getGlobal(), rt, MO.getOffset(), 0,
780 } else if (MO.isExternalSymbol())
781 emitExternalSymbolAddress(MO.getSymbolName(), rt);
782 else if (MO.isConstantPoolIndex())
783 emitConstPoolAddress(MO.getIndex(), rt);
784 else if (MO.isJumpTableIndex())
785 emitJumpTableAddress(MO.getIndex(), rt);
791 case X86II::MRMInitReg:
792 MCE.emitByte(BaseOpcode);
793 // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
794 emitRegModRMByte(MI.getOperand(CurOp).getReg(),
795 getX86RegNum(MI.getOperand(CurOp).getReg()));
800 assert((Desc->isVariadic() || CurOp == NumOps) && "Unknown encoding!");